{
  "design": {
    "design_info": {
      "boundary_crc": "0x82F7CD001DE2BC1E",
      "device": "xc7a35tcpg236-1",
      "name": "loopback_I2S",
      "rev_ctrl_bd_flag": "RevCtrlBdOff",
      "synth_flow_mode": "None",
      "tool_version": "2020.2",
      "validated": "true"
    },
    "design_tree": {
      "proc_sys_reset_0": "",
      "clk_wiz_0": "",
      "proc_sys_reset_1": "",
      "axis_dual_i2s_0": "",
      "system_ila_0": ""
    },
    "ports": {
      "reset": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_HIGH"
          }
        }
      },
      "sys_clock": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "loopback_I2S_sys_clock",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000"
          },
          "FREQ_TOLERANCE_HZ": {
            "value": "0",
            "value_src": "default"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.000"
          }
        }
      },
      "rx_sdin_0": {
        "direction": "I"
      },
      "tx_mclk_0": {
        "direction": "O"
      },
      "tx_lrck_0": {
        "direction": "O"
      },
      "tx_sclk_0": {
        "direction": "O"
      },
      "tx_sdout_0": {
        "direction": "O"
      },
      "rx_mclk_0": {
        "direction": "O"
      },
      "rx_lrck_0": {
        "direction": "O"
      },
      "rx_sclk_0": {
        "direction": "O"
      }
    },
    "components": {
      "proc_sys_reset_0": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "loopback_I2S_proc_sys_reset_0_0",
        "xci_path": "ip\\loopback_I2S_proc_sys_reset_0_0\\loopback_I2S_proc_sys_reset_0_0.xci",
        "inst_hier_path": "proc_sys_reset_0",
        "parameters": {
          "RESET_BOARD_INTERFACE": {
            "value": "reset"
          },
          "USE_BOARD_FLOW": {
            "value": "true"
          }
        }
      },
      "clk_wiz_0": {
        "vlnv": "xilinx.com:ip:clk_wiz:6.0",
        "xci_name": "loopback_I2S_clk_wiz_0_0",
        "xci_path": "ip\\loopback_I2S_clk_wiz_0_0\\loopback_I2S_clk_wiz_0_0.xci",
        "inst_hier_path": "clk_wiz_0",
        "parameters": {
          "CLKOUT1_JITTER": {
            "value": "149.337"
          },
          "CLKOUT1_PHASE_ERROR": {
            "value": "122.577"
          },
          "CLKOUT2_JITTER": {
            "value": "201.826"
          },
          "CLKOUT2_PHASE_ERROR": {
            "value": "122.577"
          },
          "CLKOUT2_REQUESTED_OUT_FREQ": {
            "value": "22.579"
          },
          "CLKOUT2_USED": {
            "value": "true"
          },
          "CLK_IN1_BOARD_INTERFACE": {
            "value": "sys_clock"
          },
          "MMCM_CLKFBOUT_MULT_F": {
            "value": "7.000"
          },
          "MMCM_CLKOUT0_DIVIDE_F": {
            "value": "7.000"
          },
          "MMCM_CLKOUT1_DIVIDE": {
            "value": "31"
          },
          "NUM_OUT_CLKS": {
            "value": "2"
          },
          "USE_BOARD_FLOW": {
            "value": "true"
          }
        }
      },
      "proc_sys_reset_1": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "loopback_I2S_proc_sys_reset_0_1",
        "xci_path": "ip\\loopback_I2S_proc_sys_reset_0_1\\loopback_I2S_proc_sys_reset_0_1.xci",
        "inst_hier_path": "proc_sys_reset_1",
        "parameters": {
          "RESET_BOARD_INTERFACE": {
            "value": "reset"
          },
          "USE_BOARD_FLOW": {
            "value": "true"
          }
        }
      },
      "axis_dual_i2s_0": {
        "vlnv": "DigiLAB:ip:axis_dual_i2s:1.0",
        "xci_name": "loopback_I2S_axis_dual_i2s_0_0",
        "xci_path": "ip\\loopback_I2S_axis_dual_i2s_0_0\\loopback_I2S_axis_dual_i2s_0_0.xci",
        "inst_hier_path": "axis_dual_i2s_0"
      },
      "system_ila_0": {
        "vlnv": "xilinx.com:ip:system_ila:1.1",
        "xci_name": "loopback_I2S_system_ila_0_0",
        "xci_path": "ip\\loopback_I2S_system_ila_0_0\\loopback_I2S_system_ila_0_0.xci",
        "inst_hier_path": "system_ila_0",
        "parameters": {
          "C_SLOT_0_INTF_TYPE": {
            "value": "xilinx.com:interface:axis_rtl:1.0"
          }
        },
        "interface_ports": {
          "SLOT_0_AXIS": {
            "mode": "Monitor",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
          }
        }
      }
    },
    "interface_nets": {
      "axis_dual_i2s_0_m_axis": {
        "interface_ports": [
          "axis_dual_i2s_0/s_axis",
          "axis_dual_i2s_0/m_axis",
          "system_ila_0/SLOT_0_AXIS"
        ]
      }
    },
    "nets": {
      "reset_1": {
        "ports": [
          "reset",
          "proc_sys_reset_0/ext_reset_in",
          "clk_wiz_0/reset",
          "proc_sys_reset_1/ext_reset_in"
        ]
      },
      "sys_clock_1": {
        "ports": [
          "sys_clock",
          "clk_wiz_0/clk_in1"
        ]
      },
      "clk_wiz_0_locked": {
        "ports": [
          "clk_wiz_0/locked",
          "proc_sys_reset_0/dcm_locked",
          "proc_sys_reset_1/dcm_locked"
        ]
      },
      "clk_wiz_0_clk_out1": {
        "ports": [
          "clk_wiz_0/clk_out1",
          "system_ila_0/clk",
          "axis_dual_i2s_0/aclk",
          "proc_sys_reset_0/slowest_sync_clk"
        ]
      },
      "clk_wiz_0_clk_out2": {
        "ports": [
          "clk_wiz_0/clk_out2",
          "proc_sys_reset_1/slowest_sync_clk",
          "axis_dual_i2s_0/i2s_clk"
        ]
      },
      "proc_sys_reset_0_peripheral_aresetn": {
        "ports": [
          "proc_sys_reset_0/peripheral_aresetn",
          "system_ila_0/resetn",
          "axis_dual_i2s_0/aresetn"
        ]
      },
      "proc_sys_reset_1_peripheral_aresetn": {
        "ports": [
          "proc_sys_reset_1/peripheral_aresetn",
          "axis_dual_i2s_0/i2s_resetn"
        ]
      },
      "rx_sdin_0_1": {
        "ports": [
          "rx_sdin_0",
          "axis_dual_i2s_0/rx_sdin"
        ]
      },
      "axis_dual_i2s_0_tx_mclk": {
        "ports": [
          "axis_dual_i2s_0/tx_mclk",
          "tx_mclk_0"
        ]
      },
      "axis_dual_i2s_0_tx_lrck": {
        "ports": [
          "axis_dual_i2s_0/tx_lrck",
          "tx_lrck_0"
        ]
      },
      "axis_dual_i2s_0_tx_sclk": {
        "ports": [
          "axis_dual_i2s_0/tx_sclk",
          "tx_sclk_0"
        ]
      },
      "axis_dual_i2s_0_tx_sdout": {
        "ports": [
          "axis_dual_i2s_0/tx_sdout",
          "tx_sdout_0"
        ]
      },
      "axis_dual_i2s_0_rx_mclk": {
        "ports": [
          "axis_dual_i2s_0/rx_mclk",
          "rx_mclk_0"
        ]
      },
      "axis_dual_i2s_0_rx_lrck": {
        "ports": [
          "axis_dual_i2s_0/rx_lrck",
          "rx_lrck_0"
        ]
      },
      "axis_dual_i2s_0_rx_sclk": {
        "ports": [
          "axis_dual_i2s_0/rx_sclk",
          "rx_sclk_0"
        ]
      }
    }
  }
}