diff --git a/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr b/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr
index d4eb671..87b78e0 100644
--- a/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr
+++ b/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr
@@ -47,7 +47,7 @@
-
+
diff --git a/LAB1/src/KittCarPWM.vhd b/LAB1/src/KittCarPWM.vhd
index e97ba26..b1741f8 100644
--- a/LAB1/src/KittCarPWM.vhd
+++ b/LAB1/src/KittCarPWM.vhd
@@ -1,37 +1,133 @@
---------- DEFAULT LIBRARY ---------
-library IEEE;
- use IEEE.STD_LOGIC_1164.all;
- use IEEE.NUMERIC_STD.ALL;
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
------------------------------------
-entity KittCarPWM is
- Generic (
+ENTITY KittCarPWM IS
+ GENERIC (
+ CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
+ MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
- CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
- MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
+ NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
+ NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16; -- Number of output LEDs
- NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
- NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16; -- Number of output LEDs
+ TAIL_LENGTH : INTEGER RANGE 1 TO 16 := 4 -- Tail length
+ );
+ PORT (
- TAIL_LENGTH : INTEGER RANGE 1 TO 16 := 4 -- Tail length
- );
- Port (
+ ------- Reset/Clock --------
+ reset : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ ----------------------------
- ------- Reset/Clock --------
- reset : IN STD_LOGIC;
- clk : IN STD_LOGIC;
- ----------------------------
+ -------- LEDs/SWs ----------
+ sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3
+ led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3
+ ----------------------------
- -------- LEDs/SWs ----------
- sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS-1 downto 0); -- Switches avaiable on Basys3
- leds : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS-1 downto 0) -- LEDs avaiable on Basys3
- ----------------------------
+ );
+END KittCarPWM;
- );
-end KittCarPWM;
+ARCHITECTURE Behavioral OF KittCarPWM IS
+ COMPONENT PulseWidthModulator
+ GENERIC (
+ BIT_LENGTH : INTEGER RANGE 1 TO 16;
+ T_ON_INIT : POSITIVE;
+ PERIOD_INIT : POSITIVE;
+ PWM_INIT : STD_LOGIC
+ );
+ PORT (
+ reset : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
-architecture Behavioral of KittCarPWM is
+ Ton : IN STD_LOGIC_VECTOR(BIT_LENGTH - 1 DOWNTO 0);
+ Period : IN STD_LOGIC_VECTOR(BIT_LENGTH - 1 DOWNTO 0);
+ PWM : OUT STD_LOGIC
+ );
+ END COMPONENT;
-begin
+ TYPE led_reg IS ARRAY (TAIL_LENGTH - 1 DOWNTO 0) OF INTEGER RANGE 0 TO led'HIGH;
-end Behavioral;
+ CONSTANT MIN_KITT_CAR_STEP_NS : UNSIGNED(46 DOWNTO 0) := to_unsigned(MIN_KITT_CAR_STEP_MS * 1000000, 47);
+ CONSTANT BIT_LENGTH : INTEGER RANGE 1 TO 16 := 8;
+
+ SIGNAL leds_sr : led_reg := (OTHERS => 0);
+ SIGNAL leds_pwm : STD_LOGIC_VECTOR(TAIL_LENGTH - 1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL led_sig : STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL n_period : UNSIGNED(NUM_OF_SWS DOWNTO 0) := to_unsigned(1, NUM_OF_SWS + 1);
+ SIGNAL up : STD_LOGIC := '1';
+BEGIN
+
+ -- Instantiate the PWM
+ PWM : FOR i IN 1 TO TAIL_LENGTH GENERATE
+ BEGIN
+ PWM : PulseWidthModulator
+ GENERIC MAP(
+ BIT_LENGTH => BIT_LENGTH,
+ T_ON_INIT => 64,
+ PERIOD_INIT => 128,
+ PWM_INIT => '0'
+ )
+ PORT MAP(
+ reset => reset,
+ clk => clk,
+ Ton => STD_LOGIC_VECTOR(to_unsigned(i, BIT_LENGTH)),
+ Period => STD_LOGIC_VECTOR(to_unsigned(TAIL_LENGTH - 1, BIT_LENGTH)),
+ PWM => leds_pwm(i - 1)
+ );
+ END GENERATE;
+
+ -- Sincronous logic
+ PROCESS (clk, reset)
+ VARIABLE counter : UNSIGNED(46 DOWNTO 0) := (OTHERS => '0');
+ BEGIN
+ IF reset = '1' THEN
+ leds_sr <= (OTHERS => 0);
+ led_sig <= (OTHERS => '0');
+ counter := (OTHERS => '0');
+ ELSIF rising_edge(clk) THEN
+
+ -- Kitt logic
+ IF leds_sr(TAIL_LENGTH - 1) = 15 THEN
+ up <= '0';
+ ELSIF leds_sr(TAIL_LENGTH - 1) = 0 THEN
+ up <= '1';
+ END IF;
+
+ -- Increment the counter
+ counter := counter + to_unsigned(CLK_PERIOD_NS, counter'LENGTH);
+
+ -- Calculate the number of periods
+ IF counter >= (MIN_KITT_CAR_STEP_NS * n_period) THEN
+
+ -- Shift the leds
+ IF up = '1' THEN
+ leds_sr <= (leds_sr(TAIL_LENGTH - 1) + 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
+ ELSIF up = '0' THEN
+ leds_sr <= (leds_sr(TAIL_LENGTH - 1) - 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
+ END IF;
+
+ -- Reset leg_sig
+ led_sig <= (OTHERS => '0');
+
+ -- Assign the leds
+ FOR i IN 0 TO TAIL_LENGTH - 1 LOOP
+ led_sig(leds_sr(i)) <= leds_pwm(i);
+ END LOOP;
+
+ -- Reset the counter
+ counter := (OTHERS => '0');
+ END IF;
+ END IF;
+ END PROCESS;
+
+ -- Handle the switch
+ PROCESS (sw)
+ BEGIN
+ n_period <= unsigned('0' & sw) + 1;
+ END PROCESS;
+
+ led <= led_sig;
+
+END Behavioral;
\ No newline at end of file
diff --git a/LAB1/src/PulseWidthModulator.vhd b/LAB1/src/PulseWidthModulator.vhd
new file mode 100644
index 0000000..bd7c9d5
--- /dev/null
+++ b/LAB1/src/PulseWidthModulator.vhd
@@ -0,0 +1,83 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 07.03.2025 15:23:11
+-- Design Name:
+-- Module Name: PulseWidthModulator - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PulseWidthModulator is
+ Generic(
+ BIT_LENGTH : INTEGER RANGE 1 to 16 := 8;
+ T_ON_INIT : POSITIVE := 64;
+ PERIOD_INIT : POSITIVE := 128;
+ PWM_INIT : STD_LOGIC := '0'
+ );
+ Port (
+ reset : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+
+ Ton : IN std_logic_vector(BIT_LENGTH-1 downto 0);
+ Period : IN std_logic_vector(BIT_LENGTH-1 downto 0);
+ PWM : OUT std_logic
+ );
+ end PulseWidthModulator;
+
+architecture Behavioral of PulseWidthModulator is
+ signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0');
+ signal pwm_out : std_logic;
+begin
+
+ process(clk, reset)
+ begin
+ if reset = '1' then
+ counter <= (others => '0');
+ pwm_out <= '0'; -- Assicura PWM spento al reset
+ elsif rising_edge(clk) then
+ if counter = unsigned(period) then
+ counter <= (others => '0'); -- Reset counter
+ else
+ counter <= counter + 1; -- Incrementa il counter
+ end if;
+
+ -- Accendi il PWM all'inizio di ogni ciclo
+ if counter = 0 then
+ pwm_out <= '1';
+ end if;
+
+ -- Spegni il PWM quando il contatore raggiunge Ton
+ if counter = unsigned(Ton) then
+ pwm_out <= '0';
+ end if;
+ end if;
+ end process;
+
+ PWM <= pwm_out; -- Output PWM
+
+end Behavioral;
+
diff --git a/LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr b/LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr
new file mode 100644
index 0000000..95b970f
--- /dev/null
+++ b/LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr
@@ -0,0 +1,213 @@
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