From 038ea732913ca430168d858da87a96eb1f743b2b Mon Sep 17 00:00:00 2001
From: Davide <davidecavagnola@gmail.com>
Date: Fri, 21 Mar 2025 16:20:55 +0100
Subject: [PATCH] Add PulseWidthModulator and update KittCarPWM; adjust
 simulation launch time

---
 .../lab0_pulse_width_modulator.xpr            |   2 +-
 LAB1/src/KittCarPWM.vhd                       | 146 ++++++++++--
 LAB1/src/PulseWidthModulator.vhd              |  83 +++++++
 .../lab1_kit_car_pwm/lab1_kit_car_pwm.xpr     | 213 ++++++++++++++++++
 4 files changed, 418 insertions(+), 26 deletions(-)
 create mode 100644 LAB1/src/PulseWidthModulator.vhd
 create mode 100644 LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr

diff --git a/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr b/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr
index d4eb671..87b78e0 100644
--- a/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr
+++ b/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr
@@ -47,7 +47,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="10"/>
+    <Option Name="WTXSimLaunchSim" Val="12"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
diff --git a/LAB1/src/KittCarPWM.vhd b/LAB1/src/KittCarPWM.vhd
index e97ba26..b1741f8 100644
--- a/LAB1/src/KittCarPWM.vhd
+++ b/LAB1/src/KittCarPWM.vhd
@@ -1,37 +1,133 @@
 ---------- DEFAULT LIBRARY ---------
-library IEEE;
-	use IEEE.STD_LOGIC_1164.all;
-	use IEEE.NUMERIC_STD.ALL;
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
 ------------------------------------
 
-entity KittCarPWM is
-	Generic (
+ENTITY KittCarPWM IS
+    GENERIC (
+        CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds
+        MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
 
-		CLK_PERIOD_NS			:	POSITIVE	RANGE	1	TO	100     := 10;	-- clk period in nanoseconds
-		MIN_KITT_CAR_STEP_MS	:	POSITIVE	RANGE	1	TO	2000    := 1;	-- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t)
+        NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches
+        NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16; -- Number of output LEDs
 
-		NUM_OF_SWS				:	INTEGER	RANGE	1 TO 16 := 16;	-- Number of input switches
-		NUM_OF_LEDS				:	INTEGER	RANGE	1 TO 16 := 16;	-- Number of output LEDs
+        TAIL_LENGTH : INTEGER RANGE 1 TO 16 := 4 -- Tail length
+    );
+    PORT (
 
-		TAIL_LENGTH				:	INTEGER	RANGE	1 TO 16	:= 4	-- Tail length
-	);
-	Port (
+        ------- Reset/Clock --------
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        ----------------------------
 
-		------- Reset/Clock --------
-		reset	:	IN	STD_LOGIC;
-		clk		:	IN	STD_LOGIC;
-		----------------------------
+        -------- LEDs/SWs ----------
+        sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3
+        led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3
+        ----------------------------
 
-		-------- LEDs/SWs ----------
-		sw		:	IN	STD_LOGIC_VECTOR(NUM_OF_SWS-1 downto 0);	-- Switches avaiable on Basys3
-		leds	:	OUT	STD_LOGIC_VECTOR(NUM_OF_LEDS-1 downto 0)	-- LEDs avaiable on Basys3
-		----------------------------
+    );
+END KittCarPWM;
 
-	);
-end KittCarPWM;
+ARCHITECTURE Behavioral OF KittCarPWM IS
+    COMPONENT PulseWidthModulator
+        GENERIC (
+            BIT_LENGTH : INTEGER RANGE 1 TO 16;
+            T_ON_INIT : POSITIVE;
+            PERIOD_INIT : POSITIVE;
+            PWM_INIT : STD_LOGIC
+        );
+        PORT (
+            reset : IN STD_LOGIC;
+            clk : IN STD_LOGIC;
 
-architecture Behavioral of KittCarPWM is
+            Ton : IN STD_LOGIC_VECTOR(BIT_LENGTH - 1 DOWNTO 0);
+            Period : IN STD_LOGIC_VECTOR(BIT_LENGTH - 1 DOWNTO 0);
+            PWM : OUT STD_LOGIC
+        );
+    END COMPONENT;
 
-begin
+    TYPE led_reg IS ARRAY (TAIL_LENGTH - 1 DOWNTO 0) OF INTEGER RANGE 0 TO led'HIGH;
 
-end Behavioral;
+    CONSTANT MIN_KITT_CAR_STEP_NS : UNSIGNED(46 DOWNTO 0) := to_unsigned(MIN_KITT_CAR_STEP_MS * 1000000, 47);
+    CONSTANT BIT_LENGTH : INTEGER RANGE 1 TO 16 := 8;
+
+    SIGNAL leds_sr : led_reg := (OTHERS => 0);
+    SIGNAL leds_pwm : STD_LOGIC_VECTOR(TAIL_LENGTH - 1 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL led_sig : STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL n_period : UNSIGNED(NUM_OF_SWS DOWNTO 0) := to_unsigned(1, NUM_OF_SWS + 1);
+    SIGNAL up : STD_LOGIC := '1';
+BEGIN
+
+    -- Instantiate the PWM
+    PWM : FOR i IN 1 TO TAIL_LENGTH GENERATE
+    BEGIN
+        PWM : PulseWidthModulator
+        GENERIC MAP(
+            BIT_LENGTH => BIT_LENGTH,
+            T_ON_INIT => 64,
+            PERIOD_INIT => 128,
+            PWM_INIT => '0'
+        )
+        PORT MAP(
+            reset => reset,
+            clk => clk,
+            Ton => STD_LOGIC_VECTOR(to_unsigned(i, BIT_LENGTH)),
+            Period => STD_LOGIC_VECTOR(to_unsigned(TAIL_LENGTH - 1, BIT_LENGTH)),
+            PWM => leds_pwm(i - 1)
+        );
+    END GENERATE;
+
+    -- Sincronous logic
+    PROCESS (clk, reset)
+        VARIABLE counter : UNSIGNED(46 DOWNTO 0) := (OTHERS => '0');
+    BEGIN
+        IF reset = '1' THEN
+            leds_sr <= (OTHERS => 0);
+            led_sig <= (OTHERS => '0');
+            counter := (OTHERS => '0');
+        ELSIF rising_edge(clk) THEN
+
+            -- Kitt logic
+            IF leds_sr(TAIL_LENGTH - 1) = 15 THEN
+                up <= '0';
+            ELSIF leds_sr(TAIL_LENGTH - 1) = 0 THEN
+                up <= '1';
+            END IF;
+
+            -- Increment the counter
+            counter := counter + to_unsigned(CLK_PERIOD_NS, counter'LENGTH);
+
+            -- Calculate the number of periods
+            IF counter >= (MIN_KITT_CAR_STEP_NS * n_period) THEN
+
+                -- Shift the leds
+                IF up = '1' THEN
+                    leds_sr <= (leds_sr(TAIL_LENGTH - 1) + 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
+                ELSIF up = '0' THEN
+                    leds_sr <= (leds_sr(TAIL_LENGTH - 1) - 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
+                END IF;
+
+                -- Reset leg_sig
+                led_sig <= (OTHERS => '0');
+
+                -- Assign the leds
+                FOR i IN 0 TO TAIL_LENGTH - 1 LOOP
+                    led_sig(leds_sr(i)) <= leds_pwm(i);
+                END LOOP;
+
+                -- Reset the counter
+                counter := (OTHERS => '0');
+            END IF;
+        END IF;
+    END PROCESS;
+
+    -- Handle the switch
+    PROCESS (sw)
+    BEGIN
+        n_period <= unsigned('0' & sw) + 1;
+    END PROCESS;
+
+    led <= led_sig;
+
+END Behavioral;
\ No newline at end of file
diff --git a/LAB1/src/PulseWidthModulator.vhd b/LAB1/src/PulseWidthModulator.vhd
new file mode 100644
index 0000000..bd7c9d5
--- /dev/null
+++ b/LAB1/src/PulseWidthModulator.vhd
@@ -0,0 +1,83 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 07.03.2025 15:23:11
+-- Design Name: 
+-- Module Name: PulseWidthModulator - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PulseWidthModulator is
+    Generic(
+        BIT_LENGTH  : INTEGER RANGE 1 to 16 := 8;
+        T_ON_INIT   : POSITIVE := 64;   
+        PERIOD_INIT : POSITIVE := 128;             
+        PWM_INIT    : STD_LOGIC := '0'
+    );
+    Port (
+        reset   : IN STD_LOGIC;
+        clk     : IN STD_LOGIC;
+        
+        Ton     : IN std_logic_vector(BIT_LENGTH-1 downto 0);
+        Period  : IN std_logic_vector(BIT_LENGTH-1 downto 0);
+        PWM     : OUT std_logic
+    );
+ end PulseWidthModulator;
+
+architecture Behavioral of PulseWidthModulator is
+    signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0');
+    signal pwm_out : std_logic;
+begin
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            counter  <= (others => '0');
+            pwm_out  <= '0';  -- Assicura PWM spento al reset
+        elsif rising_edge(clk) then
+            if counter = unsigned(period) then
+                counter <= (others => '0');  -- Reset counter
+            else
+                counter <= counter + 1;  -- Incrementa il counter
+            end if;
+
+            -- Accendi il PWM all'inizio di ogni ciclo
+            if counter = 0 then
+                pwm_out <= '1';  
+            end if;
+
+            -- Spegni il PWM quando il contatore raggiunge Ton
+            if counter = unsigned(Ton) then
+                pwm_out <= '0';
+            end if;
+        end if;
+    end process;
+
+    PWM <= pwm_out; -- Output PWM
+
+end Behavioral;
+
diff --git a/LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr b/LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr
new file mode 100644
index 0000000..95b970f
--- /dev/null
+++ b/LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr
@@ -0,0 +1,213 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="54" Path="C:/DESD/LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="197059de45624c67b2900cf4ced29fd2"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirIES" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirIES" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../src/PulseWidthModulator.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../src/KittCarPWM.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="KittCarPWM"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../../cons/basys3_master.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="KittCarPWM"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="15">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>