Add IPs
This commit is contained in:
685
LAB3/ip/axi4-stream-dual-i2s/component.xml
Normal file
685
LAB3/ip/axi4-stream-dual-i2s/component.xml
Normal file
@@ -0,0 +1,685 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>DigiLAB</spirit:vendor>
|
||||
<spirit:library>ip</spirit:library>
|
||||
<spirit:name>axis_dual_i2s</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>i2s_resetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>i2s_resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.I2S_RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis:s_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>i2s_clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>i2s_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.I2S_CLK.ASSOCIATED_RESET">i2s_resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>axis_i2s_wrapper</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>4daa8100</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>axis_i2s_wrapper</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>4daa8100</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>f6c69e0f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>i2s_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>i2s_resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">23</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">23</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tx_mclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tx_lrck</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tx_sclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tx_sdout</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rx_mclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rx_lrck</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rx_sclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rx_sdin</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/axis_dual_i2s.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/axis_dual_i2s_wrapper.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_f786a01c</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/axis_dual_i2s.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/axis_dual_i2s_wrapper.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/axis_dual_i2s_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_f6c69e0f</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>AXI4-Stream to Dual I2S</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_i2s_wrapper_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Communication_&_Networking/Serial_Interfaces</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>AXI4-Stream to Dual I2S</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:xpmLibraries>
|
||||
<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
|
||||
</xilinx:xpmLibraries>
|
||||
<xilinx:coreRevision>3</xilinx:coreRevision>
|
||||
<xilinx:upgrades>
|
||||
<xilinx:canUpgradeFrom>user.org:user:axis_i2s_wrapper:1.0</xilinx:canUpgradeFrom>
|
||||
</xilinx:upgrades>
|
||||
<xilinx:coreCreationDateTime>2022-05-09T16:06:21Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="nopcore"/>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@ff3941e_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@57b5032_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4fe28858_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@55c0c7db_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5bc11d2d_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3dc95077_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3b5f3776_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@39a7f92_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@b70b378_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6eb3092b_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1e1c742f_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@fbf29a8_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@307c1be8_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@69b79557_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5328f8b_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6a1a36f1_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@75d778b2_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1f5ea28d_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@b934f1f_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@21f5c930_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@47a4b151_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@47db1e11_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3634d390_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@46cec449_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6dbbd91d_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@10a5abf8_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@16c9180a_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@ad6f741_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@e598f3f_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@33507377_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@688403c0_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@65f95694_ARCHIVE_LOCATION">/home/nicola/Documents/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1bb037de_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6258183a_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e9ceb86_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@10a3240b_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4c1a3d50_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@48930c4e_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3b987f9b_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2a34784c_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7a4d5def_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@d06ee0e_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1897799_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4d7cb849_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@38e7d24c_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@393ff311_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3f1c5c1_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7fd352d9_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@35077c7c_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5b33c21b_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@78e74e0_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@225057cd_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@f7e6e3_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@521e410a_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@735e19c4_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@31f93ec8_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@41451e9a_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@15ed1e0e_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4d1ecc32_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2413a732_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5fdd797a_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6b5b8f17_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@709e2958_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@35f14102_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@39177ff_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@55bcd91c_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@bc36efa_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@720d0339_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@26796051_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@36684725_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6521124a_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6cdc4300_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@782fb831_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e9de252_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@434796c4_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@45c1f3f7_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3053fe27"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="383510ae"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="015ca523"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="a7694fdf"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
159
LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s.v
Normal file
159
LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s.v
Normal file
@@ -0,0 +1,159 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Digilent & Politecnico di Milano
|
||||
// Engineer: Arthur Brown, Nicola Corna, Fabio Garzetti, Nicola Lusardi
|
||||
//
|
||||
// Create Date: 14/05/2019
|
||||
// Module Name: axis_i2s
|
||||
// Description: AXI-Stream I2S controller
|
||||
// Generates clocks and select signals required to place each of the ICs on the Pmod I2S2 into slave mode.
|
||||
// Data is 24-bit, shifted one serial clock right from the LRCK boundaries.
|
||||
// This module only supports 44.1KHz sample rate, and expects the frequency of axis_clk to be approx 22.591MHz.
|
||||
// At the end of each I2S frame, a 2-word packet is made available on the AXIS master interface. Further packets will be discarded
|
||||
// until the current packet is accepted by an AXIS slave.
|
||||
// Whenever a 2-word packet is received on the AXIS slave interface, it is transmitted over the I2S interface on the next frame.
|
||||
// Each packet consists of two 3-byte words, starting with left audio channel data, followed by right channel data.
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Revision 0.02 - Use 24-bit interfaces
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module axis_dual_i2s (
|
||||
input wire axis_clk, // require: approx 22.591MHz
|
||||
input wire axis_resetn,
|
||||
|
||||
input wire [23:0] tx_axis_s_data,
|
||||
input wire tx_axis_s_valid,
|
||||
output reg tx_axis_s_ready = 1'b0,
|
||||
input wire tx_axis_s_last,
|
||||
|
||||
output wire [23:0] rx_axis_m_data,
|
||||
output reg rx_axis_m_valid = 1'b0,
|
||||
input wire rx_axis_m_ready,
|
||||
output reg rx_axis_m_last = 1'b0,
|
||||
|
||||
output wire tx_mclk,
|
||||
output wire tx_lrck,
|
||||
output wire tx_sclk,
|
||||
output reg tx_sdout,
|
||||
output wire rx_mclk,
|
||||
output wire rx_lrck,
|
||||
output wire rx_sclk,
|
||||
input wire rx_sdin
|
||||
);
|
||||
reg [8:0] count = 9'd0;
|
||||
localparam EOF_COUNT = 9'd455; // end of full I2S frame
|
||||
|
||||
always@(posedge axis_clk)
|
||||
count <= count + 1;
|
||||
|
||||
wire lrck = count[8];
|
||||
wire sclk = count[2];
|
||||
wire mclk = axis_clk;
|
||||
assign tx_lrck = lrck;
|
||||
assign tx_sclk = sclk;
|
||||
assign tx_mclk = mclk;
|
||||
assign rx_lrck = lrck;
|
||||
assign rx_sclk = sclk;
|
||||
assign rx_mclk = mclk;
|
||||
|
||||
/* AXIS SLAVE CONTROLLER */
|
||||
reg [23:0] tx_data_l = 0;
|
||||
reg [23:0] tx_data_r = 0;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0)
|
||||
tx_axis_s_ready <= 1'b0;
|
||||
else if (tx_axis_s_ready == 1'b1 && tx_axis_s_valid == 1'b1 && tx_axis_s_last == 1'b1) // end of packet, cannot accept data until current one has been transmitted
|
||||
tx_axis_s_ready <= 1'b0;
|
||||
else if (count == 9'b0) // beginning of I2S frame, in order to avoid tearing, cannot accept data until frame complete
|
||||
tx_axis_s_ready <= 1'b0;
|
||||
else if (count == EOF_COUNT) // end of I2S frame, can accept data
|
||||
tx_axis_s_ready <= 1'b1;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0) begin
|
||||
tx_data_r <= 24'b0;
|
||||
tx_data_l <= 24'b0;
|
||||
end else if (tx_axis_s_valid == 1'b1 && tx_axis_s_ready == 1'b1)
|
||||
if (tx_axis_s_last == 1'b1)
|
||||
tx_data_r <= tx_axis_s_data;
|
||||
else
|
||||
tx_data_l <= tx_axis_s_data;
|
||||
|
||||
/* I2S TRANSMIT SHIFT REGISTERS */
|
||||
reg [23:0] tx_data_l_shift = 24'b0;
|
||||
reg [23:0] tx_data_r_shift = 24'b0;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (count == 3'b000000111) begin
|
||||
tx_data_l_shift <= tx_data_l[23:0];
|
||||
tx_data_r_shift <= tx_data_r[23:0];
|
||||
end else if (count[2:0] == 3'b111 && count[7:3] >= 5'd1 && count[7:3] <= 5'd24) begin
|
||||
if (count[8] == 1'b1)
|
||||
tx_data_r_shift <= {tx_data_r_shift[22:0], 1'b0};
|
||||
else
|
||||
tx_data_l_shift <= {tx_data_l_shift[22:0], 1'b0};
|
||||
end
|
||||
|
||||
always@(count, tx_data_l_shift, tx_data_r_shift)
|
||||
if (count[7:3] <= 5'd24 && count[7:3] >= 4'd1)
|
||||
if (count[8] == 1'b1)
|
||||
tx_sdout = tx_data_r_shift[23];
|
||||
else
|
||||
tx_sdout = tx_data_l_shift[23];
|
||||
else
|
||||
tx_sdout = 1'b0;
|
||||
|
||||
/* SYNCHRONIZE DATA IN TO AXIS CLOCK DOMAIN */
|
||||
reg [2:0] din_sync_shift = 3'd0;
|
||||
wire din_sync = din_sync_shift[2];
|
||||
always@(posedge axis_clk)
|
||||
din_sync_shift <= {din_sync_shift[1:0], rx_sdin};
|
||||
|
||||
/* I2S RECEIVE SHIFT REGISTERS */
|
||||
reg [23:0] rx_data_l_shift = 24'b0;
|
||||
reg [23:0] rx_data_r_shift = 24'b0;
|
||||
always@(posedge axis_clk)
|
||||
if (count[2:0] == 3'b011 && count[7:3] <= 5'd24 && count[7:3] >= 5'd1)
|
||||
if (lrck == 1'b1)
|
||||
rx_data_r_shift <= {rx_data_r_shift, din_sync};
|
||||
else
|
||||
rx_data_l_shift <= {rx_data_l_shift, din_sync};
|
||||
|
||||
/* AXIS MASTER CONTROLLER */
|
||||
reg [23:0] rx_data_l = 24'b0;
|
||||
reg [23:0] rx_data_r = 24'b0;
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0) begin
|
||||
rx_data_l <= 24'b0;
|
||||
rx_data_r <= 24'b0;
|
||||
end else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0) begin
|
||||
rx_data_l <= {8'b0, rx_data_l_shift};
|
||||
rx_data_r <= {8'b0, rx_data_r_shift};
|
||||
end
|
||||
|
||||
assign rx_axis_m_data = (rx_axis_m_last == 1'b1) ? rx_data_r : rx_data_l;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0)
|
||||
rx_axis_m_valid <= 1'b0;
|
||||
else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0)
|
||||
rx_axis_m_valid <= 1'b1;
|
||||
else if (rx_axis_m_valid == 1'b1 && rx_axis_m_ready == 1'b1 && rx_axis_m_last == 1'b1)
|
||||
rx_axis_m_valid <= 1'b0;
|
||||
|
||||
always@(posedge axis_clk)
|
||||
if (axis_resetn == 1'b0)
|
||||
rx_axis_m_last <= 1'b0;
|
||||
else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0)
|
||||
rx_axis_m_last <= 1'b0;
|
||||
else if (rx_axis_m_valid == 1'b1 && rx_axis_m_ready == 1'b1)
|
||||
rx_axis_m_last <= ~rx_axis_m_last;
|
||||
|
||||
|
||||
endmodule
|
||||
175
LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s_wrapper.v
Normal file
175
LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s_wrapper.v
Normal file
@@ -0,0 +1,175 @@
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
module axis_i2s_wrapper (
|
||||
input wire i2s_clk, // require: approx 22.591MHz
|
||||
input wire i2s_resetn,
|
||||
|
||||
input wire aclk,
|
||||
input wire aresetn,
|
||||
|
||||
input wire [23:0] s_axis_tdata,
|
||||
input wire s_axis_tvalid,
|
||||
output wire s_axis_tready,
|
||||
input wire s_axis_tlast,
|
||||
|
||||
output wire [23:0] m_axis_tdata,
|
||||
output wire m_axis_tvalid,
|
||||
input wire m_axis_tready,
|
||||
output wire m_axis_tlast,
|
||||
|
||||
output wire tx_mclk,
|
||||
output wire tx_lrck,
|
||||
output wire tx_sclk,
|
||||
output wire tx_sdout,
|
||||
output wire rx_mclk,
|
||||
output wire rx_lrck,
|
||||
output wire rx_sclk,
|
||||
input wire rx_sdin
|
||||
);
|
||||
|
||||
wire [23:0] tx_axis_s_data;
|
||||
wire tx_axis_s_valid;
|
||||
wire tx_axis_s_ready;
|
||||
wire tx_axis_s_last;
|
||||
|
||||
wire [23:0] rx_axis_m_data;
|
||||
wire rx_axis_m_valid;
|
||||
wire rx_axis_m_ready;
|
||||
wire rx_axis_m_last;
|
||||
|
||||
xpm_fifo_axis #(
|
||||
.CDC_SYNC_STAGES(2),
|
||||
.CLOCKING_MODE("independent_clock"),
|
||||
.ECC_MODE("no_ecc"),
|
||||
.FIFO_DEPTH(1024),
|
||||
.FIFO_MEMORY_TYPE("auto"),
|
||||
.PACKET_FIFO("false"),
|
||||
.PROG_EMPTY_THRESH(10),
|
||||
.PROG_FULL_THRESH(10),
|
||||
.RD_DATA_COUNT_WIDTH(1),
|
||||
.RELATED_CLOCKS(0),
|
||||
.SIM_ASSERT_CHK(1),
|
||||
.TDATA_WIDTH(24),
|
||||
.TDEST_WIDTH(1),
|
||||
.TID_WIDTH(1),
|
||||
.TUSER_WIDTH(1),
|
||||
.USE_ADV_FEATURES("0000"),
|
||||
.WR_DATA_COUNT_WIDTH(1)
|
||||
)
|
||||
rx_fifo (
|
||||
.s_aclk(aclk),
|
||||
.s_aresetn(aresetn),
|
||||
.s_axis_tvalid(s_axis_tvalid),
|
||||
.s_axis_tready(s_axis_tready),
|
||||
.s_axis_tdata(s_axis_tdata),
|
||||
.s_axis_tlast(s_axis_tlast),
|
||||
.s_axis_tdest(1'b0),
|
||||
.s_axis_tid(1'b0),
|
||||
.s_axis_tkeep(1'b111),
|
||||
.s_axis_tstrb(1'b111),
|
||||
.s_axis_tuser(1'b0),
|
||||
|
||||
.m_aclk(i2s_clk),
|
||||
.m_axis_tvalid(tx_axis_s_valid),
|
||||
.m_axis_tready(tx_axis_s_ready),
|
||||
.m_axis_tdata(tx_axis_s_data),
|
||||
.m_axis_tlast(tx_axis_s_last),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tuser(),
|
||||
|
||||
.almost_empty_axis(),
|
||||
.almost_full_axis(),
|
||||
.dbiterr_axis(),
|
||||
.prog_empty_axis(),
|
||||
.prog_full_axis(),
|
||||
.rd_data_count_axis(),
|
||||
.sbiterr_axis(),
|
||||
.wr_data_count_axis(),
|
||||
.injectdbiterr_axis(1'b0),
|
||||
.injectsbiterr_axis(1'b0)
|
||||
);
|
||||
|
||||
axis_dual_i2s axis_dual_i2s_inst (
|
||||
.axis_clk(i2s_clk),
|
||||
.axis_resetn(i2s_resetn),
|
||||
|
||||
.tx_axis_s_data(tx_axis_s_data),
|
||||
.tx_axis_s_valid(tx_axis_s_valid),
|
||||
.tx_axis_s_ready(tx_axis_s_ready),
|
||||
.tx_axis_s_last(tx_axis_s_last),
|
||||
|
||||
.rx_axis_m_data(rx_axis_m_data),
|
||||
.rx_axis_m_valid(rx_axis_m_valid),
|
||||
.rx_axis_m_ready(rx_axis_m_ready),
|
||||
.rx_axis_m_last(rx_axis_m_last),
|
||||
|
||||
.tx_mclk(tx_mclk),
|
||||
.tx_lrck(tx_lrck),
|
||||
.tx_sclk(tx_sclk),
|
||||
.tx_sdout(tx_sdout),
|
||||
.rx_mclk(rx_mclk),
|
||||
.rx_lrck(rx_lrck),
|
||||
.rx_sclk(rx_sclk),
|
||||
.rx_sdin(rx_sdin)
|
||||
);
|
||||
|
||||
xpm_fifo_axis #(
|
||||
.CDC_SYNC_STAGES(2),
|
||||
.CLOCKING_MODE("independent_clock"),
|
||||
.ECC_MODE("no_ecc"),
|
||||
.FIFO_DEPTH(1024),
|
||||
.FIFO_MEMORY_TYPE("auto"),
|
||||
.PACKET_FIFO("false"),
|
||||
.PROG_EMPTY_THRESH(10),
|
||||
.PROG_FULL_THRESH(10),
|
||||
.RD_DATA_COUNT_WIDTH(1),
|
||||
.RELATED_CLOCKS(0),
|
||||
.SIM_ASSERT_CHK(1),
|
||||
.TDATA_WIDTH(24),
|
||||
.TDEST_WIDTH(1),
|
||||
.TID_WIDTH(1),
|
||||
.TUSER_WIDTH(1),
|
||||
.USE_ADV_FEATURES("0000"),
|
||||
.WR_DATA_COUNT_WIDTH(1)
|
||||
)
|
||||
tx_fifo (
|
||||
.s_aclk(i2s_clk),
|
||||
.s_aresetn(i2s_resetn),
|
||||
.s_axis_tvalid(rx_axis_m_valid),
|
||||
.s_axis_tready(rx_axis_m_ready),
|
||||
.s_axis_tdata(rx_axis_m_data),
|
||||
.s_axis_tlast(rx_axis_m_last),
|
||||
.s_axis_tdest(1'b0),
|
||||
.s_axis_tid(1'b0),
|
||||
.s_axis_tkeep(1'b111),
|
||||
.s_axis_tstrb(1'b111),
|
||||
.s_axis_tuser(1'b0),
|
||||
|
||||
.m_aclk(aclk),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tready(m_axis_tready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tuser(),
|
||||
|
||||
.almost_empty_axis(),
|
||||
.almost_full_axis(),
|
||||
.dbiterr_axis(),
|
||||
.prog_empty_axis(),
|
||||
.prog_full_axis(),
|
||||
.rd_data_count_axis(),
|
||||
.sbiterr_axis(),
|
||||
.wr_data_count_axis(),
|
||||
.injectdbiterr_axis(1'b0),
|
||||
.injectsbiterr_axis(1'b0)
|
||||
);
|
||||
|
||||
endmodule
|
||||
12
LAB3/ip/axi4-stream-dual-i2s/xgui/axis_dual_i2s_v1_0.tcl
Normal file
12
LAB3/ip/axi4-stream-dual-i2s/xgui/axis_dual_i2s_v1_0.tcl
Normal file
@@ -0,0 +1,12 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_static_text $IPINST -name "Warnings" -parent ${Page_0} -text {The jumper on the board MUST BE in position SLV.
|
||||
The input clock axis_clk MUST BE 22.591 MHz.}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user