Add IPs
This commit is contained in:
35
LAB3/ip/axi4-stream-spi-master/README.md
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35
LAB3/ip/axi4-stream-spi-master/README.md
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# AXI4-Stream SPI Master
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This module implements an SPI Master.
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This module is based on the "SPI Master Lightweight" module on OpenCores, freely
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downloadable from [here](https://opencores.org/projects/spi_master_lightweight),
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with minimal modifications to add AXI4-Stream interfaces and reset signal.
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The cs signal is automatically asserted half clock cycle (SCLK) before the first
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rising edge of SCLK (with CPOL=0 and CPHA=0) and deasserted half clock cycle
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(SCLK) after the last falling edge of SCLK (with CPOL=0 and CPHA=0).
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## Generics
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* c_clkfreq: aclk frequency (in Hz)
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* c_sclkfreq: desired sclk frequency (in Hz); must be <= c_clkfreq/8
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* c_cpol: SPI CPOL
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* c_cpha: SPI CPHA
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## Slave AXI4-Stream
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Data passed to this module through this interface are serialized and send
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through the MOSI port, MSbit first.
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The CS signal will go low at the beginning of the transfer and will stay low
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until this module has data to send. In other words, keep s_axis_tvalid high and
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keep sending data if you want an uninterrupted transfer with CS always low.
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## Master AXI4-Stream
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Data received by this module will be sent through this interface. Note that this
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interface lacks a tready signal.
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For how the SPI protocol works, data can be received only when data is
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transmitted by the master so, if you want to receive N bytes, you have to send
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N bytes (by writing on the Slave AXI4-Stream interface).
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130
LAB3/ip/axi4-stream-spi-master/cocotb/.gitignore
vendored
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130
LAB3/ip/axi4-stream-spi-master/cocotb/.gitignore
vendored
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@@ -0,0 +1,130 @@
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# Byte-compiled / optimized / DLL files
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__pycache__/
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*.py[cod]
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*$py.class
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# C extensions
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*.so
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# Distribution / packaging
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.Python
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build/
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develop-eggs/
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dist/
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downloads/
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eggs/
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.eggs/
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lib/
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lib64/
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parts/
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sdist/
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var/
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wheels/
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pip-wheel-metadata/
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share/python-wheels/
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*.egg-info/
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.installed.cfg
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*.egg
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MANIFEST
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# PyInstaller
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# Usually these files are written by a python script from a template
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# before PyInstaller builds the exe, so as to inject date/other infos into it.
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*.manifest
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*.spec
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# Installer logs
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pip-log.txt
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pip-delete-this-directory.txt
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# Unit test / coverage reports
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htmlcov/
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.tox/
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.nox/
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.coverage
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.coverage.*
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.cache
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nosetests.xml
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coverage.xml
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*.cover
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.hypothesis/
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.pytest_cache/
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# Translations
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*.mo
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*.pot
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# Django stuff:
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*.log
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local_settings.py
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db.sqlite3
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db.sqlite3-journal
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# Flask stuff:
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instance/
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.webassets-cache
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# Scrapy stuff:
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.scrapy
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# Sphinx documentation
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docs/_build/
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# PyBuilder
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target/
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# Jupyter Notebook
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.ipynb_checkpoints
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# IPython
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profile_default/
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ipython_config.py
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# pyenv
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.python-version
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# pipenv
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# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
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# However, in case of collaboration, if having platform-specific dependencies or dependencies
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# having no cross-platform support, pipenv may install dependencies that don't work, or not
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# install all needed dependencies.
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#Pipfile.lock
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# celery beat schedule file
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celerybeat-schedule
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# SageMath parsed files
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*.sage.py
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# Environments
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.env
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.venv
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env/
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venv/
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ENV/
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env.bak/
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venv.bak/
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# Spyder project settings
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.spyderproject
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.spyproject
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# Rope project settings
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.ropeproject
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# mkdocs documentation
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/site
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# mypy
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.mypy_cache/
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.dmypy.json
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dmypy.json
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# Pyre type checker
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.pyre/
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# Cocotb build folder
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build/
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# Cocotb results
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results.xml
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20
LAB3/ip/axi4-stream-spi-master/cocotb/Makefile
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20
LAB3/ip/axi4-stream-spi-master/cocotb/Makefile
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@@ -0,0 +1,20 @@
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export PYTHON_BIN=python3
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PWD := $(shell pwd)
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SIM ?= ghdl
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SIM_ARGS ?= --wave=$(PWD)/build/waveform.ghw -gc_clkfreq=100000000 -gc_sclkfreq=10000000
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GHDL_ARGS ?= -fsynopsys
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TOPLEVEL_LANG = vhdl
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SIM_BUILD = $(PWD)/build
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MODULE = tester_axis_lw_spi_master
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TOPLEVEL = axis_lw_spi_master
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HDL_DIR = $(PWD)/../hdl
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VHDL_SOURCES = \
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$(HDL_DIR)/spi_master_lightweight/rtl/lw_spi_master.vhd \
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$(HDL_DIR)/axis_lw_spi_master.vhd
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -0,0 +1,82 @@
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#!/usr/bin/env python3
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import secrets
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, ClockCycles
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from cocotbext.axi4stream.drivers import Axi4StreamMaster
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from cocotbext.axi4stream.monitors import Axi4Stream
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from cocotbext.spi import SpiSlaveBase, SpiSignals, SpiConfig
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CLK_PERIOD = 10
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class SimpleSpiSlave(SpiSlaveBase):
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def __init__(self, signals, config, data):
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self._config = config
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self.content = 0
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self.data = data
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super().__init__(signals)
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async def get_content(self):
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await self.idle.wait()
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return self.content
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async def _transaction(self, frame_start, frame_end):
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await frame_start
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self.idle.clear()
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self._miso.value = 1 if self.data[0] & 0x80 else 0
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self.content = int(await self._shift(len(self.data) * 8 - 1, tx_word=int.from_bytes(self.data, 'big')))
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await RisingEdge(self._sclk)
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self.content = self.content << 1 | int(self._mosi.value.integer)
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await frame_end
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async def setup_dut(dut):
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cocotb.fork(Clock(dut.aclk, CLK_PERIOD, "ns").start())
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@cocotb.test()
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async def test_spi(dut, length=32):
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"""TODO"""
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spi_signals = SpiSignals(
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sclk = dut.sclk,
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mosi = dut.mosi,
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miso = dut.miso,
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cs = dut.cs
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)
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spi_config = SpiConfig(
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word_width = 8,
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cpol = False,
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cpha = False,
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data_output_idle = 0,
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msb_first = True
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)
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mosi_tx = secrets.randbits(length * 8).to_bytes(length, 'little')
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miso_tx = secrets.randbits(length * 8).to_bytes(length, 'little')
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spi_slave = SimpleSpiSlave(spi_signals, spi_config, miso_tx)
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miso_rx = bytearray()
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axis_m = Axi4StreamMaster(dut, "s_axis", dut.aclk)
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axis_monitor = Axi4Stream(dut, "m_axis", dut.aclk, packets=False)
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axis_monitor.add_callback(lambda data: miso_rx.extend(data))
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await setup_dut(dut)
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await ClockCycles(dut.aclk, 10)
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await axis_m.write([b for b in mosi_tx])
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mosi_rx = (await spi_slave.get_content()).to_bytes(length, 'big')
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await ClockCycles(dut.aclk, 10)
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assert mosi_tx == mosi_rx, "Received MOSI data does not match transmitted one"
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assert miso_tx == miso_rx, "Received MISO data does not match transmitted one"
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53
LAB3/ip/axi4-stream-spi-master/cocotb/waveforms.gtkw
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53
LAB3/ip/axi4-stream-spi-master/cocotb/waveforms.gtkw
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@@ -0,0 +1,53 @@
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Fri Mar 25 16:24:27 2022
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[*]
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[dumpfile] "/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master/sim/build/waveform.ghw"
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[dumpfile_mtime] "Fri Mar 25 16:23:35 2022"
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[dumpfile_size] 3066
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[savefile] "/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master/sim/waveforms.gtkw"
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[timestart] 0
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[size] 1920 1001
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[pos] -27 -24
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*-27.176317 7190000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.axis_lw_spi_master.
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[treeopen] top.axis_lw_spi_master.inst_lw_spi_master.
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[sst_width] 281
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[signals_width] 200
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[sst_expanded] 1
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[sst_vpaned_height] 285
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@28
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top.axis_lw_spi_master.clk
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@200
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-
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@28
|
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top.axis_lw_spi_master.s_axis_tvalid
|
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top.axis_lw_spi_master.s_axis_tready
|
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@22
|
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#{top.axis_lw_spi_master.s_axis_tdata[7:0]} top.axis_lw_spi_master.s_axis_tdata[7] top.axis_lw_spi_master.s_axis_tdata[6] top.axis_lw_spi_master.s_axis_tdata[5] top.axis_lw_spi_master.s_axis_tdata[4] top.axis_lw_spi_master.s_axis_tdata[3] top.axis_lw_spi_master.s_axis_tdata[2] top.axis_lw_spi_master.s_axis_tdata[1] top.axis_lw_spi_master.s_axis_tdata[0]
|
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@200
|
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-
|
||||
@28
|
||||
top.axis_lw_spi_master.m_axis_tvalid
|
||||
@22
|
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#{top.axis_lw_spi_master.m_axis_tdata[7:0]} top.axis_lw_spi_master.m_axis_tdata[7] top.axis_lw_spi_master.m_axis_tdata[6] top.axis_lw_spi_master.m_axis_tdata[5] top.axis_lw_spi_master.m_axis_tdata[4] top.axis_lw_spi_master.m_axis_tdata[3] top.axis_lw_spi_master.m_axis_tdata[2] top.axis_lw_spi_master.m_axis_tdata[1] top.axis_lw_spi_master.m_axis_tdata[0]
|
||||
@200
|
||||
-
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||||
@28
|
||||
top.axis_lw_spi_master.inst_lw_spi_master.en_i
|
||||
@22
|
||||
#{top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[7:0]} top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[7] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[6] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[5] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[4] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[3] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[2] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[1] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[0]
|
||||
#{top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[7:0]} top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[7] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[6] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[5] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[4] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[3] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[2] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[1] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[0]
|
||||
@28
|
||||
top.axis_lw_spi_master.inst_lw_spi_master.data_ready_o
|
||||
@200
|
||||
-
|
||||
@28
|
||||
top.axis_lw_spi_master.sclk
|
||||
top.axis_lw_spi_master.mosi
|
||||
top.axis_lw_spi_master.miso
|
||||
@29
|
||||
top.axis_lw_spi_master.cs
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
761
LAB3/ip/axi4-stream-spi-master/component.xml
Normal file
761
LAB3/ip/axi4-stream-spi-master/component.xml
Normal file
@@ -0,0 +1,761 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>DigiLAB</spirit:vendor>
|
||||
<spirit:library>ip</spirit:library>
|
||||
<spirit:name>axi4stream_spi_master</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
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<xilinx:tag xilinx:name="ui.data.coregen.dd@3c220934_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@60cc7730_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1b872887_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@12cc8e94_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@60277b97_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@727d172d_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d142a37_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@52ee67f1_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5d92efa1_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1dee489d_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@26ad48d_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@35633496_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6e7fd5e1_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2f269b73_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4321e470_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@622e4722_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@516bcd31_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@154652f5_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@154b0aec_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2bdfa8f4_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6a2c4c16_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5b6edfab_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@300166e6_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2640b195_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@209eabbb_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7b342600_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@63834115_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2f81fecf_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@263866aa_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4729e3d6_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@64f75c13_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@44df24ac_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@38346929_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@13994ae1_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2b5aa9df_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@254f99cf_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5992ce27_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1d65a24d_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@66fe833_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4e265a05_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7ea38f04_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5dea1411_ARCHIVE_LOCATION">/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="e1253621"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8b40e7f6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c4276c6c"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f6029529"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="fa214c74"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
104
LAB3/ip/axi4-stream-spi-master/hdl/axis_lw_spi_master.vhd
Normal file
104
LAB3/ip/axi4-stream-spi-master/hdl/axis_lw_spi_master.vhd
Normal file
@@ -0,0 +1,104 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity axis_lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 100_000_000;
|
||||
c_sclkfreq : integer := 1_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
|
||||
cs : out STD_LOGIC;
|
||||
sclk : out STD_LOGIC;
|
||||
mosi : out STD_LOGIC;
|
||||
miso : in STD_LOGIC
|
||||
);
|
||||
end axis_lw_spi_master;
|
||||
|
||||
architecture Behavioral of axis_lw_spi_master is
|
||||
|
||||
component lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 50_000_000;
|
||||
c_sclkfreq : integer := 5_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
clk_i : in STD_LOGIC;
|
||||
rst_i : in STD_LOGIC;
|
||||
en_i : in STD_LOGIC;
|
||||
mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
data_ready_o : out STD_LOGIC;
|
||||
cs_o : out STD_LOGIC;
|
||||
sclk_o : out STD_LOGIC;
|
||||
mosi_o : out STD_LOGIC;
|
||||
miso_i : in STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst : std_logic;
|
||||
signal data_ready : std_logic;
|
||||
signal data_ready_reg : std_logic;
|
||||
signal new_data : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
inst_lw_spi_master : lw_spi_master
|
||||
generic map (
|
||||
c_clkfreq => c_clkfreq,
|
||||
c_sclkfreq => c_sclkfreq,
|
||||
c_cpol => c_cpol,
|
||||
c_cpha => c_cpha
|
||||
)
|
||||
Port map (
|
||||
clk_i => aclk,
|
||||
rst_i => rst,
|
||||
en_i => s_axis_tvalid,
|
||||
mosi_data_i => s_axis_tdata,
|
||||
miso_data_o => m_axis_tdata,
|
||||
data_ready_o => data_ready,
|
||||
cs_o => cs,
|
||||
sclk_o => sclk,
|
||||
mosi_o => mosi,
|
||||
miso_i => miso
|
||||
);
|
||||
|
||||
rst <= not aresetn;
|
||||
s_axis_tready <= new_data;
|
||||
m_axis_tvalid <= new_data;
|
||||
|
||||
process (aclk)
|
||||
begin
|
||||
if rising_edge(aclk) then
|
||||
if aresetn = '0' then
|
||||
|
||||
new_data <= '0';
|
||||
|
||||
else
|
||||
|
||||
data_ready_reg <= data_ready;
|
||||
|
||||
if data_ready_reg = '0' and data_ready = '1' then
|
||||
new_data <= '1';
|
||||
else
|
||||
new_data <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
103
LAB3/ip/axi4-stream-spi-master/hdl/ipi_axis_lw_spi_master.vhd
Normal file
103
LAB3/ip/axi4-stream-spi-master/hdl/ipi_axis_lw_spi_master.vhd
Normal file
@@ -0,0 +1,103 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity ipi_axis_lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 100_000_000;
|
||||
c_sclkfreq : integer := 1_000_000;
|
||||
c_cpol : integer range 0 to 1 := 0;
|
||||
c_cpha : integer range 0 to 1 := 0
|
||||
);
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
|
||||
cs_i : in STD_LOGIC;
|
||||
cs_o : out STD_LOGIC;
|
||||
cs_t : out STD_LOGIC;
|
||||
|
||||
sclk_i : in STD_LOGIC;
|
||||
sclk_o : out STD_LOGIC;
|
||||
sclk_t : out STD_LOGIC;
|
||||
|
||||
mosi_i : in STD_LOGIC;
|
||||
mosi_o : out STD_LOGIC;
|
||||
mosi_t : out STD_LOGIC;
|
||||
|
||||
miso_i : in STD_LOGIC;
|
||||
miso_o : out STD_LOGIC;
|
||||
miso_t : out STD_LOGIC
|
||||
);
|
||||
end ipi_axis_lw_spi_master;
|
||||
|
||||
architecture Behavioral of ipi_axis_lw_spi_master is
|
||||
|
||||
component axis_lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 100_000_000;
|
||||
c_sclkfreq : integer := 1_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
|
||||
cs : out STD_LOGIC;
|
||||
sclk : out STD_LOGIC;
|
||||
mosi : out STD_LOGIC;
|
||||
miso : in STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
constant C_CPOL_SLV : std_logic_vector := std_logic_vector(to_unsigned(c_cpol, 1));
|
||||
constant C_CPHA_SLV : std_logic_vector := std_logic_vector(to_unsigned(c_cpha, 1));
|
||||
|
||||
begin
|
||||
|
||||
inst_axis_lw_spi_master : axis_lw_spi_master
|
||||
generic map (
|
||||
c_clkfreq => c_clkfreq,
|
||||
c_sclkfreq => c_sclkfreq,
|
||||
c_cpol => C_CPOL_SLV(0),
|
||||
c_cpha => C_CPHA_SLV(0)
|
||||
)
|
||||
Port map (
|
||||
aclk => aclk,
|
||||
aresetn => aresetn,
|
||||
|
||||
s_axis_tvalid => s_axis_tvalid,
|
||||
s_axis_tdata => s_axis_tdata,
|
||||
s_axis_tready => s_axis_tready,
|
||||
|
||||
m_axis_tvalid => m_axis_tvalid,
|
||||
m_axis_tdata => m_axis_tdata,
|
||||
|
||||
cs => cs_o,
|
||||
sclk => sclk_o,
|
||||
mosi => mosi_o,
|
||||
miso => miso_i
|
||||
);
|
||||
|
||||
cs_t <= '0';
|
||||
sclk_t <= '0';
|
||||
mosi_t <= '0';
|
||||
miso_t <= '1';
|
||||
miso_o <= '0';
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,3 @@
|
||||
# SPI Master Lightweight
|
||||
|
||||
Taken from [OpenCores](https://opencores.org/projects/spi_master_lightweight).
|
||||
Binary file not shown.
@@ -0,0 +1,165 @@
|
||||
GNU LESSER GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
|
||||
This version of the GNU Lesser General Public License incorporates
|
||||
the terms and conditions of version 3 of the GNU General Public
|
||||
License, supplemented by the additional permissions listed below.
|
||||
|
||||
0. Additional Definitions.
|
||||
|
||||
As used herein, "this License" refers to version 3 of the GNU Lesser
|
||||
General Public License, and the "GNU GPL" refers to version 3 of the GNU
|
||||
General Public License.
|
||||
|
||||
"The Library" refers to a covered work governed by this License,
|
||||
other than an Application or a Combined Work as defined below.
|
||||
|
||||
An "Application" is any work that makes use of an interface provided
|
||||
by the Library, but which is not otherwise based on the Library.
|
||||
Defining a subclass of a class defined by the Library is deemed a mode
|
||||
of using an interface provided by the Library.
|
||||
|
||||
A "Combined Work" is a work produced by combining or linking an
|
||||
Application with the Library. The particular version of the Library
|
||||
with which the Combined Work was made is also called the "Linked
|
||||
Version".
|
||||
|
||||
The "Minimal Corresponding Source" for a Combined Work means the
|
||||
Corresponding Source for the Combined Work, excluding any source code
|
||||
for portions of the Combined Work that, considered in isolation, are
|
||||
based on the Application, and not on the Linked Version.
|
||||
|
||||
The "Corresponding Application Code" for a Combined Work means the
|
||||
object code and/or source code for the Application, including any data
|
||||
and utility programs needed for reproducing the Combined Work from the
|
||||
Application, but excluding the System Libraries of the Combined Work.
|
||||
|
||||
1. Exception to Section 3 of the GNU GPL.
|
||||
|
||||
You may convey a covered work under sections 3 and 4 of this License
|
||||
without being bound by section 3 of the GNU GPL.
|
||||
|
||||
2. Conveying Modified Versions.
|
||||
|
||||
If you modify a copy of the Library, and, in your modifications, a
|
||||
facility refers to a function or data to be supplied by an Application
|
||||
that uses the facility (other than as an argument passed when the
|
||||
facility is invoked), then you may convey a copy of the modified
|
||||
version:
|
||||
|
||||
a) under this License, provided that you make a good faith effort to
|
||||
ensure that, in the event an Application does not supply the
|
||||
function or data, the facility still operates, and performs
|
||||
whatever part of its purpose remains meaningful, or
|
||||
|
||||
b) under the GNU GPL, with none of the additional permissions of
|
||||
this License applicable to that copy.
|
||||
|
||||
3. Object Code Incorporating Material from Library Header Files.
|
||||
|
||||
The object code form of an Application may incorporate material from
|
||||
a header file that is part of the Library. You may convey such object
|
||||
code under terms of your choice, provided that, if the incorporated
|
||||
material is not limited to numerical parameters, data structure
|
||||
layouts and accessors, or small macros, inline functions and templates
|
||||
(ten or fewer lines in length), you do both of the following:
|
||||
|
||||
a) Give prominent notice with each copy of the object code that the
|
||||
Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the object code with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
4. Combined Works.
|
||||
|
||||
You may convey a Combined Work under terms of your choice that,
|
||||
taken together, effectively do not restrict modification of the
|
||||
portions of the Library contained in the Combined Work and reverse
|
||||
engineering for debugging such modifications, if you also do each of
|
||||
the following:
|
||||
|
||||
a) Give prominent notice with each copy of the Combined Work that
|
||||
the Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the Combined Work with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
c) For a Combined Work that displays copyright notices during
|
||||
execution, include the copyright notice for the Library among
|
||||
these notices, as well as a reference directing the user to the
|
||||
copies of the GNU GPL and this license document.
|
||||
|
||||
d) Do one of the following:
|
||||
|
||||
0) Convey the Minimal Corresponding Source under the terms of this
|
||||
License, and the Corresponding Application Code in a form
|
||||
suitable for, and under terms that permit, the user to
|
||||
recombine or relink the Application with a modified version of
|
||||
the Linked Version to produce a modified Combined Work, in the
|
||||
manner specified by section 6 of the GNU GPL for conveying
|
||||
Corresponding Source.
|
||||
|
||||
1) Use a suitable shared library mechanism for linking with the
|
||||
Library. A suitable mechanism is one that (a) uses at run time
|
||||
a copy of the Library already present on the user's computer
|
||||
system, and (b) will operate properly with a modified version
|
||||
of the Library that is interface-compatible with the Linked
|
||||
Version.
|
||||
|
||||
e) Provide Installation Information, but only if you would otherwise
|
||||
be required to provide such information under section 6 of the
|
||||
GNU GPL, and only to the extent that such information is
|
||||
necessary to install and execute a modified version of the
|
||||
Combined Work produced by recombining or relinking the
|
||||
Application with a modified version of the Linked Version. (If
|
||||
you use option 4d0, the Installation Information must accompany
|
||||
the Minimal Corresponding Source and Corresponding Application
|
||||
Code. If you use option 4d1, you must provide the Installation
|
||||
Information in the manner specified by section 6 of the GNU GPL
|
||||
for conveying Corresponding Source.)
|
||||
|
||||
5. Combined Libraries.
|
||||
|
||||
You may place library facilities that are a work based on the
|
||||
Library side by side in a single library together with other library
|
||||
facilities that are not Applications and are not covered by this
|
||||
License, and convey such a combined library under terms of your
|
||||
choice, if you do both of the following:
|
||||
|
||||
a) Accompany the combined library with a copy of the same work based
|
||||
on the Library, uncombined with any other library facilities,
|
||||
conveyed under the terms of this License.
|
||||
|
||||
b) Give prominent notice with the combined library that part of it
|
||||
is a work based on the Library, and explaining where to find the
|
||||
accompanying uncombined form of the same work.
|
||||
|
||||
6. Revised Versions of the GNU Lesser General Public License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions
|
||||
of the GNU Lesser General Public License from time to time. Such new
|
||||
versions will be similar in spirit to the present version, but may
|
||||
differ in detail to address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Library as you received it specifies that a certain numbered version
|
||||
of the GNU Lesser General Public License "or any later version"
|
||||
applies to it, you have the option of following the terms and
|
||||
conditions either of that published version or of any later version
|
||||
published by the Free Software Foundation. If the Library as you
|
||||
received it does not specify a version number of the GNU Lesser
|
||||
General Public License, you may choose any version of the GNU Lesser
|
||||
General Public License ever published by the Free Software Foundation.
|
||||
|
||||
If the Library as you received it specifies that a proxy can decide
|
||||
whether future versions of the GNU Lesser General Public License shall
|
||||
apply, that proxy's public statement of acceptance of any version is
|
||||
permanent authorization for you to choose that version for the
|
||||
Library.
|
||||
@@ -0,0 +1,263 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity lw_spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 50_000_000;
|
||||
c_sclkfreq : integer := 5_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
clk_i : in STD_LOGIC;
|
||||
rst_i : in STD_LOGIC;
|
||||
en_i : in STD_LOGIC;
|
||||
mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
data_ready_o : out STD_LOGIC;
|
||||
cs_o : out STD_LOGIC;
|
||||
sclk_o : out STD_LOGIC;
|
||||
mosi_o : out STD_LOGIC;
|
||||
miso_i : in STD_LOGIC
|
||||
);
|
||||
end lw_spi_master;
|
||||
|
||||
architecture Behavioral of lw_spi_master is
|
||||
|
||||
signal write_reg : std_logic_vector (7 downto 0) := (others => '0');
|
||||
signal read_reg : std_logic_vector (7 downto 0) := (others => '0');
|
||||
|
||||
signal sclk_en : std_logic := '0';
|
||||
signal sclk : std_logic := '0';
|
||||
signal sclk_prev : std_logic := '0';
|
||||
signal sclk_rise : std_logic := '0';
|
||||
signal sclk_fall : std_logic := '0';
|
||||
|
||||
signal pol_phase : std_logic_vector (1 downto 0) := (others => '0');
|
||||
signal mosi_en : std_logic := '0';
|
||||
signal miso_en : std_logic := '0';
|
||||
|
||||
constant c_edgecntrlimdiv2 : integer := c_clkfreq/(c_sclkfreq*2);
|
||||
signal edgecntr : integer range 0 to c_edgecntrlimdiv2 := 0;
|
||||
|
||||
signal cntr : integer range 0 to 15 := 0;
|
||||
|
||||
type states is (S_IDLE, S_TRANSFER);
|
||||
signal state : states := S_IDLE;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
pol_phase <= c_cpol & c_cpha;
|
||||
|
||||
P_SAMPLE_EN : process (pol_phase, sclk_fall, sclk_rise) begin
|
||||
|
||||
case pol_phase is
|
||||
|
||||
when "00" =>
|
||||
|
||||
mosi_en <= sclk_fall;
|
||||
miso_en <= sclk_rise;
|
||||
|
||||
when "01" =>
|
||||
|
||||
mosi_en <= sclk_rise;
|
||||
miso_en <= sclk_fall;
|
||||
|
||||
when "10" =>
|
||||
|
||||
mosi_en <= sclk_rise;
|
||||
miso_en <= sclk_fall;
|
||||
|
||||
when "11" =>
|
||||
|
||||
mosi_en <= sclk_fall;
|
||||
miso_en <= sclk_rise;
|
||||
|
||||
when others =>
|
||||
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
P_RISEFALL_DETECT : process (sclk, sclk_prev) begin
|
||||
|
||||
if (sclk = '1' and sclk_prev = '0') then
|
||||
sclk_rise <= '1';
|
||||
else
|
||||
sclk_rise <= '0';
|
||||
end if;
|
||||
|
||||
if (sclk = '0' and sclk_prev = '1') then
|
||||
sclk_fall <= '1';
|
||||
else
|
||||
sclk_fall <= '0';
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
P_MAIN : process (clk_i) begin
|
||||
if (rising_edge(clk_i)) then
|
||||
|
||||
if rst_i = '1' then
|
||||
|
||||
cs_o <= '1';
|
||||
mosi_o <= '0';
|
||||
data_ready_o <= '0';
|
||||
sclk_en <= '0';
|
||||
|
||||
else
|
||||
sclk_prev <= sclk;
|
||||
|
||||
case state is
|
||||
|
||||
when S_IDLE =>
|
||||
|
||||
cs_o <= '1';
|
||||
mosi_o <= '0';
|
||||
data_ready_o <= '0';
|
||||
sclk_en <= '0';
|
||||
cntr <= 0;
|
||||
|
||||
if (c_cpol = '0') then
|
||||
sclk_o <= '0';
|
||||
else
|
||||
sclk_o <= '1';
|
||||
end if;
|
||||
|
||||
if (en_i = '1') then
|
||||
state <= S_TRANSFER;
|
||||
sclk_en <= '1';
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
read_reg <= x"00";
|
||||
end if;
|
||||
|
||||
when S_TRANSFER =>
|
||||
|
||||
cs_o <= '0';
|
||||
mosi_o <= write_reg(7);
|
||||
|
||||
|
||||
if (c_cpha = '1') then
|
||||
|
||||
if (cntr = 0) then
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
elsif (cntr = 8) then
|
||||
data_ready_o <= '1';
|
||||
miso_data_o <= read_reg;
|
||||
if (mosi_en = '1') then
|
||||
data_ready_o <= '0';
|
||||
if (en_i = '1') then
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
sclk_o <= sclk;
|
||||
cntr <= 0;
|
||||
else
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
end if;
|
||||
elsif (cntr = 9) then
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
else
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (mosi_en = '1') then
|
||||
mosi_o <= write_reg(7);
|
||||
write_reg(7 downto 1) <= write_reg(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else -- c_cpha = '0'
|
||||
|
||||
if (cntr = 0) then
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
elsif (cntr = 8) then
|
||||
|
||||
data_ready_o <= '1';
|
||||
miso_data_o <= read_reg;
|
||||
sclk_o <= sclk;
|
||||
if (mosi_en = '1') then
|
||||
data_ready_o <= '0';
|
||||
if (en_i = '1') then
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
cntr <= 0;
|
||||
else
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
end if;
|
||||
elsif (cntr = 9) then
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
else
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (mosi_en = '1') then
|
||||
write_reg(7 downto 1) <= write_reg(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
P_SCLK_GEN : process (clk_i) begin
|
||||
if (rising_edge(clk_i)) then
|
||||
|
||||
if (sclk_en = '1') then
|
||||
if edgecntr = c_edgecntrlimdiv2-1 then
|
||||
sclk <= not sclk;
|
||||
edgecntr <= 0;
|
||||
else
|
||||
edgecntr <= edgecntr + 1;
|
||||
end if;
|
||||
else
|
||||
edgecntr <= 0;
|
||||
if (c_cpol = '0') then
|
||||
sclk <= '0';
|
||||
else
|
||||
sclk <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,315 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- AUTHOR: MEHMET BURAK AYKENAR
|
||||
-- CREATED: 09.12.2019
|
||||
-- REVISION DATE: 09.12.2019
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- DESCRIPTION:
|
||||
-- This module implements master part of SPI communication interface and can be used to any SPI slave IC.
|
||||
|
||||
-- In order to read from a slave IC, mosi_data_i input signal should be assigned to desired value and en_i signal should be high.
|
||||
-- In order to write to a slave IC, en_i input signal should be high.
|
||||
-- data_ready_o output signal has the logic high value for one clock cycle as read or/and write operation finished. miso_data_o output signal
|
||||
-- has the data read from slave IC.
|
||||
-- In order to read or/and write consecutively, en_i signal should be kept high. To end the transaction, en_i input signal should be assigned to zero
|
||||
-- when data_ready_o output signal gets high.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Limitation/Assumption: In order to use this module properly, the ratio of (c_clkfreq / c_sclkFreq) should be equal to 8 or more.
|
||||
-- For higher SCLK frequencies are possible but more elaboration is needed.
|
||||
-- Notes: c_cpol and c_cpha parameters are clock polarity and clock phase, respectively.
|
||||
--------------------------------------------------------------------------------
|
||||
-- VHDL DIALECT: VHDL '93
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- PROJECT : General purpose
|
||||
-- BOARD : General purpose
|
||||
-- ENTITY : spi_master
|
||||
--------------------------------------------------------------------
|
||||
-- FILE : spi_master.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- REVISION HISTORY:
|
||||
-- REVISION DATE AUTHOR COMMENT
|
||||
-- -------- ---------- ------------ -----------
|
||||
-- 1.0 19.12.2019 M.B.AYKENAR INITIAL REVISION
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity spi_master is
|
||||
generic (
|
||||
c_clkfreq : integer := 50_000_000;
|
||||
c_sclkfreq : integer := 1_000_000;
|
||||
c_cpol : std_logic := '0';
|
||||
c_cpha : std_logic := '0'
|
||||
);
|
||||
Port (
|
||||
clk_i : in STD_LOGIC;
|
||||
en_i : in STD_LOGIC;
|
||||
mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
data_ready_o : out STD_LOGIC;
|
||||
cs_o : out STD_LOGIC;
|
||||
sclk_o : out STD_LOGIC;
|
||||
mosi_o : out STD_LOGIC;
|
||||
miso_i : in STD_LOGIC
|
||||
);
|
||||
end spi_master;
|
||||
|
||||
architecture Behavioral of spi_master is
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- CONSTANTS
|
||||
constant c_edgecntrlimdiv2 : integer := c_clkfreq/(c_sclkfreq*2);
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- INTERNAL SIGNALS
|
||||
signal write_reg : std_logic_vector (7 downto 0) := (others => '0');
|
||||
signal read_reg : std_logic_vector (7 downto 0) := (others => '0');
|
||||
|
||||
signal sclk_en : std_logic := '0';
|
||||
signal sclk : std_logic := '0';
|
||||
signal sclk_prev : std_logic := '0';
|
||||
signal sclk_rise : std_logic := '0';
|
||||
signal sclk_fall : std_logic := '0';
|
||||
|
||||
signal pol_phase : std_logic_vector (1 downto 0) := (others => '0');
|
||||
signal mosi_en : std_logic := '0';
|
||||
signal miso_en : std_logic := '0';
|
||||
signal once : std_logic := '0';
|
||||
|
||||
signal edgecntr : integer range 0 to c_edgecntrlimdiv2 := 0;
|
||||
|
||||
signal cntr : integer range 0 to 15 := 0;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- STATE DEFINITIONS
|
||||
type states is (S_IDLE, S_TRANSFER);
|
||||
signal state : states := S_IDLE;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
pol_phase <= c_cpol & c_cpha;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- SAMPLE_EN process assigns mosi_en and miso_en internal signals to sclk_fall or sclk_rise in a combinational logic according to
|
||||
-- generic parameters of c_cpol and c_cpha via pol_phase signal.
|
||||
P_SAMPLE_EN : process (pol_phase, sclk_fall, sclk_rise) begin
|
||||
|
||||
case pol_phase is
|
||||
|
||||
when "00" =>
|
||||
|
||||
mosi_en <= sclk_fall;
|
||||
miso_en <= sclk_rise;
|
||||
|
||||
when "01" =>
|
||||
|
||||
mosi_en <= sclk_rise;
|
||||
miso_en <= sclk_fall;
|
||||
|
||||
when "10" =>
|
||||
|
||||
mosi_en <= sclk_rise;
|
||||
miso_en <= sclk_fall;
|
||||
|
||||
when "11" =>
|
||||
|
||||
mosi_en <= sclk_fall;
|
||||
miso_en <= sclk_rise;
|
||||
|
||||
when others =>
|
||||
|
||||
end case;
|
||||
|
||||
end process P_SAMPLE_EN;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- RISEFALL_DETECT process assigns sclk_rise and sclk_fall signals in a combinational logic.
|
||||
P_RISEFALL_DETECT : process (sclk, sclk_prev) begin
|
||||
|
||||
if (sclk = '1' and sclk_prev = '0') then
|
||||
sclk_rise <= '1';
|
||||
else
|
||||
sclk_rise <= '0';
|
||||
end if;
|
||||
|
||||
if (sclk = '0' and sclk_prev = '1') then
|
||||
sclk_fall <= '1';
|
||||
else
|
||||
sclk_fall <= '0';
|
||||
end if;
|
||||
|
||||
end process P_RISEFALL_DETECT;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- In the MAIN process S_IDLE and S_TRANSFER states are implemented. state changes from S_IDLE to S_TRANSFER when en_i input
|
||||
-- signal has the logic high value. At that cycle, write_reg signal is assigned to mosi_data_i input signal. According to c_cpha generic
|
||||
-- parameter, the transaction operation changes slightly. This operational difference is well explained in the paper that can be found
|
||||
-- in Documents folder of the SPI, which is located in SVN server.
|
||||
P_MAIN : process (clk_i) begin
|
||||
if (rising_edge(clk_i)) then
|
||||
|
||||
data_ready_o <= '0';
|
||||
sclk_prev <= sclk;
|
||||
|
||||
case state is
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
when S_IDLE =>
|
||||
|
||||
cs_o <= '1';
|
||||
mosi_o <= '0';
|
||||
data_ready_o <= '0';
|
||||
sclk_en <= '0';
|
||||
cntr <= 0;
|
||||
|
||||
if (c_cpol = '0') then
|
||||
sclk_o <= '0';
|
||||
else
|
||||
sclk_o <= '1';
|
||||
end if;
|
||||
|
||||
if (en_i = '1') then
|
||||
state <= S_TRANSFER;
|
||||
sclk_en <= '1';
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
read_reg <= x"00";
|
||||
end if;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
when S_TRANSFER =>
|
||||
|
||||
cs_o <= '0';
|
||||
mosi_o <= write_reg(7);
|
||||
|
||||
|
||||
if (c_cpha = '1') then
|
||||
|
||||
if (cntr = 0) then
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
once <= '1';
|
||||
end if;
|
||||
elsif (cntr = 8) then
|
||||
if (once = '1') then
|
||||
data_ready_o <= '1';
|
||||
once <= '0';
|
||||
end if;
|
||||
miso_data_o <= read_reg;
|
||||
if (mosi_en = '1') then
|
||||
if (en_i = '1') then
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
sclk_o <= sclk;
|
||||
cntr <= 0;
|
||||
else
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
end if;
|
||||
elsif (cntr = 9) then
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
else
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (mosi_en = '1') then
|
||||
mosi_o <= write_reg(7);
|
||||
write_reg(7 downto 1) <= write_reg(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else -- c_cpha = '0'
|
||||
|
||||
if (cntr = 0) then
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
once <= '1';
|
||||
end if;
|
||||
elsif (cntr = 8) then
|
||||
if (once = '1') then
|
||||
data_ready_o <= '1';
|
||||
once <= '0';
|
||||
end if;
|
||||
miso_data_o <= read_reg;
|
||||
sclk_o <= sclk;
|
||||
if (mosi_en = '1') then
|
||||
if (en_i = '1') then
|
||||
write_reg <= mosi_data_i;
|
||||
mosi_o <= mosi_data_i(7);
|
||||
cntr <= 0;
|
||||
else
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
end if;
|
||||
elsif (cntr = 9) then
|
||||
if (miso_en = '1') then
|
||||
state <= S_IDLE;
|
||||
cs_o <= '1';
|
||||
end if;
|
||||
else
|
||||
sclk_o <= sclk;
|
||||
if (miso_en = '1') then
|
||||
read_reg(0) <= miso_i;
|
||||
read_reg(7 downto 1) <= read_reg(6 downto 0);
|
||||
cntr <= cntr + 1;
|
||||
end if;
|
||||
if (mosi_en = '1') then
|
||||
write_reg(7 downto 1) <= write_reg(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process P_MAIN;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- In the SCLK_GEN process, internal sclk signal is generated if sclk_en signal is '1'.
|
||||
P_SCLK_GEN : process (clk_i) begin
|
||||
if (rising_edge(clk_i)) then
|
||||
|
||||
if (sclk_en = '1') then
|
||||
if edgecntr = c_edgecntrlimdiv2-1 then
|
||||
sclk <= not sclk;
|
||||
edgecntr <= 0;
|
||||
else
|
||||
edgecntr <= edgecntr + 1;
|
||||
end if;
|
||||
else
|
||||
edgecntr <= 0;
|
||||
if (c_cpol = '0') then
|
||||
sclk <= '0';
|
||||
else
|
||||
sclk <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process P_SCLK_GEN;
|
||||
|
||||
end Behavioral;
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 68 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 186 KiB |
@@ -0,0 +1,233 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
ENTITY tb_lw_spi_master IS
|
||||
END tb_lw_spi_master;
|
||||
|
||||
ARCHITECTURE behavior OF tb_lw_spi_master IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT lw_spi_master
|
||||
PORT(
|
||||
clk_i : IN std_logic;
|
||||
en_i : IN std_logic;
|
||||
mosi_data_i : IN std_logic_vector(7 downto 0);
|
||||
miso_data_o : OUT std_logic_vector(7 downto 0);
|
||||
data_ready_o : OUT std_logic;
|
||||
cs_o : OUT std_logic;
|
||||
sclk_o : OUT std_logic;
|
||||
mosi_o : OUT std_logic;
|
||||
miso_i : IN std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal clk_i : std_logic := '0';
|
||||
signal en_i : std_logic := '0';
|
||||
signal mosi_data_i : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal miso_i : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal miso_data_o : std_logic_vector(7 downto 0);
|
||||
signal data_ready_o : std_logic;
|
||||
signal cs_o : std_logic;
|
||||
signal sclk_o : std_logic;
|
||||
signal mosi_o : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
-- Clock period definitions
|
||||
constant clk_i_period : time := 20 ns;
|
||||
constant sckPeriod : time := 200 ns;
|
||||
|
||||
signal SPISIGNAL : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal spiWrite : std_logic := '0';
|
||||
signal spiWriteDone : std_logic := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: lw_spi_master PORT MAP (
|
||||
clk_i => clk_i,
|
||||
en_i => en_i,
|
||||
mosi_data_i => mosi_data_i,
|
||||
miso_data_o => miso_data_o,
|
||||
data_ready_o => data_ready_o,
|
||||
cs_o => cs_o,
|
||||
sclk_o => sclk_o,
|
||||
mosi_o => mosi_o,
|
||||
miso_i => miso_i
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
clk_i_process :process
|
||||
begin
|
||||
clk_i <= '0';
|
||||
wait for clk_i_period/2;
|
||||
clk_i <= '1';
|
||||
wait for clk_i_period/2;
|
||||
end process;
|
||||
|
||||
SPIWRITE_P : process begin
|
||||
|
||||
wait until rising_edge(spiWrite);
|
||||
|
||||
-- for cpol = 1 cpha = 1
|
||||
-- for cpol = 0 cpha = 0
|
||||
|
||||
miso_i <= SPISIGNAL(7);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(6);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(5);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(4);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(3);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(2);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(1);
|
||||
wait until falling_edge(sclk_o);
|
||||
miso_i <= SPISIGNAL(0);
|
||||
|
||||
-- for cpol = 0 cpha = 1
|
||||
-- for cpol = 1 cpha = 0
|
||||
|
||||
-- miso_i <= SPISIGNAL(7);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(6);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(5);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(4);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(3);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(2);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(1);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- miso_i <= SPISIGNAL(0);
|
||||
|
||||
spiWriteDone <= '1';
|
||||
wait for 1 ps;
|
||||
spiWriteDone <= '0';
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
|
||||
wait for clk_i_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- -- CPOL,CPHA = 00
|
||||
en_i <= '1';
|
||||
|
||||
-- write 0xA7, read 0xB2
|
||||
mosi_data_i <= x"A7";
|
||||
wait until falling_edge(cs_o);
|
||||
SPISIGNAL <= x"B2";
|
||||
spiWrite <= '1';
|
||||
wait until rising_edge(spiWriteDone);
|
||||
spiWrite <= '0';
|
||||
|
||||
-- write 0xB8, read 0xC3
|
||||
wait until rising_edge(data_ready_o);
|
||||
mosi_data_i <= x"B8";
|
||||
wait until falling_edge(data_ready_o);
|
||||
SPISIGNAL <= x"C3";
|
||||
spiWrite <= '1';
|
||||
wait until rising_edge(spiWriteDone);
|
||||
spiWrite <= '0';
|
||||
en_i <= '0';
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- -- CPOL,CPHA = 10
|
||||
-- en_i <= '1';
|
||||
--
|
||||
-- -- write 0xA7, read 0xB2
|
||||
-- mosi_data_i <= x"A7";
|
||||
-- wait until falling_edge(cs_o);
|
||||
-- wait for 50 ns;
|
||||
-- SPISIGNAL <= x"B2";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
--
|
||||
-- -- write 0xB8, read 0xC3
|
||||
-- wait until rising_edge(data_ready_o);
|
||||
-- mosi_data_i <= x"B8";
|
||||
-- wait until falling_edge(data_ready_o);
|
||||
-- SPISIGNAL <= x"C3";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
-- en_i <= '0';
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- CPOL,CPHA = 01
|
||||
-- en_i <= '1';
|
||||
--
|
||||
-- -- write 0xA7, read 0xB2
|
||||
-- mosi_data_i <= x"A7";
|
||||
-- wait until falling_edge(cs_o);
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- SPISIGNAL <= x"B2";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
--
|
||||
-- -- write 0xB8, read 0xC3
|
||||
-- wait until rising_edge(data_ready_o);
|
||||
-- mosi_data_i <= x"B8";
|
||||
-- wait until rising_edge(sclk_o);
|
||||
-- SPISIGNAL <= x"C3";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
-- en_i <= '0';
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- -- CPOL,CPHA = 11
|
||||
-- en_i <= '1';
|
||||
--
|
||||
-- -- write 0xA7, read 0xB2
|
||||
-- mosi_data_i <= x"A7";
|
||||
-- wait until falling_edge(cs_o);
|
||||
-- wait until falling_edge(sclk_o);
|
||||
-- SPISIGNAL <= x"B2";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
--
|
||||
-- -- write 0xB8, read 0xC3
|
||||
-- wait until rising_edge(data_ready_o);
|
||||
-- mosi_data_i <= x"B8";
|
||||
-- wait until falling_edge(sclk_o);
|
||||
-- SPISIGNAL <= x"C3";
|
||||
-- spiWrite <= '1';
|
||||
-- wait until rising_edge(spiWriteDone);
|
||||
-- spiWrite <= '0';
|
||||
-- en_i <= '0';
|
||||
|
||||
|
||||
|
||||
wait for 1 us;
|
||||
|
||||
assert false
|
||||
report "SIM DONE"
|
||||
severity failure;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,74 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "c_clkfreq" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set SPI_parameters [ipgui::add_group $IPINST -name "SPI parameters" -parent ${Page_0}]
|
||||
set c_sclkfreq [ipgui::add_param $IPINST -name "c_sclkfreq" -parent ${SPI_parameters}]
|
||||
set_property tooltip {Desired SCLK frequency (must be less or equal than aclk_freq/8)} ${c_sclkfreq}
|
||||
ipgui::add_param $IPINST -name "c_cpol" -parent ${SPI_parameters}
|
||||
ipgui::add_param $IPINST -name "c_cpha" -parent ${SPI_parameters}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.c_clkfreq { PARAM_VALUE.c_clkfreq } {
|
||||
# Procedure called to update c_clkfreq when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.c_clkfreq { PARAM_VALUE.c_clkfreq } {
|
||||
# Procedure called to validate c_clkfreq
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.c_cpha { PARAM_VALUE.c_cpha } {
|
||||
# Procedure called to update c_cpha when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.c_cpha { PARAM_VALUE.c_cpha } {
|
||||
# Procedure called to validate c_cpha
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.c_cpol { PARAM_VALUE.c_cpol } {
|
||||
# Procedure called to update c_cpol when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.c_cpol { PARAM_VALUE.c_cpol } {
|
||||
# Procedure called to validate c_cpol
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.c_sclkfreq { PARAM_VALUE.c_sclkfreq } {
|
||||
# Procedure called to update c_sclkfreq when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.c_sclkfreq { PARAM_VALUE.c_sclkfreq } {
|
||||
# Procedure called to validate c_sclkfreq
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.c_clkfreq { MODELPARAM_VALUE.c_clkfreq PARAM_VALUE.c_clkfreq } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.c_clkfreq}] ${MODELPARAM_VALUE.c_clkfreq}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.c_sclkfreq { MODELPARAM_VALUE.c_sclkfreq PARAM_VALUE.c_sclkfreq } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.c_sclkfreq}] ${MODELPARAM_VALUE.c_sclkfreq}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.c_cpol { MODELPARAM_VALUE.c_cpol PARAM_VALUE.c_cpol } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.c_cpol}] ${MODELPARAM_VALUE.c_cpol}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.c_cpha { MODELPARAM_VALUE.c_cpha PARAM_VALUE.c_cpha } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.c_cpha}] ${MODELPARAM_VALUE.c_cpha}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user