Add IPs
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130
LAB3/ip/axi4-stream-spi-master/cocotb/.gitignore
vendored
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130
LAB3/ip/axi4-stream-spi-master/cocotb/.gitignore
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# Byte-compiled / optimized / DLL files
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__pycache__/
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*.py[cod]
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*$py.class
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# C extensions
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*.so
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# Distribution / packaging
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.Python
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build/
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develop-eggs/
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dist/
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downloads/
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eggs/
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.eggs/
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lib/
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lib64/
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parts/
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sdist/
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var/
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wheels/
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pip-wheel-metadata/
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share/python-wheels/
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*.egg-info/
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.installed.cfg
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*.egg
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MANIFEST
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# PyInstaller
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# Usually these files are written by a python script from a template
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# before PyInstaller builds the exe, so as to inject date/other infos into it.
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*.manifest
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*.spec
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# Installer logs
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pip-log.txt
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pip-delete-this-directory.txt
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# Unit test / coverage reports
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htmlcov/
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.tox/
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.nox/
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.coverage
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.coverage.*
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.cache
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nosetests.xml
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coverage.xml
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*.cover
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.hypothesis/
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.pytest_cache/
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# Translations
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*.mo
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*.pot
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# Django stuff:
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*.log
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local_settings.py
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db.sqlite3
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# Flask stuff:
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instance/
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# Scrapy stuff:
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.scrapy
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# Sphinx documentation
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docs/_build/
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# PyBuilder
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target/
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# Jupyter Notebook
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.ipynb_checkpoints
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# IPython
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profile_default/
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ipython_config.py
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# pyenv
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.python-version
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# pipenv
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# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
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# However, in case of collaboration, if having platform-specific dependencies or dependencies
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# having no cross-platform support, pipenv may install dependencies that don't work, or not
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# install all needed dependencies.
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#Pipfile.lock
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# celery beat schedule file
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celerybeat-schedule
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# SageMath parsed files
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*.sage.py
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# Environments
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.env
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.venv
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env/
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venv/
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ENV/
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env.bak/
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venv.bak/
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# Spyder project settings
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.spyderproject
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.spyproject
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# Rope project settings
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.ropeproject
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# mkdocs documentation
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/site
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# mypy
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.mypy_cache/
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.dmypy.json
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dmypy.json
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# Pyre type checker
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.pyre/
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# Cocotb build folder
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build/
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# Cocotb results
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results.xml
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20
LAB3/ip/axi4-stream-spi-master/cocotb/Makefile
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20
LAB3/ip/axi4-stream-spi-master/cocotb/Makefile
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export PYTHON_BIN=python3
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PWD := $(shell pwd)
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SIM ?= ghdl
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SIM_ARGS ?= --wave=$(PWD)/build/waveform.ghw -gc_clkfreq=100000000 -gc_sclkfreq=10000000
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GHDL_ARGS ?= -fsynopsys
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TOPLEVEL_LANG = vhdl
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SIM_BUILD = $(PWD)/build
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MODULE = tester_axis_lw_spi_master
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TOPLEVEL = axis_lw_spi_master
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HDL_DIR = $(PWD)/../hdl
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VHDL_SOURCES = \
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$(HDL_DIR)/spi_master_lightweight/rtl/lw_spi_master.vhd \
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$(HDL_DIR)/axis_lw_spi_master.vhd
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include $(shell cocotb-config --makefiles)/Makefile.sim
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#!/usr/bin/env python3
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import secrets
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, ClockCycles
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from cocotbext.axi4stream.drivers import Axi4StreamMaster
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from cocotbext.axi4stream.monitors import Axi4Stream
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from cocotbext.spi import SpiSlaveBase, SpiSignals, SpiConfig
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CLK_PERIOD = 10
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class SimpleSpiSlave(SpiSlaveBase):
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def __init__(self, signals, config, data):
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self._config = config
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self.content = 0
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self.data = data
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super().__init__(signals)
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async def get_content(self):
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await self.idle.wait()
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return self.content
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async def _transaction(self, frame_start, frame_end):
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await frame_start
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self.idle.clear()
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self._miso.value = 1 if self.data[0] & 0x80 else 0
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self.content = int(await self._shift(len(self.data) * 8 - 1, tx_word=int.from_bytes(self.data, 'big')))
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await RisingEdge(self._sclk)
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self.content = self.content << 1 | int(self._mosi.value.integer)
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await frame_end
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async def setup_dut(dut):
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cocotb.fork(Clock(dut.aclk, CLK_PERIOD, "ns").start())
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@cocotb.test()
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async def test_spi(dut, length=32):
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"""TODO"""
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spi_signals = SpiSignals(
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sclk = dut.sclk,
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mosi = dut.mosi,
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miso = dut.miso,
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cs = dut.cs
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)
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spi_config = SpiConfig(
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word_width = 8,
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cpol = False,
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cpha = False,
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data_output_idle = 0,
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msb_first = True
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)
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mosi_tx = secrets.randbits(length * 8).to_bytes(length, 'little')
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miso_tx = secrets.randbits(length * 8).to_bytes(length, 'little')
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spi_slave = SimpleSpiSlave(spi_signals, spi_config, miso_tx)
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miso_rx = bytearray()
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axis_m = Axi4StreamMaster(dut, "s_axis", dut.aclk)
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axis_monitor = Axi4Stream(dut, "m_axis", dut.aclk, packets=False)
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axis_monitor.add_callback(lambda data: miso_rx.extend(data))
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await setup_dut(dut)
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await ClockCycles(dut.aclk, 10)
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await axis_m.write([b for b in mosi_tx])
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mosi_rx = (await spi_slave.get_content()).to_bytes(length, 'big')
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await ClockCycles(dut.aclk, 10)
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assert mosi_tx == mosi_rx, "Received MOSI data does not match transmitted one"
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assert miso_tx == miso_rx, "Received MISO data does not match transmitted one"
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53
LAB3/ip/axi4-stream-spi-master/cocotb/waveforms.gtkw
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53
LAB3/ip/axi4-stream-spi-master/cocotb/waveforms.gtkw
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@@ -0,0 +1,53 @@
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Fri Mar 25 16:24:27 2022
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[*]
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[dumpfile] "/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master/sim/build/waveform.ghw"
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[dumpfile_mtime] "Fri Mar 25 16:23:35 2022"
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[dumpfile_size] 3066
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[savefile] "/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master/sim/waveforms.gtkw"
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[timestart] 0
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[size] 1920 1001
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[pos] -27 -24
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*-27.176317 7190000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.axis_lw_spi_master.
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[treeopen] top.axis_lw_spi_master.inst_lw_spi_master.
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[sst_width] 281
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[signals_width] 200
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[sst_expanded] 1
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[sst_vpaned_height] 285
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@28
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top.axis_lw_spi_master.clk
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@200
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-
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@28
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top.axis_lw_spi_master.s_axis_tvalid
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top.axis_lw_spi_master.s_axis_tready
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@22
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#{top.axis_lw_spi_master.s_axis_tdata[7:0]} top.axis_lw_spi_master.s_axis_tdata[7] top.axis_lw_spi_master.s_axis_tdata[6] top.axis_lw_spi_master.s_axis_tdata[5] top.axis_lw_spi_master.s_axis_tdata[4] top.axis_lw_spi_master.s_axis_tdata[3] top.axis_lw_spi_master.s_axis_tdata[2] top.axis_lw_spi_master.s_axis_tdata[1] top.axis_lw_spi_master.s_axis_tdata[0]
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@200
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-
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@28
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top.axis_lw_spi_master.m_axis_tvalid
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@22
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#{top.axis_lw_spi_master.m_axis_tdata[7:0]} top.axis_lw_spi_master.m_axis_tdata[7] top.axis_lw_spi_master.m_axis_tdata[6] top.axis_lw_spi_master.m_axis_tdata[5] top.axis_lw_spi_master.m_axis_tdata[4] top.axis_lw_spi_master.m_axis_tdata[3] top.axis_lw_spi_master.m_axis_tdata[2] top.axis_lw_spi_master.m_axis_tdata[1] top.axis_lw_spi_master.m_axis_tdata[0]
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@200
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-
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@28
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top.axis_lw_spi_master.inst_lw_spi_master.en_i
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@22
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#{top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[7:0]} top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[7] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[6] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[5] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[4] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[3] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[2] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[1] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[0]
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#{top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[7:0]} top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[7] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[6] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[5] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[4] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[3] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[2] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[1] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[0]
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@28
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top.axis_lw_spi_master.inst_lw_spi_master.data_ready_o
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@200
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-
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@28
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top.axis_lw_spi_master.sclk
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top.axis_lw_spi_master.mosi
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top.axis_lw_spi_master.miso
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@29
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top.axis_lw_spi_master.cs
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[pattern_trace] 1
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[pattern_trace] 0
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