From 0d805b93b6df18ac7b19093bade96bd56404e857 Mon Sep 17 00:00:00 2001 From: Davide Date: Fri, 11 Apr 2025 01:50:19 +0200 Subject: [PATCH] Refactor RGB to Grayscale Converter and Add Divider Component - Updated the rgb2gray.vhd file to improve readability and structure, including consistent casing for keywords and signals. - Implemented a new divider_by_3 component to calculate the grayscale value by dividing the sum of RGB channels by 3. - Enhanced the state machine in rgb2gray to handle RGB input and output grayscale values correctly. - Updated the Vivado project file to include the new divider_by_3.vhd for synthesis and simulation. - Modified vhdl_ls.toml to include unisim files for third-party library support. --- LAB2/src/divider_by_3.vhd | 53 ++ LAB2/src/lab_2/lab_2.bd | 1085 ++++++++++++++++--------------------- LAB2/src/rgb2gray.vhd | 115 +++- LAB2/vivado/lab2/lab2.xpr | 14 +- vhdl_ls.toml | 9 +- 5 files changed, 643 insertions(+), 633 deletions(-) create mode 100644 LAB2/src/divider_by_3.vhd diff --git a/LAB2/src/divider_by_3.vhd b/LAB2/src/divider_by_3.vhd new file mode 100644 index 0000000..9665824 --- /dev/null +++ b/LAB2/src/divider_by_3.vhd @@ -0,0 +1,53 @@ +---------- DEFAULT LIBRARIES ------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.MATH_REAL.ALL; +------------------------------------ + +ENTITY divider_by_3 IS + GENERIC ( + BIT_DEPTH : INTEGER := 8 + ); + PORT ( + R : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0); + G : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0); + B : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0); + grey : OUT STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0) + ); +END divider_by_3; + +ARCHITECTURE Behavioral OF divider_by_3 IS + -- Constant to calculate the multiplier for approximating division by 3 + CONSTANT DIVISION_MULTIPLIER : INTEGER := INTEGER(floor(real(2 ** (BIT_DEPTH + 2)) / 3.0)); + + -- Constant to calculate the length of the result signal + CONSTANT RESULT_WIDTH : INTEGER := (2 * BIT_DEPTH) + 2; + + -- Signals to hold the sum of the RGB channels and the intermediate results + SIGNAL rgb_sum_extended : UNSIGNED(BIT_DEPTH + 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL scaled_result : UNSIGNED(RESULT_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL grayscale_value : UNSIGNED(BIT_DEPTH - 1 DOWNTO 0) := (OTHERS => '0'); +BEGIN + + -- Explanation of how the division by 3 is performed: + -- 1. The sum of the RGB channels (R + G + B) is calculated and extended to avoid overflow. + -- 2. The sum is multiplied by a precomputed constant (DIVISION_MULTIPLIER), which is approximately equal to (2^(BIT_DEPTH + 2)) / 3. + -- This scales the value up to prepare for the division. + -- 3. The result of the multiplication is then right-shifted by a specific number of bits. + -- This operation effectively scales the value back down, approximating the division by 3. + -- 4. The final grayscale value is extracted from the result and converted back to a std_logic_vector. + + -- Calculate the sum of the RGB channels + rgb_sum_extended <= UNSIGNED(R) + UNSIGNED(G) + UNSIGNED(B) + TO_UNSIGNED(2, BIT_DEPTH + 2); + + -- Multiply the sum by the precomputed multiplier + scaled_result <= rgb_sum_extended * TO_UNSIGNED(DIVISION_MULTIPLIER, RESULT_WIDTH); + + -- Extract the grayscale value from the scaled result by right-shifting + grayscale_value <= scaled_result(RESULT_WIDTH - 1 DOWNTO RESULT_WIDTH - BIT_DEPTH - 1); + + -- Assign the grayscale value to the output + grey <= STD_LOGIC_VECTOR(grayscale_value); + +END Behavioral; \ No newline at end of file diff --git a/LAB2/src/lab_2/lab_2.bd b/LAB2/src/lab_2/lab_2.bd index 22ed7a5..b8c417a 100644 --- a/LAB2/src/lab_2/lab_2.bd +++ b/LAB2/src/lab_2/lab_2.bd @@ -6,14 +6,10 @@ "name": "lab_2", "rev_ctrl_bd_flag": "RevCtrlBdOff", "synth_flow_mode": "None", - "tool_version": "2020.2", - "validated": "true" + "tool_version": "2020.2" }, "design_tree": { "bram_writer_0": "", - "depacketizer_0": "", - "packetizer_0": "", - "rgb2gray_0": "", "led_blinker_0": "", "img_conv_0": "", "led_blinker_1": "", @@ -21,7 +17,10 @@ "system_ila_0": "", "clk_wiz_0": "", "proc_sys_reset_1": "", - "AXI4Stream_UART_0": "" + "AXI4Stream_UART_0": "", + "depacketizer_0": "", + "packetizer_0": "", + "rgb2gray_0": "" }, "interface_ports": { "usb_uart": { @@ -43,21 +42,9 @@ "type": "clk", "direction": "I", "parameters": { - "CLK_DOMAIN": { - "value": "lab_2_sys_clock", - "value_src": "default" - }, "FREQ_HZ": { "value": "100000000" }, - "FREQ_TOLERANCE_HZ": { - "value": "0", - "value_src": "default" - }, - "INSERT_VIP": { - "value": "0", - "value_src": "default" - }, "PHASE": { "value": "0.000" } @@ -67,10 +54,6 @@ "type": "rst", "direction": "I", "parameters": { - "INSERT_VIP": { - "value": "0", - "value_src": "default" - }, "POLARITY": { "value": "ACTIVE_HIGH" } @@ -224,571 +207,6 @@ } } }, - "depacketizer_0": { - "vlnv": "xilinx.com:module_ref:depacketizer:1.0", - "xci_name": "lab_2_depacketizer_0_0", - "xci_path": "ip\\lab_2_depacketizer_0_0\\lab_2_depacketizer_0_0.xci", - "inst_hier_path": "depacketizer_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "depacketizer", - "boundary_crc": "0x0" - }, - "interface_ports": { - "m_axis": { - "mode": "Master", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "m_axis_tdata", - "direction": "O", - "left": "7", - "right": "0" - }, - "TLAST": { - "physical_name": "m_axis_tlast", - "direction": "O" - }, - "TVALID": { - "physical_name": "m_axis_tvalid", - "direction": "O" - }, - "TREADY": { - "physical_name": "m_axis_tready", - "direction": "I" - } - } - }, - "s_axis": { - "mode": "Slave", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "0", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "s_axis_tdata", - "direction": "I", - "left": "7", - "right": "0" - }, - "TVALID": { - "physical_name": "s_axis_tvalid", - "direction": "I" - }, - "TREADY": { - "physical_name": "s_axis_tready", - "direction": "O" - } - } - } - }, - "ports": { - "clk": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "m_axis:s_axis", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "aresetn", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - } - }, - "aresetn": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - } - } - }, - "packetizer_0": { - "vlnv": "xilinx.com:module_ref:packetizer:1.0", - "xci_name": "lab_2_packetizer_0_0", - "xci_path": "ip\\lab_2_packetizer_0_0\\lab_2_packetizer_0_0.xci", - "inst_hier_path": "packetizer_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "packetizer", - "boundary_crc": "0x0" - }, - "interface_ports": { - "m_axis": { - "mode": "Master", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "0", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "m_axis_tdata", - "direction": "O", - "left": "7", - "right": "0" - }, - "TVALID": { - "physical_name": "m_axis_tvalid", - "direction": "O" - }, - "TREADY": { - "physical_name": "m_axis_tready", - "direction": "I" - } - } - }, - "s_axis": { - "mode": "Slave", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "s_axis_tdata", - "direction": "I", - "left": "7", - "right": "0" - }, - "TLAST": { - "physical_name": "s_axis_tlast", - "direction": "I" - }, - "TVALID": { - "physical_name": "s_axis_tvalid", - "direction": "I" - }, - "TREADY": { - "physical_name": "s_axis_tready", - "direction": "O" - } - } - } - }, - "ports": { - "clk": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "m_axis:s_axis", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "aresetn", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - } - }, - "aresetn": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - } - } - }, - "rgb2gray_0": { - "vlnv": "xilinx.com:module_ref:rgb2gray:1.0", - "xci_name": "lab_2_rgb2gray_0_0", - "xci_path": "ip\\lab_2_rgb2gray_0_0\\lab_2_rgb2gray_0_0.xci", - "inst_hier_path": "rgb2gray_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "rgb2gray", - "boundary_crc": "0x0" - }, - "interface_ports": { - "m_axis": { - "mode": "Master", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "m_axis_tdata", - "direction": "O", - "left": "7", - "right": "0" - }, - "TLAST": { - "physical_name": "m_axis_tlast", - "direction": "O" - }, - "TVALID": { - "physical_name": "m_axis_tvalid", - "direction": "O" - }, - "TREADY": { - "physical_name": "m_axis_tready", - "direction": "I" - } - } - }, - "s_axis": { - "mode": "Slave", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "s_axis_tdata", - "direction": "I", - "left": "7", - "right": "0" - }, - "TLAST": { - "physical_name": "s_axis_tlast", - "direction": "I" - }, - "TVALID": { - "physical_name": "s_axis_tvalid", - "direction": "I" - }, - "TREADY": { - "physical_name": "s_axis_tready", - "direction": "O" - } - } - } - }, - "ports": { - "clk": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "m_axis:s_axis", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "resetn", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - } - }, - "resetn": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - } - } - }, "led_blinker_0": { "vlnv": "xilinx.com:module_ref:led_blinker:1.0", "xci_name": "lab_2_led_blinker_0_0", @@ -1166,9 +584,473 @@ "value": "true" } } + }, + "depacketizer_0": { + "vlnv": "xilinx.com:module_ref:depacketizer:1.0", + "xci_name": "lab_2_depacketizer_0_0", + "xci_path": "ip\\lab_2_depacketizer_0_0\\lab_2_depacketizer_0_0.xci", + "inst_hier_path": "depacketizer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "depacketizer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + }, + "packetizer_0": { + "vlnv": "xilinx.com:module_ref:packetizer:1.0", + "xci_name": "lab_2_packetizer_0_0", + "xci_path": "ip\\lab_2_packetizer_0_0\\lab_2_packetizer_0_0.xci", + "inst_hier_path": "packetizer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "packetizer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + }, + "rgb2gray_0": { + "vlnv": "xilinx.com:module_ref:rgb2gray:1.0", + "xci_name": "lab_2_rgb2gray_0_0", + "xci_path": "ip\\lab_2_rgb2gray_0_0\\lab_2_rgb2gray_0_0.xci", + "inst_hier_path": "rgb2gray_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "rgb2gray", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "resetn", + "value_src": "constant" + } + } + }, + "resetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } } }, "interface_nets": { + "Conn": { + "interface_ports": [ + "rgb2gray_0/s_axis", + "depacketizer_0/m_axis", + "system_ila_0/SLOT_0_AXIS" + ] + }, "AXI4Stream_UART_0_M00_AXIS_RX": { "interface_ports": [ "AXI4Stream_UART_0/M00_AXIS_RX", @@ -1181,11 +1063,10 @@ "AXI4Stream_UART_0/S00_AXIS_TX" ] }, - "Conn": { + "AXI4Stream_UART_0_UART": { "interface_ports": [ - "rgb2gray_0/s_axis", - "depacketizer_0/m_axis", - "system_ila_0/SLOT_0_AXIS" + "usb_uart", + "AXI4Stream_UART_0/UART" ] }, "rgb2gray_0_m_axis": { @@ -1201,12 +1082,6 @@ "packetizer_0/s_axis", "system_ila_0/SLOT_1_AXIS" ] - }, - "AXI4Stream_UART_0_UART": { - "interface_ports": [ - "usb_uart", - "AXI4Stream_UART_0/UART" - ] } }, "nets": { @@ -1214,9 +1089,6 @@ "ports": [ "clk_wiz_0/clk_out1", "img_conv_0/clk", - "packetizer_0/clk", - "depacketizer_0/clk", - "rgb2gray_0/clk", "led_blinker_0/clk", "led_blinker_1/clk", "led_blinker_2/clk", @@ -1225,23 +1097,26 @@ "proc_sys_reset_1/slowest_sync_clk", "AXI4Stream_UART_0/clk_uart", "AXI4Stream_UART_0/m00_axis_rx_aclk", - "AXI4Stream_UART_0/s00_axis_tx_aclk" + "AXI4Stream_UART_0/s00_axis_tx_aclk", + "depacketizer_0/clk", + "packetizer_0/clk", + "rgb2gray_0/clk" ] }, "proc_sys_reset_0_peripheral_aresetn": { "ports": [ "proc_sys_reset_1/peripheral_aresetn", "img_conv_0/aresetn", - "packetizer_0/aresetn", - "depacketizer_0/aresetn", - "rgb2gray_0/resetn", "led_blinker_0/aresetn", "led_blinker_1/aresetn", "led_blinker_2/aresetn", "bram_writer_0/aresetn", "system_ila_0/resetn", "AXI4Stream_UART_0/m00_axis_rx_aresetn", - "AXI4Stream_UART_0/s00_axis_tx_aresetn" + "AXI4Stream_UART_0/s00_axis_tx_aresetn", + "depacketizer_0/aresetn", + "packetizer_0/aresetn", + "rgb2gray_0/resetn" ] }, "bram_writer_0_conv_data": { diff --git a/LAB2/src/rgb2gray.vhd b/LAB2/src/rgb2gray.vhd index 65e4f96..87b6458 100644 --- a/LAB2/src/rgb2gray.vhd +++ b/LAB2/src/rgb2gray.vhd @@ -1,36 +1,111 @@ ---------- DEFAULT LIBRARIES ------- -library IEEE; - use IEEE.STD_LOGIC_1164.all; - use IEEE.NUMERIC_STD.ALL; - use IEEE.MATH_REAL.all; -- For LOG **FOR A CONSTANT!!** +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.MATH_REAL.ALL; -- For logarithmic calculations (used for a constant) ------------------------------------ ---------- OTHER LIBRARIES --------- -- NONE ------------------------------------ -entity rgb2gray is - Port ( - clk : in std_logic; - resetn : in std_logic; +ENTITY rgb2gray IS + PORT ( + clk : IN STD_LOGIC; + resetn : IN STD_LOGIC; - m_axis_tvalid : out std_logic; - m_axis_tdata : out std_logic_vector(7 downto 0); - m_axis_tready : in std_logic; - m_axis_tlast : out std_logic; + m_axis_tvalid : OUT STD_LOGIC; + m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m_axis_tready : IN STD_LOGIC; + m_axis_tlast : OUT STD_LOGIC; - s_axis_tvalid : in std_logic; - s_axis_tdata : in std_logic_vector(7 downto 0); - s_axis_tready : out std_logic; - s_axis_tlast : in std_logic + s_axis_tvalid : IN STD_LOGIC; + s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s_axis_tready : OUT STD_LOGIC; + s_axis_tlast : IN STD_LOGIC ); -end rgb2gray; +END rgb2gray; -architecture Behavioral of rgb2gray is +ARCHITECTURE Behavioral OF rgb2gray IS + COMPONENT divider_by_3 + GENERIC ( + BIT_DEPTH : INTEGER := 8 + ); + PORT ( + R : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0); + G : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0); + B : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0); + grey : OUT STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0)); + END COMPONENT divider_by_3; + TYPE state_type IS (WAIT_R, WAIT_G, WAIT_B); + SIGNAL state : state_type := WAIT_R; -begin + SIGNAL r_val, g_val, b_val : unsigned(7 DOWNTO 0); + SIGNAL gray : unsigned(7 DOWNTO 0); +BEGIN -end Behavioral; + DIVIDER : divider_by_3 + GENERIC MAP( + BIT_DEPTH => 8 + ) + PORT MAP( + R => STD_LOGIC_VECTOR(r_val), + G => STD_LOGIC_VECTOR(g_val), + B => STD_LOGIC_VECTOR(b_val), + grey => STD_LOGIC_VECTOR(gray) + ); + + PROCESS (clk) + BEGIN + IF rising_edge(clk) THEN + IF resetn = '0' THEN + -- Reset all signals + state <= WAIT_R; + s_axis_tready <= '1'; + m_axis_tvalid <= '0'; + m_axis_tlast <= '0'; + m_axis_tdata <= (OTHERS => '0'); + r_val <= (OTHERS => '0'); + g_val <= (OTHERS => '0'); + b_val <= (OTHERS => '0'); + gray <= (OTHERS => '0'); + ELSE + -- Default control signals + s_axis_tready <= '1'; + m_axis_tvalid <= '0'; + m_axis_tlast <= '0'; + + CASE state IS + WHEN WAIT_R => + IF s_axis_tvalid = '1' THEN + r_val <= unsigned(s_axis_tdata); + state <= WAIT_G; + END IF; + + WHEN WAIT_G => + IF s_axis_tvalid = '1' THEN + g_val <= unsigned(s_axis_tdata); + state <= WAIT_B; + END IF; + + WHEN WAIT_B => + IF s_axis_tvalid = '1' THEN + b_val <= unsigned(s_axis_tdata); + END IF; + + -- If downstream is ready, send the grayscale pixel + IF m_axis_tready = '1' THEN + m_axis_tdata <= STD_LOGIC_VECTOR(gray); + m_axis_tvalid <= '1'; + m_axis_tlast <= s_axis_tlast; + state <= WAIT_R; + END IF; + END CASE; + END IF; + END IF; + END PROCESS; + +END ARCHITECTURE; \ No newline at end of file diff --git a/LAB2/vivado/lab2/lab2.xpr b/LAB2/vivado/lab2/lab2.xpr index 5017af4..5e66faf 100644 --- a/LAB2/vivado/lab2/lab2.xpr +++ b/LAB2/vivado/lab2/lab2.xpr @@ -95,6 +95,12 @@ + + + + + + @@ -196,9 +202,7 @@ - - Vivado Synthesis Defaults - + @@ -207,9 +211,7 @@ - - Default settings for Implementation. - + diff --git a/vhdl_ls.toml b/vhdl_ls.toml index 3148568..2653b30 100644 --- a/vhdl_ls.toml +++ b/vhdl_ls.toml @@ -11,7 +11,7 @@ lab1_lib.files = [ ] lab2_lib.files = [ - "LAB2/src/**/*.vhd", + "LAB2/src/*.vhd", "LAB2/sim/**/*.vhd" ] @@ -23,4 +23,9 @@ lab2_lib.files = [ xpm.files = [ "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" ] -xpm.is_third_party = true \ No newline at end of file +xpm.is_third_party = true + +unisim.files = [ + "C:/Xilinx/Vivado/2020.2/data/vhdl/src/unisims/**/*.vhd" +] +unisim.is_third_party = true \ No newline at end of file