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Add loopback design files and update project configurations

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- Created a new loopback design file (loopback.bda) with nodes and edges defined in GraphML format.
- Added a new Vivado project file for loopback (loopback.xpr) with updated configurations.
- Introduced a new testbench for image convolution (img_conv_tb.vhd) in the simulation sources.
- Updated the main project file (lab2.xpr) to reflect changes in source files and top module for simulation.
- Removed obsolete project files (pak_depak.xpr.zip) and updated paths for existing source files.
This commit is contained in:
Davide Cavagnola
2025-04-25 11:16:54 +02:00
parent 835b4d0ab8
commit 14a6be00d6
13 changed files with 237 additions and 107 deletions
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2
LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
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@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri Apr 25 00:08:55 2025
--Date : Fri Apr 25 10:55:47 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target lab_2_wrapper.bd
--Design : lab_2_wrapper

28
LAB2/design/lab_2/lab_2.bd
View File

@@ -1169,20 +1169,6 @@
}
},
"interface_nets": {
"Conn": {
"interface_ports": [
"rgb2gray_0/s_axis",
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
]
},
"rgb2gray_0_m_axis": {
"interface_ports": [
"rgb2gray_0/m_axis",
"bram_writer_0/s_axis",
"system_ila_0/SLOT_2_AXIS"
]
},
"img_conv_0_m_axis": {
"interface_ports": [
"img_conv_0/m_axis",
@@ -1207,6 +1193,20 @@
"packetizer_0/m_axis",
"AXI4Stream_UART_0/S00_AXIS_TX"
]
},
"Conn": {
"interface_ports": [
"rgb2gray_0/s_axis",
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
]
},
"rgb2gray_0_m_axis": {
"interface_ports": [
"rgb2gray_0/m_axis",
"bram_writer_0/s_axis",
"system_ila_0/SLOT_2_AXIS"
]
}
},
"nets": {

12
LAB2/design/lab_2/lab_2.bda
View File

@@ -26,17 +26,17 @@
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n0">
<node id="n2">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0">
</edge>
<edge id="e1" source="n0" target="n2">
<edge id="e1" source="n0" target="n1">
</edge>
</graph>
</graphml>

18
LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd → LAB2/design/loopback/hdl/loopback_wrapper.vhd
View File

@@ -1,36 +1,36 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Thu Apr 24 19:38:15 2025
--Date : Fri Apr 25 10:52:31 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target pak_depak_wrapper.bd
--Design : pak_depak_wrapper
--Command : generate_target loopback_wrapper.bd
--Design : loopback_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pak_depak_wrapper is
entity loopback_wrapper is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end pak_depak_wrapper;
end loopback_wrapper;
architecture STRUCTURE of pak_depak_wrapper is
component pak_depak is
architecture STRUCTURE of loopback_wrapper is
component loopback is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC
);
end component pak_depak;
end component loopback;
begin
pak_depak_i: component pak_depak
loopback_i: component loopback
port map (
reset => reset,
sys_clock => sys_clock,

36
LAB2/design/pak_depak/pak_depak.bd → LAB2/design/loopback/loopback.bd
View File

@@ -3,7 +3,7 @@
"design_info": {
"boundary_crc": "0x9157799052A71E23",
"device": "xc7a35tcpg236-1",
"name": "pak_depak",
"name": "loopback",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2020.2",
@@ -41,7 +41,7 @@
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "pak_depak_sys_clock",
"value": "loopback_sys_clock",
"value_src": "default"
},
"FREQ_HZ": {
@@ -64,8 +64,8 @@
"components": {
"proc_sys_reset_0": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "pak_depak_proc_sys_reset_0_0",
"xci_path": "ip\\pak_depak_proc_sys_reset_0_0\\pak_depak_proc_sys_reset_0_0.xci",
"xci_name": "loopback_proc_sys_reset_0_0",
"xci_path": "ip\\loopback_proc_sys_reset_0_0\\loopback_proc_sys_reset_0_0.xci",
"inst_hier_path": "proc_sys_reset_0",
"parameters": {
"RESET_BOARD_INTERFACE": {
@@ -78,8 +78,8 @@
},
"clk_wiz_0": {
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
"xci_name": "pak_depak_clk_wiz_0_0",
"xci_path": "ip\\pak_depak_clk_wiz_0_0\\pak_depak_clk_wiz_0_0.xci",
"xci_name": "loopback_clk_wiz_0_0",
"xci_path": "ip\\loopback_clk_wiz_0_0\\loopback_clk_wiz_0_0.xci",
"inst_hier_path": "clk_wiz_0",
"parameters": {
"CLK_IN1_BOARD_INTERFACE": {
@@ -95,8 +95,8 @@
},
"AXI4Stream_UART_0": {
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
"xci_name": "pak_depak_AXI4Stream_UART_0_0",
"xci_path": "ip\\pak_depak_AXI4Stream_UART_0_0\\pak_depak_AXI4Stream_UART_0_0.xci",
"xci_name": "loopback_AXI4Stream_UART_0_0",
"xci_path": "ip\\loopback_AXI4Stream_UART_0_0\\loopback_AXI4Stream_UART_0_0.xci",
"inst_hier_path": "AXI4Stream_UART_0",
"parameters": {
"UART_BOARD_INTERFACE": {
@@ -109,8 +109,8 @@
},
"packetizer_0": {
"vlnv": "xilinx.com:module_ref:packetizer:1.0",
"xci_name": "pak_depak_packetizer_0_0",
"xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci",
"xci_name": "loopback_packetizer_0_0",
"xci_path": "ip\\loopback_packetizer_0_0\\loopback_packetizer_0_0.xci",
"inst_hier_path": "packetizer_0",
"reference_info": {
"ref_type": "hdl",
@@ -296,8 +296,8 @@
},
"depacketizer_0": {
"vlnv": "xilinx.com:module_ref:depacketizer:1.0",
"xci_name": "pak_depak_depacketizer_0_0",
"xci_path": "ip\\pak_depak_depacketizer_0_0\\pak_depak_depacketizer_0_0.xci",
"xci_name": "loopback_depacketizer_0_0",
"xci_path": "ip\\loopback_depacketizer_0_0\\loopback_depacketizer_0_0.xci",
"inst_hier_path": "depacketizer_0",
"reference_info": {
"ref_type": "hdl",
@@ -489,12 +489,6 @@
"depacketizer_0/s_axis"
]
},
"depacketizer_0_m_axis": {
"interface_ports": [
"depacketizer_0/m_axis",
"packetizer_0/s_axis"
]
},
"packetizer_0_m_axis": {
"interface_ports": [
"packetizer_0/m_axis",
@@ -506,6 +500,12 @@
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
"depacketizer_0_m_axis": {
"interface_ports": [
"depacketizer_0/m_axis",
"packetizer_0/s_axis"
]
}
},
"nets": {

4
LAB2/design/pak_depak/pak_depak.bda → LAB2/design/loopback/loopback.bda
View File

@@ -22,11 +22,11 @@
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">pak_depak</data>
<data key="VM">loopback</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">pak_depak</data>
<data key="VM">loopback</data>
<data key="VT">BC</data>
</node>
<node id="n2">

BIN
LAB2/vivado/archived/lab2.xpr.zip
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BIN
LAB2/vivado/archived/loopback.xpr.zip Normal file
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Binary file not shown.

BIN
LAB2/vivado/archived/pak_depak.xpr.zip
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Binary file not shown.

128
LAB2/vivado/lab2/lab2.srcs/sim_1/new/img_conv_tb.vhd Normal file
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@@ -0,0 +1,128 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/16/2025 04:23:36 PM
-- Design Name:
-- Module Name: img_conv_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity img_conv_tb is
-- Port ( );
end img_conv_tb;
architecture Behavioral of img_conv_tb is
component img_conv is
generic(
LOG2_N_COLS: POSITIVE :=8;
LOG2_N_ROWS: POSITIVE :=8
);
port (
clk : in std_logic;
aresetn : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tlast : out std_logic;
conv_addr: out std_logic_vector(LOG2_N_COLS+LOG2_N_ROWS-1 downto 0);
conv_data: in std_logic_vector(6 downto 0);
start_conv: in std_logic;
done_conv: out std_logic
);
end component;
constant LOG2_N_COLS: POSITIVE :=2;
constant LOG2_N_ROWS: POSITIVE :=2;
type mem_type is array(0 to (2**LOG2_N_COLS)*(2**LOG2_N_ROWS)-1) of std_logic_vector(6 downto 0);
signal mem : mem_type := (0=>"0000001",others => (others => '0'));
signal clk : std_logic :='0';
signal aresetn : std_logic :='0';
signal m_axis_tdata : std_logic_vector(7 downto 0);
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tlast : std_logic;
signal conv_addr: std_logic_vector(LOG2_N_COLS+LOG2_N_ROWS-1 downto 0);
signal conv_data: std_logic_vector(6 downto 0);
signal start_conv: std_logic;
signal done_conv: std_logic;
begin
m_axis_tready<='1';
clk <= not clk after 5 ns;
process (clk)
begin
if(rising_edge(clk)) then
conv_data<=mem(to_integer(unsigned(conv_addr)));
end if;
end process;
img_conv_inst: img_conv
generic map(
LOG2_N_COLS => LOG2_N_COLS,
LOG2_N_ROWS => LOG2_N_ROWS
)
port map(
clk => clk,
aresetn => aresetn,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tlast => m_axis_tlast,
conv_addr => conv_addr,
conv_data => conv_data,
start_conv => start_conv,
done_conv => done_conv
);
process
begin
wait for 10 ns;
aresetn<='1';
wait until rising_edge(clk);
start_conv<='1';
wait until rising_edge(clk);
start_conv<='0';
wait;
end process;
end Behavioral;

27
LAB2/vivado/lab2/lab2.xpr
View File

@@ -77,13 +77,7 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/bram_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/bram_writer.vhd">
<File Path="$PPRDIR/../../src/packetizer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -107,7 +101,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/packetizer.vhd">
<File Path="$PPRDIR/../../src/bram_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/bram_writer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -157,13 +157,16 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/img_conv_tb.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="bram_writer"/>
<Option Name="TopModule" Val="img_conv_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopArchitecture" Val="rtl"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../../src/bram_writer.vhd"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>

88
LAB2/vivado/pak_depak/pak_depak.xpr → LAB2/vivado/loopback/loopback.xpr
View File

@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/pak_depak/pak_depak.xpr">
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/loopback/loopback.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="66e226cf10b24331bf3e60250910330e"/>
@@ -55,13 +55,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="4"/>
<Option Name="WTModelSimExportSim" Val="4"/>
<Option Name="WTQuestaExportSim" Val="4"/>
<Option Name="WTIesExportSim" Val="4"/>
<Option Name="WTVcsExportSim" Val="4"/>
<Option Name="WTRivieraExportSim" Val="4"/>
<Option Name="WTActivehdlExportSim" Val="4"/>
<Option Name="WTXSimExportSim" Val="5"/>
<Option Name="WTModelSimExportSim" Val="5"/>
<Option Name="WTQuestaExportSim" Val="5"/>
<Option Name="WTIesExportSim" Val="5"/>
<Option Name="WTVcsExportSim" Val="5"/>
<Option Name="WTRivieraExportSim" Val="5"/>
<Option Name="WTActivehdlExportSim" Val="5"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -89,29 +89,29 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../design/pak_depak/pak_depak.bd">
<File Path="$PPRDIR/../../design/loopback/loopback.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_clk_wiz_0_0/pak_depak_clk_wiz_0_0.xci">
<Proxy FileSetName="pak_depak_clk_wiz_0_0"/>
<CompFileExtendedInfo CompFileName="loopback.bd" FileRelPathName="ip/loopback_proc_sys_reset_0_0/loopback_proc_sys_reset_0_0.xci">
<Proxy FileSetName="loopback_proc_sys_reset_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_AXI4Stream_UART_0_0/pak_depak_AXI4Stream_UART_0_0.xci">
<Proxy FileSetName="pak_depak_AXI4Stream_UART_0_0"/>
<CompFileExtendedInfo CompFileName="loopback.bd" FileRelPathName="ip/loopback_clk_wiz_0_0/loopback_clk_wiz_0_0.xci">
<Proxy FileSetName="loopback_clk_wiz_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_proc_sys_reset_0_0/pak_depak_proc_sys_reset_0_0.xci">
<Proxy FileSetName="pak_depak_proc_sys_reset_0_0"/>
<CompFileExtendedInfo CompFileName="loopback.bd" FileRelPathName="ip/loopback_AXI4Stream_UART_0_0/loopback_AXI4Stream_UART_0_0.xci">
<Proxy FileSetName="loopback_AXI4Stream_UART_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_depacketizer_0_0/pak_depak_depacketizer_0_0.xci">
<Proxy FileSetName="pak_depak_depacketizer_0_0"/>
<CompFileExtendedInfo CompFileName="loopback.bd" FileRelPathName="ip/loopback_packetizer_0_0/loopback_packetizer_0_0.xci">
<Proxy FileSetName="loopback_packetizer_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_packetizer_0_0/pak_depak_packetizer_0_0.xci">
<Proxy FileSetName="pak_depak_packetizer_0_0"/>
<CompFileExtendedInfo CompFileName="loopback.bd" FileRelPathName="ip/loopback_depacketizer_0_0/loopback_depacketizer_0_0.xci">
<Proxy FileSetName="loopback_depacketizer_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PPRDIR/../../design/pak_depak/hdl/pak_depak_wrapper.vhd">
<File Path="$PPRDIR/../../design/loopback/hdl/loopback_wrapper.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -119,7 +119,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="pak_depak_wrapper"/>
<Option Name="TopModule" Val="loopback_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
@@ -133,7 +133,7 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="pak_depak_wrapper"/>
<Option Name="TopModule" Val="loopback_wrapper"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
@@ -152,33 +152,33 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="pak_depak_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_proc_sys_reset_0_0" RelGenDir="$PGENDIR/pak_depak_proc_sys_reset_0_0">
<FileSet Name="loopback_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/loopback_proc_sys_reset_0_0" RelGenDir="$PGENDIR/loopback_proc_sys_reset_0_0">
<Config>
<Option Name="TopModule" Val="pak_depak_proc_sys_reset_0_0"/>
<Option Name="TopModule" Val="loopback_proc_sys_reset_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pak_depak_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_clk_wiz_0_0" RelGenDir="$PGENDIR/pak_depak_clk_wiz_0_0">
<FileSet Name="loopback_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/loopback_clk_wiz_0_0" RelGenDir="$PGENDIR/loopback_clk_wiz_0_0">
<Config>
<Option Name="TopModule" Val="pak_depak_clk_wiz_0_0"/>
<Option Name="TopModule" Val="loopback_clk_wiz_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pak_depak_AXI4Stream_UART_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_AXI4Stream_UART_0_0" RelGenDir="$PGENDIR/pak_depak_AXI4Stream_UART_0_0">
<FileSet Name="loopback_AXI4Stream_UART_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/loopback_AXI4Stream_UART_0_0" RelGenDir="$PGENDIR/loopback_AXI4Stream_UART_0_0">
<Config>
<Option Name="TopModule" Val="pak_depak_AXI4Stream_UART_0_0"/>
<Option Name="TopModule" Val="loopback_AXI4Stream_UART_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pak_depak_depacketizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_depacketizer_0_0" RelGenDir="$PGENDIR/pak_depak_depacketizer_0_0">
<FileSet Name="loopback_packetizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/loopback_packetizer_0_0" RelGenDir="$PGENDIR/loopback_packetizer_0_0">
<Config>
<Option Name="TopModule" Val="pak_depak_depacketizer_0_0"/>
<Option Name="TopModule" Val="loopback_packetizer_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pak_depak_packetizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_packetizer_0_0" RelGenDir="$PGENDIR/pak_depak_packetizer_0_0">
<FileSet Name="loopback_depacketizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/loopback_depacketizer_0_0" RelGenDir="$PGENDIR/loopback_depacketizer_0_0">
<Config>
<Option Name="TopModule" Val="pak_depak_packetizer_0_0"/>
<Option Name="TopModule" Val="loopback_depacketizer_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
@@ -202,7 +202,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../pak_depak/pak_depak.srcs/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
@@ -212,7 +212,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_proc_sys_reset_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_proc_sys_reset_0_0_synth_1">
<Run Id="loopback_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="loopback_proc_sys_reset_0_0" Part="xc7a35tcpg236-1" ConstrsSet="loopback_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/loopback_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_proc_sys_reset_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -224,7 +224,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_clk_wiz_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_clk_wiz_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_clk_wiz_0_0_synth_1">
<Run Id="loopback_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="loopback_clk_wiz_0_0" Part="xc7a35tcpg236-1" ConstrsSet="loopback_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/loopback_clk_wiz_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_clk_wiz_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -236,7 +236,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_AXI4Stream_UART_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_AXI4Stream_UART_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_AXI4Stream_UART_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_AXI4Stream_UART_0_0_synth_1">
<Run Id="loopback_AXI4Stream_UART_0_0_synth_1" Type="Ft3:Synth" SrcSet="loopback_AXI4Stream_UART_0_0" Part="xc7a35tcpg236-1" ConstrsSet="loopback_AXI4Stream_UART_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/loopback_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_AXI4Stream_UART_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -248,7 +248,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_depacketizer_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_depacketizer_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_depacketizer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_depacketizer_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_depacketizer_0_0_synth_1">
<Run Id="loopback_packetizer_0_0_synth_1" Type="Ft3:Synth" SrcSet="loopback_packetizer_0_0" Part="xc7a35tcpg236-1" ConstrsSet="loopback_packetizer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/loopback_packetizer_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_packetizer_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -260,7 +260,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_packetizer_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_packetizer_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_packetizer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_packetizer_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_packetizer_0_0_synth_1">
<Run Id="loopback_depacketizer_0_0_synth_1" Type="Ft3:Synth" SrcSet="loopback_depacketizer_0_0" Part="xc7a35tcpg236-1" ConstrsSet="loopback_depacketizer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/loopback_depacketizer_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_depacketizer_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -272,7 +272,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../pak_depak/pak_depak.srcs/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
@@ -290,7 +290,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_proc_sys_reset_0_0_impl_1">
<Run Id="loopback_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="loopback_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="loopback_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_proc_sys_reset_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
@@ -309,7 +309,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_clk_wiz_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_clk_wiz_0_0_impl_1">
<Run Id="loopback_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="loopback_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="loopback_clk_wiz_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_clk_wiz_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
@@ -328,7 +328,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_AXI4Stream_UART_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_AXI4Stream_UART_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_AXI4Stream_UART_0_0_impl_1">
<Run Id="loopback_AXI4Stream_UART_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="loopback_AXI4Stream_UART_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="loopback_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_AXI4Stream_UART_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
@@ -347,7 +347,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_depacketizer_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_depacketizer_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_depacketizer_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_depacketizer_0_0_impl_1">
<Run Id="loopback_packetizer_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="loopback_packetizer_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="loopback_packetizer_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_packetizer_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
@@ -366,7 +366,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pak_depak_packetizer_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_packetizer_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_packetizer_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_packetizer_0_0_impl_1">
<Run Id="loopback_depacketizer_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="loopback_depacketizer_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="loopback_depacketizer_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/loopback_depacketizer_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>