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Add loopback design files and update project configurations

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- Created a new loopback design file (loopback.bda) with nodes and edges defined in GraphML format.
- Added a new Vivado project file for loopback (loopback.xpr) with updated configurations.
- Introduced a new testbench for image convolution (img_conv_tb.vhd) in the simulation sources.
- Updated the main project file (lab2.xpr) to reflect changes in source files and top module for simulation.
- Removed obsolete project files (pak_depak.xpr.zip) and updated paths for existing source files.
This commit is contained in:
Davide Cavagnola
2025-04-25 11:16:54 +02:00
parent 835b4d0ab8
commit 14a6be00d6
13 changed files with 237 additions and 107 deletions
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2
LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
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@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri Apr 25 00:08:55 2025
--Date : Fri Apr 25 10:55:47 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target lab_2_wrapper.bd
--Design : lab_2_wrapper

28
LAB2/design/lab_2/lab_2.bd
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@@ -1169,20 +1169,6 @@
}
},
"interface_nets": {
"Conn": {
"interface_ports": [
"rgb2gray_0/s_axis",
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
]
},
"rgb2gray_0_m_axis": {
"interface_ports": [
"rgb2gray_0/m_axis",
"bram_writer_0/s_axis",
"system_ila_0/SLOT_2_AXIS"
]
},
"img_conv_0_m_axis": {
"interface_ports": [
"img_conv_0/m_axis",
@@ -1207,6 +1193,20 @@
"packetizer_0/m_axis",
"AXI4Stream_UART_0/S00_AXIS_TX"
]
},
"Conn": {
"interface_ports": [
"rgb2gray_0/s_axis",
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
]
},
"rgb2gray_0_m_axis": {
"interface_ports": [
"rgb2gray_0/m_axis",
"bram_writer_0/s_axis",
"system_ila_0/SLOT_2_AXIS"
]
}
},
"nets": {

12
LAB2/design/lab_2/lab_2.bda
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@@ -26,17 +26,17 @@
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n0">
<node id="n2">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0">
</edge>
<edge id="e1" source="n0" target="n2">
<edge id="e1" source="n0" target="n1">
</edge>
</graph>
</graphml>

18
LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd → LAB2/design/loopback/hdl/loopback_wrapper.vhd
View File

@@ -1,36 +1,36 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Thu Apr 24 19:38:15 2025
--Date : Fri Apr 25 10:52:31 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target pak_depak_wrapper.bd
--Design : pak_depak_wrapper
--Command : generate_target loopback_wrapper.bd
--Design : loopback_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pak_depak_wrapper is
entity loopback_wrapper is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end pak_depak_wrapper;
end loopback_wrapper;
architecture STRUCTURE of pak_depak_wrapper is
component pak_depak is
architecture STRUCTURE of loopback_wrapper is
component loopback is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC
);
end component pak_depak;
end component loopback;
begin
pak_depak_i: component pak_depak
loopback_i: component loopback
port map (
reset => reset,
sys_clock => sys_clock,

36
LAB2/design/pak_depak/pak_depak.bd → LAB2/design/loopback/loopback.bd
View File

@@ -3,7 +3,7 @@
"design_info": {
"boundary_crc": "0x9157799052A71E23",
"device": "xc7a35tcpg236-1",
"name": "pak_depak",
"name": "loopback",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2020.2",
@@ -41,7 +41,7 @@
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "pak_depak_sys_clock",
"value": "loopback_sys_clock",
"value_src": "default"
},
"FREQ_HZ": {
@@ -64,8 +64,8 @@
"components": {
"proc_sys_reset_0": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "pak_depak_proc_sys_reset_0_0",
"xci_path": "ip\\pak_depak_proc_sys_reset_0_0\\pak_depak_proc_sys_reset_0_0.xci",
"xci_name": "loopback_proc_sys_reset_0_0",
"xci_path": "ip\\loopback_proc_sys_reset_0_0\\loopback_proc_sys_reset_0_0.xci",
"inst_hier_path": "proc_sys_reset_0",
"parameters": {
"RESET_BOARD_INTERFACE": {
@@ -78,8 +78,8 @@
},
"clk_wiz_0": {
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
"xci_name": "pak_depak_clk_wiz_0_0",
"xci_path": "ip\\pak_depak_clk_wiz_0_0\\pak_depak_clk_wiz_0_0.xci",
"xci_name": "loopback_clk_wiz_0_0",
"xci_path": "ip\\loopback_clk_wiz_0_0\\loopback_clk_wiz_0_0.xci",
"inst_hier_path": "clk_wiz_0",
"parameters": {
"CLK_IN1_BOARD_INTERFACE": {
@@ -95,8 +95,8 @@
},
"AXI4Stream_UART_0": {
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
"xci_name": "pak_depak_AXI4Stream_UART_0_0",
"xci_path": "ip\\pak_depak_AXI4Stream_UART_0_0\\pak_depak_AXI4Stream_UART_0_0.xci",
"xci_name": "loopback_AXI4Stream_UART_0_0",
"xci_path": "ip\\loopback_AXI4Stream_UART_0_0\\loopback_AXI4Stream_UART_0_0.xci",
"inst_hier_path": "AXI4Stream_UART_0",
"parameters": {
"UART_BOARD_INTERFACE": {
@@ -109,8 +109,8 @@
},
"packetizer_0": {
"vlnv": "xilinx.com:module_ref:packetizer:1.0",
"xci_name": "pak_depak_packetizer_0_0",
"xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci",
"xci_name": "loopback_packetizer_0_0",
"xci_path": "ip\\loopback_packetizer_0_0\\loopback_packetizer_0_0.xci",
"inst_hier_path": "packetizer_0",
"reference_info": {
"ref_type": "hdl",
@@ -296,8 +296,8 @@
},
"depacketizer_0": {
"vlnv": "xilinx.com:module_ref:depacketizer:1.0",
"xci_name": "pak_depak_depacketizer_0_0",
"xci_path": "ip\\pak_depak_depacketizer_0_0\\pak_depak_depacketizer_0_0.xci",
"xci_name": "loopback_depacketizer_0_0",
"xci_path": "ip\\loopback_depacketizer_0_0\\loopback_depacketizer_0_0.xci",
"inst_hier_path": "depacketizer_0",
"reference_info": {
"ref_type": "hdl",
@@ -489,12 +489,6 @@
"depacketizer_0/s_axis"
]
},
"depacketizer_0_m_axis": {
"interface_ports": [
"depacketizer_0/m_axis",
"packetizer_0/s_axis"
]
},
"packetizer_0_m_axis": {
"interface_ports": [
"packetizer_0/m_axis",
@@ -506,6 +500,12 @@
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
"depacketizer_0_m_axis": {
"interface_ports": [
"depacketizer_0/m_axis",
"packetizer_0/s_axis"
]
}
},
"nets": {

4
LAB2/design/pak_depak/pak_depak.bda → LAB2/design/loopback/loopback.bda
View File

@@ -22,11 +22,11 @@
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">pak_depak</data>
<data key="VM">loopback</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">pak_depak</data>
<data key="VM">loopback</data>
<data key="VT">BC</data>
</node>
<node id="n2">