Add loopback design files and update project configurations

- Created a new loopback design file (loopback.bda) with nodes and edges defined in GraphML format.
- Added a new Vivado project file for loopback (loopback.xpr) with updated configurations.
- Introduced a new testbench for image convolution (img_conv_tb.vhd) in the simulation sources.
- Updated the main project file (lab2.xpr) to reflect changes in source files and top module for simulation.
- Removed obsolete project files (pak_depak.xpr.zip) and updated paths for existing source files.

LAB2/design/loopback/hdl/loopback_wrapper.vhd

@@ -0,0 +1,40 @@
+--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+--Date        : Fri Apr 25 10:52:31 2025
+--Host        : DavideASUS running 64-bit major release  (build 9200)
+--Command     : generate_target loopback_wrapper.bd
+--Design      : loopback_wrapper
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity loopback_wrapper is
+  port (
+    reset : in STD_LOGIC;
+    sys_clock : in STD_LOGIC;
+    usb_uart_rxd : in STD_LOGIC;
+    usb_uart_txd : out STD_LOGIC
+  );
+end loopback_wrapper;
+
+architecture STRUCTURE of loopback_wrapper is
+  component loopback is
+  port (
+    reset : in STD_LOGIC;
+    sys_clock : in STD_LOGIC;
+    usb_uart_txd : out STD_LOGIC;
+    usb_uart_rxd : in STD_LOGIC
+  );
+  end component loopback;
+begin
+loopback_i: component loopback
+     port map (
+      reset => reset,
+      sys_clock => sys_clock,
+      usb_uart_rxd => usb_uart_rxd,
+      usb_uart_txd => usb_uart_txd
+    );
+end STRUCTURE;