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Add loopback design files and update project configurations

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- Created a new loopback design file (loopback.bda) with nodes and edges defined in GraphML format.
- Added a new Vivado project file for loopback (loopback.xpr) with updated configurations.
- Introduced a new testbench for image convolution (img_conv_tb.vhd) in the simulation sources.
- Updated the main project file (lab2.xpr) to reflect changes in source files and top module for simulation.
- Removed obsolete project files (pak_depak.xpr.zip) and updated paths for existing source files.
This commit is contained in:
Davide Cavagnola
2025-04-25 11:16:54 +02:00
parent 835b4d0ab8
commit 14a6be00d6
13 changed files with 237 additions and 107 deletions
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27
LAB2/vivado/lab2/lab2.xpr
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@@ -77,13 +77,7 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/bram_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/bram_writer.vhd">
<File Path="$PPRDIR/../../src/packetizer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -107,7 +101,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/packetizer.vhd">
<File Path="$PPRDIR/../../src/bram_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/bram_writer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -157,13 +157,16 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/img_conv_tb.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="bram_writer"/>
<Option Name="TopModule" Val="img_conv_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopArchitecture" Val="rtl"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../../src/bram_writer.vhd"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>