diff --git a/.gitignore b/.gitignore index cc912b4..4043e16 100644 --- a/.gitignore +++ b/.gitignore @@ -50,6 +50,7 @@ *.sim/ *.cache/ *.hw/ +*.srcs/ .hwdbg/ *.ip_user_files/ .webtalk/ diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd deleted file mode 100644 index d2bff85..0000000 --- a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd +++ /dev/null @@ -1,56 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 03.03.2025 14:21:16 --- Design Name: --- Module Name: shift_register_v0 - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity shift_register_v0 is - Port ( reset : in STD_LOGIC; - clk : in STD_LOGIC; - din : in STD_LOGIC; - dout : out STD_LOGIC); -end shift_register_v0; - -architecture Behavioral of shift_register_v0 is - signal sr : std_logic := '0'; -begin - - process(clk, reset) - begin - if reset = '1' then - sr <= '0'; - elsif rising_edge(clk) then - sr <= din; - end if; - end process; - - dout <= sr; - -end Behavioral; diff --git a/LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd b/LAB0/sim/tb_PulseWidthModulator.vhd similarity index 100% rename from LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd rename to LAB0/sim/tb_PulseWidthModulator.vhd diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd b/LAB0/sim/tb_ShiftRegister_v0.vhd similarity index 100% rename from LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd rename to LAB0/sim/tb_ShiftRegister_v0.vhd diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd b/LAB0/sim/tb_ShiftRegister_v1.vhd similarity index 100% rename from LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd rename to LAB0/sim/tb_ShiftRegister_v1.vhd diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd b/LAB0/sim/tb_ShiftRegister_v2.vhd similarity index 100% rename from LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd rename to LAB0/sim/tb_ShiftRegister_v2.vhd diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd b/LAB0/src/PulseWidthModulator.vhd similarity index 100% rename from LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd rename to LAB0/src/PulseWidthModulator.vhd diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd b/LAB0/src/ShiftRegister_v0.vhd similarity index 100% rename from LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd rename to LAB0/src/ShiftRegister_v0.vhd diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd b/LAB0/src/ShiftRegister_v1.vhd similarity index 100% rename from LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd rename to LAB0/src/ShiftRegister_v1.vhd diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd b/LAB0/src/ShiftRegister_v2.vhd similarity index 100% rename from LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd rename to LAB0/src/ShiftRegister_v2.vhd diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr b/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr similarity index 93% rename from LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr rename to LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr index 40caca1..d4eb671 100644 --- a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr +++ b/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr @@ -3,7 +3,7 @@ - +