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Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.

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This commit is contained in:
Davide Cavagnola
2025-05-19 16:24:36 +02:00
parent 5f30651763
commit 1b6bae5183
16 changed files with 965 additions and 618 deletions
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38
LAB3/design/diligent_jstk/diligent_jstk.bd
View File

@@ -71,7 +71,7 @@
"proc_sys_reset_0": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "diligent_jstk_proc_sys_reset_0_0",
"xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0_1\\diligent_jstk_proc_sys_reset_0_0.xci",
"xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0\\diligent_jstk_proc_sys_reset_0_0.xci",
"inst_hier_path": "proc_sys_reset_0",
"parameters": {
"RESET_BOARD_INTERFACE": {
@@ -85,7 +85,7 @@
"clk_wiz_0": {
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
"xci_name": "diligent_jstk_clk_wiz_0_0",
"xci_path": "ip\\diligent_jstk_clk_wiz_0_0_1\\diligent_jstk_clk_wiz_0_0.xci",
"xci_path": "ip\\diligent_jstk_clk_wiz_0_0\\diligent_jstk_clk_wiz_0_0.xci",
"inst_hier_path": "clk_wiz_0",
"parameters": {
"CLK_IN1_BOARD_INTERFACE": {
@@ -99,7 +99,7 @@
"AXI4Stream_UART_0": {
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
"xci_name": "diligent_jstk_AXI4Stream_UART_0_0",
"xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0_1\\diligent_jstk_AXI4Stream_UART_0_0.xci",
"xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0\\diligent_jstk_AXI4Stream_UART_0_0.xci",
"inst_hier_path": "AXI4Stream_UART_0",
"parameters": {
"UART_BAUD_RATE": {
@@ -116,7 +116,7 @@
"jstk_uart_bridge_0": {
"vlnv": "xilinx.com:module_ref:jstk_uart_bridge:1.0",
"xci_name": "diligent_jstk_jstk_uart_bridge_0_0",
"xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0_1\\diligent_jstk_jstk_uart_bridge_0_0.xci",
"xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0\\diligent_jstk_jstk_uart_bridge_0_0.xci",
"inst_hier_path": "jstk_uart_bridge_0",
"reference_info": {
"ref_type": "hdl",
@@ -330,7 +330,7 @@
"axi4stream_spi_master_0": {
"vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0",
"xci_name": "diligent_jstk_axi4stream_spi_master_0_0",
"xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0_1\\diligent_jstk_axi4stream_spi_master_0_0.xci",
"xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0\\diligent_jstk_axi4stream_spi_master_0_0.xci",
"inst_hier_path": "axi4stream_spi_master_0",
"parameters": {
"c_sclkfreq": {
@@ -341,7 +341,7 @@
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"xci_name": "diligent_jstk_system_ila_0_0",
"xci_path": "ip\\diligent_jstk_system_ila_0_0_1\\diligent_jstk_system_ila_0_0.xci",
"xci_path": "ip\\diligent_jstk_system_ila_0_0\\diligent_jstk_system_ila_0_0.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_MON_TYPE": {
@@ -377,7 +377,7 @@
"digilent_jstk2_0": {
"vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
"xci_name": "diligent_jstk_digilent_jstk2_0_0",
"xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0_1\\diligent_jstk_digilent_jstk2_0_0.xci",
"xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0\\diligent_jstk_digilent_jstk2_0_0.xci",
"inst_hier_path": "digilent_jstk2_0",
"parameters": {
"SPI_SCLKFREQ": {
@@ -591,12 +591,6 @@
}
},
"interface_nets": {
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
@@ -610,10 +604,16 @@
"jstk_uart_bridge_0/s_axis"
]
},
"jstk_uart_bridge_0_m_axis": {
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
"digilent_jstk2_0_m_axis": {
@@ -623,10 +623,10 @@
"system_ila_0/SLOT_0_AXIS"
]
},
"axi4stream_spi_master_0_SPI_M": {
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
}
},

10
LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
View File

@@ -1,8 +1,8 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Sun May 18 23:39:32 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Date : Mon May 19 09:11:39 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper
--Purpose : IP block netlist
@@ -29,6 +29,8 @@ architecture STRUCTURE of diligent_jstk_wrapper is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
SPI_M_0_sck_t : out STD_LOGIC;
SPI_M_0_io1_o : out STD_LOGIC;
SPI_M_0_ss_t : out STD_LOGIC;
@@ -40,9 +42,7 @@ architecture STRUCTURE of diligent_jstk_wrapper is
SPI_M_0_sck_o : out STD_LOGIC;
SPI_M_0_ss_i : in STD_LOGIC;
SPI_M_0_io1_i : in STD_LOGIC;
SPI_M_0_io0_i : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC
SPI_M_0_io0_i : in STD_LOGIC
);
end component diligent_jstk;
component IOBUF is