Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.
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@@ -1,34 +1,55 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity effect_selector is
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generic(
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JOYSTICK_LENGHT : integer := 10
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ENTITY effect_selector IS
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GENERIC (
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JOYSTICK_LENGHT : INTEGER := 10
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);
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Port (
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aclk : in STD_LOGIC;
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aresetn : in STD_LOGIC;
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effect : in STD_LOGIC;
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jstck_x : in STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0);
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jstck_y : in STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0);
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volume : out STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0);
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balance : out STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0);
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lfo_period : out STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0)
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PORT (
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aclk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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effect : IN STD_LOGIC;
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jstck_x : IN STD_LOGIC_VECTOR(JOYSTICK_LENGHT - 1 DOWNTO 0);
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jstck_y : IN STD_LOGIC_VECTOR(JOYSTICK_LENGHT - 1 DOWNTO 0);
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volume : OUT STD_LOGIC_VECTOR(JOYSTICK_LENGHT - 1 DOWNTO 0);
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balance : OUT STD_LOGIC_VECTOR(JOYSTICK_LENGHT - 1 DOWNTO 0);
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lfo_period : OUT STD_LOGIC_VECTOR(JOYSTICK_LENGHT - 1 DOWNTO 0)
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);
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end effect_selector;
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END effect_selector;
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architecture Behavioral of effect_selector is
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ARCHITECTURE Behavioral OF effect_selector IS
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begin
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BEGIN
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end Behavioral;
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PROCESS (aclk)
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BEGIN
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IF rising_edge(aclk) THEN
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IF aresetn = '0' THEN
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volume <= (OTHERS => '0');
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balance <= (OTHERS => '0');
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lfo_period <= (OTHERS => '0');
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ELSE
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balance <= jstck_x;
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IF effect = '0' THEN
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-- volume/balance control
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volume <= jstck_y;
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lfo_period <= (OTHERS => '0');
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ELSE
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-- LFO control
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lfo_period <= jstck_y;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END Behavioral;
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