Add testbench for balance_controller and update Vivado project files
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@@ -6,7 +6,7 @@ ENTITY balance_controller IS
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GENERIC (
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TDATA_WIDTH : POSITIVE := 24;
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BALANCE_WIDTH : POSITIVE := 10;
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BALANCE_STEP_2 : POSITIVE := 6 -- i.e., balance_values_per_step = 2**VOLUME_STEP_2
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BALANCE_STEP_2 : POSITIVE := 6 -- i.e., balance_values_per_step = 2**BALANCE_STEP_2
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);
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PORT (
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aclk : IN STD_LOGIC;
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@@ -27,128 +27,92 @@ ENTITY balance_controller IS
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END balance_controller;
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ARCHITECTURE Behavioral OF balance_controller IS
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CONSTANT CENTER_VALUE : INTEGER := 2 ** (BALANCE_WIDTH - 1) - 1; -- 511 per BALANCE_WIDTH=10
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CONSTANT DEADZONE : INTEGER := 32; -- Deadzone da -32 a +32
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CONSTANT MAX_SHIFT : INTEGER := TDATA_WIDTH - 1; -- Massimo shift possibile
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SIGNAL balance_signed : signed(BALANCE_WIDTH - 1 DOWNTO 0);
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SIGNAL shift_amount_left, shift_amount_right : NATURAL RANGE 0 TO MAX_SHIFT;
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CONSTANT BALANCE_STEPS : INTEGER := (2 ** (BALANCE_WIDTH - 1)) / (2 ** BALANCE_STEP_2) + 1;
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CONSTANT BAL_MID : INTEGER := 2 ** (BALANCE_WIDTH - 1); -- 512 for 10 bit
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CONSTANT BLOCK_SIZE : INTEGER := 2 ** BALANCE_STEP_2;
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CONSTANT DEAD_ZONE : INTEGER := BLOCK_SIZE / 2;
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-- Registri di pipeline
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SIGNAL audio_in_reg : signed(TDATA_WIDTH - 1 DOWNTO 0);
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SIGNAL tlast_reg : STD_LOGIC;
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SIGNAL valid_reg : STD_LOGIC;
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SIGNAL left_channel : INTEGER RANGE 0 TO BALANCE_STEPS := 0;
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SIGNAL right_channel : INTEGER RANGE 0 TO BALANCE_STEPS := 0;
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-- Segnali di controllo
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SIGNAL ready_int : STD_LOGIC;
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SIGNAL processing_active : STD_LOGIC;
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SIGNAL m_axis_tvalid_int : STD_LOGIC;
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BEGIN
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-- Convert balance input to signed (-512 to +511)
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balance_signed <= signed(balance);
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-- Assigning the output signals
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m_axis_tvalid <= m_axis_tvalid_int;
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s_axis_tready <= m_axis_tready AND aresetn;
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-- Calcolo dello shift amount con deadzone e scaling esponenziale
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PROCESS (balance_signed)
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VARIABLE centered_value : signed(BALANCE_WIDTH - 1 DOWNTO 0);
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VARIABLE abs_value : unsigned(BALANCE_WIDTH - 2 DOWNTO 0);
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VARIABLE exp_shift : INTEGER;
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BEGIN
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-- Centra il valore intorno a 0 (da -512 a +511 -> da -511 a +511)
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centered_value := balance_signed - to_signed(CENTER_VALUE, BALANCE_WIDTH);
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-- Inizializzazione
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shift_amount_left <= 0;
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shift_amount_right <= 0;
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-- Calcola il valore assoluto
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IF centered_value(BALANCE_WIDTH - 1) = '1' THEN -- negativo
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abs_value := unsigned(-centered_value(BALANCE_WIDTH - 2 DOWNTO 0));
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ELSE
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abs_value := unsigned(centered_value(BALANCE_WIDTH - 2 DOWNTO 0));
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END IF;
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-- Applica deadzone e calcola shift
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IF centered_value > DEADZONE THEN
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-- Calcola lo shift per il canale sinistro (valori positivi)
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exp_shift := (to_integer(abs_value) - DEADZONE) / 2 ** BALANCE_STEP_2 + 1;
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IF exp_shift > MAX_SHIFT THEN
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shift_amount_left <= MAX_SHIFT;
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ELSE
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shift_amount_left <= exp_shift;
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END IF;
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ELSIF centered_value <- DEADZONE THEN
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-- Calcola lo shift per il canale destro (valori negativi)
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exp_shift := (to_integer(abs_value) - DEADZONE) / 2 ** BALANCE_STEP_2 + 1;
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IF exp_shift > MAX_SHIFT THEN
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shift_amount_right <= MAX_SHIFT;
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ELSE
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shift_amount_right <= exp_shift;
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END IF;
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END IF;
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END PROCESS;
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-- Il resto del codice rimane IDENTICO alla versione originale
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-- Logica di controllo AXI
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-- Balance to exp
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PROCESS (aclk)
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VARIABLE temp : signed(TDATA_WIDTH + MAX_SHIFT - 1 DOWNTO 0);
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BEGIN
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IF rising_edge(aclk) THEN
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IF aresetn = '0' THEN
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-- Reset asincrono
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valid_reg <= '0';
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audio_in_reg <= (OTHERS => '0');
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tlast_reg <= '0';
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processing_active <= '0';
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left_channel <= 0;
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right_channel <= 0;
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ELSE
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-- Gestione del flusso dati
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IF ready_int = '1' THEN
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valid_reg <= '0';
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IF s_axis_tvalid = '1' THEN
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-- Registrazione degli ingressi
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audio_in_reg <= signed(s_axis_tdata);
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tlast_reg <= s_axis_tlast;
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valid_reg <= '1';
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processing_active <= '1';
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ELSE
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processing_active <= '0';
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END IF;
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-- Balance left and right channels
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IF unsigned(balance) > (BAL_MID + DEAD_ZONE) THEN
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left_channel <= to_integer((unsigned(balance) - (BAL_MID + DEAD_ZONE)) SRL BALANCE_STEP_2) + 1;
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ELSE
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left_channel <= 0;
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END IF;
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-- Elaborazione del dato (sempre attiva)
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IF processing_active = '1' OR valid_reg = '1' THEN
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temp := resize(audio_in_reg, temp'length);
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IF tlast_reg = '0' THEN
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temp := shift_right(temp, shift_amount_left);
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ELSE
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temp := shift_right(temp, shift_amount_right);
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END IF;
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-- Saturazione
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IF temp > 2 ** (TDATA_WIDTH - 1) - 1 THEN
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m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(2 ** (TDATA_WIDTH - 1) - 1, TDATA_WIDTH));
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ELSIF temp <- 2 ** (TDATA_WIDTH - 1) THEN
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m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(-2 ** (TDATA_WIDTH - 1), TDATA_WIDTH));
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ELSE
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m_axis_tdata <= STD_LOGIC_VECTOR(temp(TDATA_WIDTH - 1 DOWNTO 0));
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END IF;
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m_axis_tlast <= tlast_reg;
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IF unsigned(balance) < (BAL_MID - DEAD_ZONE) THEN
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right_channel <= to_integer(((BAL_MID - DEAD_ZONE) - unsigned(balance)) SRL BALANCE_STEP_2) + 1;
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ELSE
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right_channel <= 0;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-- Logica combinazionale per tready
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ready_int <= m_axis_tready OR NOT valid_reg;
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s_axis_tready <= ready_int;
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-- Handle AXIS stream
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PROCESS (aclk)
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BEGIN
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-- Assegnazione del valid in uscita
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m_axis_tvalid <= valid_reg;
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IF rising_edge(aclk) THEN
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IF aresetn = '0' THEN
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m_axis_tvalid_int <= '0';
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m_axis_tlast <= '0';
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m_axis_tdata <= (OTHERS => '0');
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ELSE
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-- Default output signals
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m_axis_tlast <= '0';
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-- Clear valid flag when master interface is ready
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IF m_axis_tready = '1' THEN
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m_axis_tvalid_int <= '0';
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END IF;
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-- Handle the data flow
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IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
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-- Joystick datasheet: (x-axis) a 0 value corresponds to the axis
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-- being tilted fully to the left and a value of 1023
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-- corresponds fully to the right
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IF s_axis_tlast = '0' THEN -- left
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m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(signed(s_axis_tdata), left_channel));
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ELSE -- right
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m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(signed(s_axis_tdata), right_channel));
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END IF;
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m_axis_tvalid_int <= '1';
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m_axis_tlast <= s_axis_tlast;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END Behavioral;
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