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Add testbench for balance_controller and update Vivado project files

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This commit is contained in:
Davide Cavagnola
2025-05-22 11:22:57 +02:00
parent 13cf70b984
commit 1d779b7d3a
5 changed files with 552 additions and 105 deletions
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170
LAB3/sim/tb_balance_controller.vhd Normal file
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@@ -0,0 +1,170 @@
----------------------------------------------------------------------------------
-- Testbench for balance_controller
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY tb_balance_controller IS
END tb_balance_controller;
ARCHITECTURE Behavioral OF tb_balance_controller IS
CONSTANT TDATA_WIDTH : POSITIVE := 24;
CONSTANT BALANCE_WIDTH : POSITIVE := 10;
CONSTANT BALANCE_STEP_2 : POSITIVE := 6;
CONSTANT N_SAMPLES : INTEGER := 8;
CONSTANT N_BALANCES : INTEGER := 5;
COMPONENT balance_controller IS
GENERIC (
TDATA_WIDTH : POSITIVE := 24;
BALANCE_WIDTH : POSITIVE := 10;
BALANCE_STEP_2 : POSITIVE := 6
);
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0);
s_axis_tready : OUT STD_LOGIC;
s_axis_tlast : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0);
m_axis_tready : IN STD_LOGIC;
m_axis_tlast : OUT STD_LOGIC;
balance : IN STD_LOGIC_VECTOR(BALANCE_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
SIGNAL aclk : STD_LOGIC := '0';
SIGNAL aresetn : STD_LOGIC := '0';
SIGNAL s_axis_tvalid : STD_LOGIC := '0';
SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axis_tlast : STD_LOGIC := '0';
SIGNAL s_axis_tready : STD_LOGIC;
SIGNAL m_axis_tvalid : STD_LOGIC;
SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0);
SIGNAL m_axis_tlast : STD_LOGIC;
SIGNAL m_axis_tready : STD_LOGIC := '1';
SIGNAL balance : STD_LOGIC_VECTOR(BALANCE_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
-- Test input samples
TYPE sample_mem_type IS ARRAY(0 TO N_SAMPLES-1) OF STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0);
SIGNAL sample_mem : sample_mem_type := (
x"000100", -- +256
x"FFFE00", -- -512
x"000001", -- +1
x"FFFFFF", -- -1 (2's comp)
x"7FFFFF", -- max positive
x"800000", -- max negative
x"000A00", -- +2560
x"FFF600" -- -2560
);
-- Balance values: left, center, right, slightly left, slightly right
TYPE balance_mem_type IS ARRAY(0 TO N_BALANCES-1) OF STD_LOGIC_VECTOR(BALANCE_WIDTH-1 DOWNTO 0);
SIGNAL balance_mem : balance_mem_type := (
std_logic_vector(to_unsigned(0, BALANCE_WIDTH)), -- full left
std_logic_vector(to_unsigned(480, BALANCE_WIDTH)), -- center
std_logic_vector(to_unsigned(1023, BALANCE_WIDTH)), -- full right
std_logic_vector(to_unsigned(240, BALANCE_WIDTH)), -- slightly left
std_logic_vector(to_unsigned(800, BALANCE_WIDTH)) -- slightly right
);
BEGIN
-- Clock generation
aclk <= NOT aclk AFTER 5 ns;
-- DUT instantiation
uut: balance_controller
GENERIC MAP (
TDATA_WIDTH => TDATA_WIDTH,
BALANCE_WIDTH => BALANCE_WIDTH,
BALANCE_STEP_2 => BALANCE_STEP_2
)
PORT MAP (
aclk => aclk,
aresetn => aresetn,
s_axis_tvalid => s_axis_tvalid,
s_axis_tdata => s_axis_tdata,
s_axis_tready => s_axis_tready,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tdata => m_axis_tdata,
m_axis_tready => m_axis_tready,
m_axis_tlast => m_axis_tlast,
balance => balance
);
-- Stimulus process
stimulus : PROCESS
BEGIN
-- Reset
WAIT FOR 10 ns;
aresetn <= '1';
WAIT UNTIL rising_edge(aclk);
-- Set balance to center
balance <= balance_mem(1);
WAIT UNTIL rising_edge(aclk);
-- Send all samples (center)
FOR i IN 0 TO N_SAMPLES-1 LOOP
s_axis_tdata <= sample_mem(i);
s_axis_tvalid <= '1';
IF i = N_SAMPLES-1 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL rising_edge(aclk);
WHILE s_axis_tready = '0' LOOP
WAIT UNTIL rising_edge(aclk);
END LOOP;
END LOOP;
s_axis_tvalid <= '0';
s_axis_tlast <= '0';
-- Change balance to full left
WAIT FOR 20 ns;
balance <= balance_mem(0);
-- Send one more sample (left)
WAIT UNTIL rising_edge(aclk);
s_axis_tdata <= x"000100";
s_axis_tvalid <= '1';
s_axis_tlast <= '1';
WAIT UNTIL rising_edge(aclk);
WHILE s_axis_tready = '0' LOOP
WAIT UNTIL rising_edge(aclk);
END LOOP;
s_axis_tvalid <= '0';
s_axis_tlast <= '0';
-- Sweep through other balance values
FOR i IN 2 TO N_BALANCES-1 LOOP
WAIT FOR 20 ns;
balance <= balance_mem(i);
WAIT UNTIL rising_edge(aclk);
END LOOP;
-- Wait and finish
WAIT FOR 100 ns;
WAIT;
END PROCESS;
-- Optionally, block m_axis_tready to test backpressure
PROCESS
BEGIN
WAIT FOR 60 ns;
WAIT UNTIL rising_edge(aclk);
m_axis_tready <= '0';
WAIT FOR 20 ns;
WAIT UNTIL rising_edge(aclk);
m_axis_tready <= '1';
WAIT;
END PROCESS;
END Behavioral;

166
LAB3/src/balance_controller.vhd
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@@ -6,7 +6,7 @@ ENTITY balance_controller IS
GENERIC (
TDATA_WIDTH : POSITIVE := 24;
BALANCE_WIDTH : POSITIVE := 10;
BALANCE_STEP_2 : POSITIVE := 6 -- i.e., balance_values_per_step = 2**VOLUME_STEP_2
BALANCE_STEP_2 : POSITIVE := 6 -- i.e., balance_values_per_step = 2**BALANCE_STEP_2
);
PORT (
aclk : IN STD_LOGIC;
@@ -28,127 +28,91 @@ END balance_controller;
ARCHITECTURE Behavioral OF balance_controller IS
CONSTANT CENTER_VALUE : INTEGER := 2 ** (BALANCE_WIDTH - 1) - 1; -- 511 per BALANCE_WIDTH=10
CONSTANT DEADZONE : INTEGER := 32; -- Deadzone da -32 a +32
CONSTANT MAX_SHIFT : INTEGER := TDATA_WIDTH - 1; -- Massimo shift possibile
CONSTANT BALANCE_STEPS : INTEGER := (2 ** (BALANCE_WIDTH - 1)) / (2 ** BALANCE_STEP_2) + 1;
CONSTANT BAL_MID : INTEGER := 2 ** (BALANCE_WIDTH - 1); -- 512 for 10 bit
CONSTANT BLOCK_SIZE : INTEGER := 2 ** BALANCE_STEP_2;
CONSTANT DEAD_ZONE : INTEGER := BLOCK_SIZE / 2;
SIGNAL balance_signed : signed(BALANCE_WIDTH - 1 DOWNTO 0);
SIGNAL shift_amount_left, shift_amount_right : NATURAL RANGE 0 TO MAX_SHIFT;
SIGNAL left_channel : INTEGER RANGE 0 TO BALANCE_STEPS := 0;
SIGNAL right_channel : INTEGER RANGE 0 TO BALANCE_STEPS := 0;
-- Registri di pipeline
SIGNAL audio_in_reg : signed(TDATA_WIDTH - 1 DOWNTO 0);
SIGNAL tlast_reg : STD_LOGIC;
SIGNAL valid_reg : STD_LOGIC;
-- Segnali di controllo
SIGNAL ready_int : STD_LOGIC;
SIGNAL processing_active : STD_LOGIC;
SIGNAL m_axis_tvalid_int : STD_LOGIC;
BEGIN
-- Convert balance input to signed (-512 to +511)
balance_signed <= signed(balance);
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= m_axis_tready AND aresetn;
-- Calcolo dello shift amount con deadzone e scaling esponenziale
PROCESS (balance_signed)
VARIABLE centered_value : signed(BALANCE_WIDTH - 1 DOWNTO 0);
VARIABLE abs_value : unsigned(BALANCE_WIDTH - 2 DOWNTO 0);
VARIABLE exp_shift : INTEGER;
BEGIN
-- Centra il valore intorno a 0 (da -512 a +511 -> da -511 a +511)
centered_value := balance_signed - to_signed(CENTER_VALUE, BALANCE_WIDTH);
-- Inizializzazione
shift_amount_left <= 0;
shift_amount_right <= 0;
-- Calcola il valore assoluto
IF centered_value(BALANCE_WIDTH - 1) = '1' THEN -- negativo
abs_value := unsigned(-centered_value(BALANCE_WIDTH - 2 DOWNTO 0));
ELSE
abs_value := unsigned(centered_value(BALANCE_WIDTH - 2 DOWNTO 0));
END IF;
-- Applica deadzone e calcola shift
IF centered_value > DEADZONE THEN
-- Calcola lo shift per il canale sinistro (valori positivi)
exp_shift := (to_integer(abs_value) - DEADZONE) / 2 ** BALANCE_STEP_2 + 1;
IF exp_shift > MAX_SHIFT THEN
shift_amount_left <= MAX_SHIFT;
ELSE
shift_amount_left <= exp_shift;
END IF;
ELSIF centered_value <- DEADZONE THEN
-- Calcola lo shift per il canale destro (valori negativi)
exp_shift := (to_integer(abs_value) - DEADZONE) / 2 ** BALANCE_STEP_2 + 1;
IF exp_shift > MAX_SHIFT THEN
shift_amount_right <= MAX_SHIFT;
ELSE
shift_amount_right <= exp_shift;
END IF;
END IF;
END PROCESS;
-- Il resto del codice rimane IDENTICO alla versione originale
-- Logica di controllo AXI
-- Balance to exp
PROCESS (aclk)
VARIABLE temp : signed(TDATA_WIDTH + MAX_SHIFT - 1 DOWNTO 0);
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
-- Reset asincrono
valid_reg <= '0';
audio_in_reg <= (OTHERS => '0');
tlast_reg <= '0';
processing_active <= '0';
left_channel <= 0;
right_channel <= 0;
ELSE
-- Gestione del flusso dati
IF ready_int = '1' THEN
valid_reg <= '0';
IF s_axis_tvalid = '1' THEN
-- Registrazione degli ingressi
audio_in_reg <= signed(s_axis_tdata);
tlast_reg <= s_axis_tlast;
valid_reg <= '1';
processing_active <= '1';
-- Balance left and right channels
IF unsigned(balance) > (BAL_MID + DEAD_ZONE) THEN
left_channel <= to_integer((unsigned(balance) - (BAL_MID + DEAD_ZONE)) SRL BALANCE_STEP_2) + 1;
ELSE
processing_active <= '0';
END IF;
left_channel <= 0;
END IF;
-- Elaborazione del dato (sempre attiva)
IF processing_active = '1' OR valid_reg = '1' THEN
temp := resize(audio_in_reg, temp'length);
IF tlast_reg = '0' THEN
temp := shift_right(temp, shift_amount_left);
IF unsigned(balance) < (BAL_MID - DEAD_ZONE) THEN
right_channel <= to_integer(((BAL_MID - DEAD_ZONE) - unsigned(balance)) SRL BALANCE_STEP_2) + 1;
ELSE
temp := shift_right(temp, shift_amount_right);
right_channel <= 0;
END IF;
-- Saturazione
IF temp > 2 ** (TDATA_WIDTH - 1) - 1 THEN
m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(2 ** (TDATA_WIDTH - 1) - 1, TDATA_WIDTH));
ELSIF temp <- 2 ** (TDATA_WIDTH - 1) THEN
m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(-2 ** (TDATA_WIDTH - 1), TDATA_WIDTH));
ELSE
m_axis_tdata <= STD_LOGIC_VECTOR(temp(TDATA_WIDTH - 1 DOWNTO 0));
END IF;
m_axis_tlast <= tlast_reg;
END IF;
END IF;
END IF;
END PROCESS;
-- Logica combinazionale per tready
ready_int <= m_axis_tready OR NOT valid_reg;
s_axis_tready <= ready_int;
-- Handle AXIS stream
PROCESS (aclk)
BEGIN
-- Assegnazione del valid in uscita
m_axis_tvalid <= valid_reg;
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
m_axis_tdata <= (OTHERS => '0');
ELSE
-- Default output signals
m_axis_tlast <= '0';
-- Clear valid flag when master interface is ready
IF m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
END IF;
-- Handle the data flow
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
-- Joystick datasheet: (x-axis) a 0 value corresponds to the axis
-- being tilted fully to the left and a value of 1023
-- corresponds fully to the right
IF s_axis_tlast = '0' THEN -- left
m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(signed(s_axis_tdata), left_channel));
ELSE -- right
m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(signed(s_axis_tdata), right_channel));
END IF;
m_axis_tvalid_int <= '1';
m_axis_tlast <= s_axis_tlast;
END IF;
END IF;
END IF;
END PROCESS;
END Behavioral;

2
LAB3/src/volume_multiplier.vhd
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@@ -83,6 +83,8 @@ BEGIN
-- Handle the data flow
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
-- Multiply the input data with the volume and assign to output
-- Joystick datasheet: (y-axis) a value of 0 when it is tilted all the way down
-- and a value of 1023 when it is tilted all the way up
IF volume_exp_mult >= 0 THEN
m_axis_tdata <= STD_LOGIC_VECTOR(
shift_left(

214
LAB3/vivado/balance_controller/balance_controller.xpr Normal file
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@@ -0,0 +1,214 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB3/vivado/balance_controller/balance_controller.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="9307f0faa63246faab8b6e3351afc999"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirIES" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="14"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/balance_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="balance_controller"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<File Path="$PPRDIR/../../sim/tb_balance_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/tb_balance_controller_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_balance_controller"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_balance_controller_behav.wcfg"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

97
LAB3/vivado/balance_controller/tb_balance_controller_behav.wcfg Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="tb_balance_controller_behav.wdb" id="1">
<top_modules>
<top_module name="tb_balance_controller" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="116601fs"></ZoomEndTime>
<Cursor1Time time="100200fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="147"></NameColumnWidth>
<ValueColumnWidth column_width="98"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="16" />
<wvobject fp_name="/tb_balance_controller/aclk" type="logic">
<obj_property name="ElementShortName">aclk</obj_property>
<obj_property name="ObjectShortName">aclk</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/aresetn" type="logic">
<obj_property name="ElementShortName">aresetn</obj_property>
<obj_property name="ObjectShortName">aresetn</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider22">
<obj_property name="label">Balance</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/balance" type="array">
<obj_property name="ElementShortName">balance[9:0]</obj_property>
<obj_property name="ObjectShortName">balance[9:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/uut/left_shift" type="other">
<obj_property name="ElementShortName">left_shift</obj_property>
<obj_property name="ObjectShortName">left_shift</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/uut/right_shift" type="other">
<obj_property name="ElementShortName">right_shift</obj_property>
<obj_property name="ObjectShortName">right_shift</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider20">
<obj_property name="label">s_axis</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/s_axis_tdata" type="array">
<obj_property name="ElementShortName">s_axis_tdata[23:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tdata[23:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/s_axis_tlast" type="logic">
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/s_axis_tvalid" type="logic">
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
<obj_property name="CustomSignalColor">#00FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/s_axis_tready" type="logic">
<obj_property name="ElementShortName">s_axis_tready</obj_property>
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider21">
<obj_property name="label">m_axis</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/m_axis_tdata" type="array">
<obj_property name="ElementShortName">m_axis_tdata[23:0]</obj_property>
<obj_property name="ObjectShortName">m_axis_tdata[23:0]</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/m_axis_tlast" type="logic">
<obj_property name="ElementShortName">m_axis_tlast</obj_property>
<obj_property name="ObjectShortName">m_axis_tlast</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/m_axis_tvalid" type="logic">
<obj_property name="ElementShortName">m_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">m_axis_tvalid</obj_property>
<obj_property name="CustomSignalColor">#00FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/tb_balance_controller/m_axis_tready" type="logic">
<obj_property name="ElementShortName">m_axis_tready</obj_property>
<obj_property name="ObjectShortName">m_axis_tready</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wave_config>