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Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

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This commit is contained in:
Davide Cavagnola
2025-05-17 13:29:40 +02:00
parent 8fd7db7575
commit 1eb2181d1d
5 changed files with 173 additions and 168 deletions
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50
LAB3/design/diligent_jstk/diligent_jstk.bd
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@@ -5,7 +5,7 @@
"device": "xc7a35tcpg236-1",
"name": "diligent_jstk",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None",
"synth_flow_mode": "Hierarchical",
"tool_version": "2020.2",
"validated": "true"
},
@@ -71,7 +71,7 @@
"proc_sys_reset_0": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "diligent_jstk_proc_sys_reset_0_0",
"xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0\\diligent_jstk_proc_sys_reset_0_0.xci",
"xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0_1\\diligent_jstk_proc_sys_reset_0_0.xci",
"inst_hier_path": "proc_sys_reset_0",
"parameters": {
"RESET_BOARD_INTERFACE": {
@@ -99,7 +99,7 @@
"AXI4Stream_UART_0": {
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
"xci_name": "diligent_jstk_AXI4Stream_UART_0_0",
"xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0\\diligent_jstk_AXI4Stream_UART_0_0.xci",
"xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0_1\\diligent_jstk_AXI4Stream_UART_0_0.xci",
"inst_hier_path": "AXI4Stream_UART_0",
"parameters": {
"UART_BAUD_RATE": {
@@ -116,7 +116,7 @@
"jstk_uart_bridge_0": {
"vlnv": "xilinx.com:module_ref:jstk_uart_bridge:1.0",
"xci_name": "diligent_jstk_jstk_uart_bridge_0_0",
"xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0\\diligent_jstk_jstk_uart_bridge_0_0.xci",
"xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0_1\\diligent_jstk_jstk_uart_bridge_0_0.xci",
"inst_hier_path": "jstk_uart_bridge_0",
"reference_info": {
"ref_type": "hdl",
@@ -330,7 +330,7 @@
"axi4stream_spi_master_0": {
"vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0",
"xci_name": "diligent_jstk_axi4stream_spi_master_0_0",
"xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0\\diligent_jstk_axi4stream_spi_master_0_0.xci",
"xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0_1\\diligent_jstk_axi4stream_spi_master_0_0.xci",
"inst_hier_path": "axi4stream_spi_master_0",
"parameters": {
"c_sclkfreq": {
@@ -341,7 +341,7 @@
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"xci_name": "diligent_jstk_system_ila_0_0",
"xci_path": "ip\\diligent_jstk_system_ila_0_0\\diligent_jstk_system_ila_0_0.xci",
"xci_path": "ip\\diligent_jstk_system_ila_0_0_1\\diligent_jstk_system_ila_0_0.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_MON_TYPE": {
@@ -377,7 +377,7 @@
"digilent_jstk2_0": {
"vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
"xci_name": "diligent_jstk_digilent_jstk2_0_0",
"xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0\\diligent_jstk_digilent_jstk2_0_0.xci",
"xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0_1\\diligent_jstk_digilent_jstk2_0_0.xci",
"inst_hier_path": "digilent_jstk2_0",
"parameters": {
"SPI_SCLKFREQ": {
@@ -591,6 +591,18 @@
}
},
"interface_nets": {
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
@@ -604,30 +616,18 @@
"system_ila_0/SLOT_0_AXIS"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
},
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
}
},
"nets": {