PickleRick/DESD
1
0
Fork 0
Code Issues 2 Pull Requests Releases Activity

Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

Browse Source
This commit is contained in:
Davide Cavagnola
2025-05-17 13:29:40 +02:00
parent 8fd7db7575
commit 1eb2181d1d
5 changed files with 173 additions and 168 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
LAB3/design/diligent_jstk/diligent_jstk.bda
View File

@@ -21,22 +21,22 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VM">diligent_jstk</data>
<data key="VT">BC</data>
</node>
<node id="n1">
<data key="VH">2</data>
<data key="VM">diligent_jstk</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">diligent_jstk</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0">
<edge id="e0" source="n0" target="n1">
</edge>
<edge id="e1" source="n0" target="n1">
<edge id="e1" source="n1" target="n2">
</edge>
</graph>
</graphml>