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Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

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Davide Cavagnola
2025-05-17 13:29:40 +02:00
parent 8fd7db7575
commit 1eb2181d1d
5 changed files with 173 additions and 168 deletions
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LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
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@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri May 16 22:32:02 2025
--Date : Sat May 17 13:12:32 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper