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Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.

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This commit is contained in:
Davide Cavagnola
2025-05-17 13:29:40 +02:00
parent 8fd7db7575
commit 1eb2181d1d
5 changed files with 173 additions and 168 deletions
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50
LAB3/design/diligent_jstk/diligent_jstk.bd
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@@ -5,7 +5,7 @@
"device": "xc7a35tcpg236-1",
"name": "diligent_jstk",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None",
"synth_flow_mode": "Hierarchical",
"tool_version": "2020.2",
"validated": "true"
},
@@ -71,7 +71,7 @@
"proc_sys_reset_0": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "diligent_jstk_proc_sys_reset_0_0",
"xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0\\diligent_jstk_proc_sys_reset_0_0.xci",
"xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0_1\\diligent_jstk_proc_sys_reset_0_0.xci",
"inst_hier_path": "proc_sys_reset_0",
"parameters": {
"RESET_BOARD_INTERFACE": {
@@ -99,7 +99,7 @@
"AXI4Stream_UART_0": {
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
"xci_name": "diligent_jstk_AXI4Stream_UART_0_0",
"xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0\\diligent_jstk_AXI4Stream_UART_0_0.xci",
"xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0_1\\diligent_jstk_AXI4Stream_UART_0_0.xci",
"inst_hier_path": "AXI4Stream_UART_0",
"parameters": {
"UART_BAUD_RATE": {
@@ -116,7 +116,7 @@
"jstk_uart_bridge_0": {
"vlnv": "xilinx.com:module_ref:jstk_uart_bridge:1.0",
"xci_name": "diligent_jstk_jstk_uart_bridge_0_0",
"xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0\\diligent_jstk_jstk_uart_bridge_0_0.xci",
"xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0_1\\diligent_jstk_jstk_uart_bridge_0_0.xci",
"inst_hier_path": "jstk_uart_bridge_0",
"reference_info": {
"ref_type": "hdl",
@@ -330,7 +330,7 @@
"axi4stream_spi_master_0": {
"vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0",
"xci_name": "diligent_jstk_axi4stream_spi_master_0_0",
"xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0\\diligent_jstk_axi4stream_spi_master_0_0.xci",
"xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0_1\\diligent_jstk_axi4stream_spi_master_0_0.xci",
"inst_hier_path": "axi4stream_spi_master_0",
"parameters": {
"c_sclkfreq": {
@@ -341,7 +341,7 @@
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"xci_name": "diligent_jstk_system_ila_0_0",
"xci_path": "ip\\diligent_jstk_system_ila_0_0\\diligent_jstk_system_ila_0_0.xci",
"xci_path": "ip\\diligent_jstk_system_ila_0_0_1\\diligent_jstk_system_ila_0_0.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_MON_TYPE": {
@@ -377,7 +377,7 @@
"digilent_jstk2_0": {
"vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
"xci_name": "diligent_jstk_digilent_jstk2_0_0",
"xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0\\diligent_jstk_digilent_jstk2_0_0.xci",
"xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0_1\\diligent_jstk_digilent_jstk2_0_0.xci",
"inst_hier_path": "digilent_jstk2_0",
"parameters": {
"SPI_SCLKFREQ": {
@@ -591,6 +591,18 @@
}
},
"interface_nets": {
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
@@ -604,30 +616,18 @@
"system_ila_0/SLOT_0_AXIS"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
},
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
}
},
"nets": {

14
LAB3/design/diligent_jstk/diligent_jstk.bda
View File

@@ -21,22 +21,22 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VM">diligent_jstk</data>
<data key="VT">BC</data>
</node>
<node id="n1">
<data key="VH">2</data>
<data key="VM">diligent_jstk</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">diligent_jstk</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0">
<edge id="e0" source="n0" target="n1">
</edge>
<edge id="e1" source="n0" target="n1">
<edge id="e1" source="n1" target="n2">
</edge>
</graph>
</graphml>

2
LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
View File

@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri May 16 22:32:02 2025
--Date : Sat May 17 13:12:32 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper

31
LAB3/src/digilent_jstk2.vhd
View File

@@ -45,7 +45,7 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
CONSTANT DELAY_CLK_CYCLES : INTEGER := DELAY_US * (CLKFREQ / 1_000_000);
-- State machine states
TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY, WAIT_READY);
TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY);
TYPE rx_state_type IS (JSTK_X_LOW, JSTK_X_HIGH, JSTK_Y_LOW, JSTK_Y_HIGH, BUTTONS);
SIGNAL tx_state : tx_state_type := DELAY;
@@ -59,13 +59,27 @@ BEGIN
-- The SPI IP-Core is a slave, so we must set the m_axis_tvalid signal to '1' when we want to send data to it.
WITH tx_state SELECT m_axis_tvalid <=
'0' WHEN DELAY,
'1' WHEN OTHERS;
'1' WHEN SEND_CMD,
'1' WHEN SEND_RED,
'1' WHEN SEND_GREEN,
'1' WHEN SEND_BLUE,
'1' WHEN SEND_DUMMY;
-- Send the data to the SPI IP-Core based on the current state of the TX FSM
WITH tx_state SELECT m_axis_tdata <=
(OTHERS => '0') WHEN DELAY,
CMDSETLEDRGB WHEN SEND_CMD,
led_r WHEN SEND_RED,
led_g WHEN SEND_GREEN,
led_b WHEN SEND_BLUE,
"01101000" WHEN SEND_DUMMY; -- Dummy byte
-- TX FSM: invia un nuovo comando solo dopo che la risposta precedente <20> stata ricevuta (rx_done = '1')
TX : PROCESS (aclk)
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
tx_state <= DELAY;
m_axis_tdata <= (OTHERS => '0');
tx_delay_counter <= 0;
@@ -83,36 +97,27 @@ BEGIN
END IF;
WHEN SEND_CMD =>
IF m_axis_tready = '1' THEN
tx_state <= SEND_RED;
m_axis_tdata <= CMDSETLEDRGB;
END IF;
WHEN SEND_RED =>
IF m_axis_tready = '1' THEN
m_axis_tdata <= led_r;
tx_state <= SEND_GREEN;
END IF;
WHEN SEND_GREEN =>
IF m_axis_tready = '1' THEN
m_axis_tdata <= led_g;
tx_state <= SEND_BLUE;
END IF;
WHEN SEND_BLUE =>
IF m_axis_tready = '1' THEN
m_axis_tdata <= led_b;
tx_state <= SEND_DUMMY;
END IF;
WHEN SEND_DUMMY =>
IF m_axis_tready = '1' THEN
m_axis_tdata <= "01101000"; -- Dummy byte
tx_state <= WAIT_READY;
END IF;
WHEN WAIT_READY =>
IF m_axis_tready = '1' THEN
m_axis_tdata <= "01000101"; -- Dummy byte not readed
tx_state <= DELAY;
END IF;

10
LAB3/test/uart_viewer.py
View File

@@ -40,18 +40,18 @@ def receive_graph_mode(ser):
if ser.in_waiting >= CHUNK_SIZE:
data = ser.read(CHUNK_SIZE)
if len(data) >= 2:
x = data[0]
y = data[1]
x = data[1]
y = data[2]
q.put((x, y))
reader_thread = threading.Thread(target=serial_reader, daemon=True)
reader_thread.start()
latest_point = [0, 0]
latest_point = [64, 64] # Punto iniziale al centro del grafico
fig, ax = plt.subplots()
sc = ax.scatter([latest_point[0]], [latest_point[1]])
ax.set_xlim(0, 255)
ax.set_ylim(0, 255)
ax.set_xlim(0, 127)
ax.set_ylim(0, 127)
ax.set_xlabel("X")
ax.set_ylabel("Y")
ax.set_title("Coordinate in tempo reale")