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fix: DELAY_CLK_CYCLES

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This commit is contained in:
Davide Cavagnola
2025-05-30 19:31:36 +02:00
parent d65bb35afe
commit 2448aecddf
1 changed files with 1 additions and 3 deletions
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4
LAB3/src/digilent_jstk2.vhd
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@@ -43,10 +43,8 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
CONSTANT CMDSETLEDRGB : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"84"; CONSTANT CMDSETLEDRGB : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"84";
-- Calculate delay in clock cycles: (delay_period + 1_SPI_clock_period) * clock_frequency -- Calculate delay in clock cycles: (delay_period + 1_SPI_clock_period) * clock_frequency
-- Uses integer arithmetic optimized to avoid truncation by performing multiplications before divisions
-- Formula: ((DELAY_US * SPI_SCLKFREQ + 1_000_000) * CLKFREQ) / (SPI_SCLKFREQ * 1_000_000)
-- This ensures proper timing between SPI packets as required by JSTK2 datasheet -- This ensures proper timing between SPI packets as required by JSTK2 datasheet
CONSTANT DELAY_CLK_CYCLES : INTEGER := ((DELAY_US * SPI_SCLKFREQ + 1_000_000) * CLKFREQ) / (SPI_SCLKFREQ * 1_000_000) + 1; CONSTANT DELAY_CLK_CYCLES : INTEGER := (DELAY_US + 1_000_000 / SPI_SCLKFREQ) * (CLKFREQ / 1_000_000);
-- State machine type definitions -- State machine type definitions
TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY); TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY);