diff --git a/.gitignore b/.gitignore
index 488d631..7747d92 100644
--- a/.gitignore
+++ b/.gitignore
@@ -42,7 +42,6 @@
*.qws
*.wdf
*.lpr
-*.xdc
*.bxml
@@ -76,6 +75,7 @@ vivado*.backup.log
**/design/**/synth/
**/design/**/ui/
**/design/**/hw_handoff/
+**/design/**/*.xdc
# Other files
**/test/*.zip
\ No newline at end of file
diff --git a/LAB2/design/lab_2/hdl/lab_2_wrapper.vhd b/LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
index 794efb5..f0aac0e 100644
--- a/LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
+++ b/LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
@@ -1,8 +1,8 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date : Fri Apr 25 22:08:38 2025
---Host : DavideASUS running 64-bit major release (build 9200)
+--Date : Mon May 12 14:33:04 2025
+--Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target lab_2_wrapper.bd
--Design : lab_2_wrapper
--Purpose : IP block netlist
diff --git a/LAB2/design/lab_2/lab_2.bd b/LAB2/design/lab_2/lab_2.bd
index 556d62b..5c8e70f 100644
--- a/LAB2/design/lab_2/lab_2.bd
+++ b/LAB2/design/lab_2/lab_2.bd
@@ -1176,11 +1176,11 @@
"system_ila_0/SLOT_2_AXIS"
]
},
- "img_conv_0_m_axis": {
+ "Conn": {
"interface_ports": [
- "img_conv_0/m_axis",
- "packetizer_0/s_axis",
- "system_ila_0/SLOT_1_AXIS"
+ "rgb2gray_0/s_axis",
+ "depacketizer_0/m_axis",
+ "system_ila_0/SLOT_0_AXIS"
]
},
"AXI4Stream_UART_0_UART": {
@@ -1201,11 +1201,11 @@
"AXI4Stream_UART_0/S00_AXIS_TX"
]
},
- "Conn": {
+ "img_conv_0_m_axis": {
"interface_ports": [
- "rgb2gray_0/s_axis",
- "depacketizer_0/m_axis",
- "system_ila_0/SLOT_0_AXIS"
+ "img_conv_0/m_axis",
+ "packetizer_0/s_axis",
+ "system_ila_0/SLOT_1_AXIS"
]
}
},
diff --git a/LAB2/design/lab_2/lab_2.bda b/LAB2/design/lab_2/lab_2.bda
index d2be325..8223b12 100644
--- a/LAB2/design/lab_2/lab_2.bda
+++ b/LAB2/design/lab_2/lab_2.bda
@@ -21,22 +21,22 @@
- active
2
- PM
+ lab_2
+ VR
lab_2
BC
+ active
2
- lab_2
- VR
+ PM
-
+
-
+
diff --git a/LAB2/vivado/lab2/lab2.xpr b/LAB2/vivado/lab2/lab2.xpr
index 17e57a7..51e444c 100644
--- a/LAB2/vivado/lab2/lab2.xpr
+++ b/LAB2/vivado/lab2/lab2.xpr
@@ -55,13 +55,13 @@
-
-
-
-
-
-
-
+
+
+
+
+
+
+
@@ -203,17 +203,16 @@
-
+
-
-
+
@@ -226,7 +225,6 @@
-
diff --git a/LAB3/cons/io.xdc b/LAB3/cons/io.xdc
new file mode 100644
index 0000000..ee4f8ea
--- /dev/null
+++ b/LAB3/cons/io.xdc
@@ -0,0 +1,13 @@
+# SPI connected to JA, top row
+set_property PACKAGE_PIN J1 [get_ports SPI_M_0_ss_io]
+set_property PACKAGE_PIN G2 [get_ports SPI_M_0_sck_io]
+set_property PACKAGE_PIN L2 [get_ports SPI_M_0_io0_io]
+set_property PACKAGE_PIN J2 [get_ports SPI_M_0_io1_io]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io0_io]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io1_io]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_sck_io]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_ss_io]
+set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io0_io]
+set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io1_io]
+set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_sck_io]
+set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_ss_io]
diff --git a/LAB3/design/lab_3/lab_3.bd b/LAB3/design/lab_3/lab_3.bd
new file mode 100644
index 0000000..d980001
--- /dev/null
+++ b/LAB3/design/lab_3/lab_3.bd
@@ -0,0 +1,2104 @@
+{
+ "design": {
+ "design_info": {
+ "boundary_crc": "0xFF71C05CB0B1FCB6",
+ "device": "xc7a35tcpg236-1",
+ "gen_directory": "../../../../lab3.gen/sources_1/bd/lab_3",
+ "name": "lab_3",
+ "rev_ctrl_bd_flag": "RevCtrlBdOff",
+ "synth_flow_mode": "None",
+ "tool_version": "2020.2",
+ "validated": "true"
+ },
+ "design_tree": {
+ "clk_wiz_0": "",
+ "proc_sys_reset_0": "",
+ "proc_sys_reset_1": "",
+ "digilent_jstk2_0": "",
+ "edge_detector_toggle_0": "",
+ "edge_detector_toggle_1": "",
+ "debouncer_0": "",
+ "axis_broadcaster_0": "",
+ "moving_average_filte_0": "",
+ "volume_controller_0": "",
+ "LFO_0": "",
+ "balance_controller_0": "",
+ "effect_selector_0": "",
+ "led_controller_0": "",
+ "led_level_controller_0": "",
+ "mute_controller_0": "",
+ "axi4stream_spi_master_0": "",
+ "axis_dual_i2s_0": ""
+ },
+ "interface_ports": {
+ "SPI_M_0": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:spi_rtl:1.0"
+ }
+ },
+ "ports": {
+ "sys_clock": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "CLK_DOMAIN": {
+ "value": "lab_3_sys_clock",
+ "value_src": "default"
+ },
+ "FREQ_HZ": {
+ "value": "100000000"
+ },
+ "FREQ_TOLERANCE_HZ": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.000"
+ }
+ }
+ },
+ "reset": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "POLARITY": {
+ "value": "ACTIVE_HIGH"
+ }
+ }
+ },
+ "tx_lrck_0": {
+ "direction": "O"
+ },
+ "rx_sdin_0": {
+ "direction": "I"
+ },
+ "rx_sclk_0": {
+ "direction": "O"
+ },
+ "rx_lrck_0": {
+ "direction": "O"
+ },
+ "rx_mclk_0": {
+ "direction": "O"
+ },
+ "tx_sdout_0": {
+ "direction": "O"
+ },
+ "tx_sclk_0": {
+ "direction": "O"
+ },
+ "tx_mclk_0": {
+ "direction": "O"
+ },
+ "lfo_enable": {
+ "direction": "I"
+ },
+ "effect": {
+ "direction": "I"
+ },
+ "LED": {
+ "direction": "O",
+ "left": "15",
+ "right": "0"
+ }
+ },
+ "components": {
+ "clk_wiz_0": {
+ "vlnv": "xilinx.com:ip:clk_wiz:6.0",
+ "xci_name": "lab_3_clk_wiz_0_0",
+ "xci_path": "ip\\lab_3_clk_wiz_0_0\\lab_3_clk_wiz_0_0.xci",
+ "inst_hier_path": "clk_wiz_0",
+ "parameters": {
+ "CLKOUT1_JITTER": {
+ "value": "149.337"
+ },
+ "CLKOUT1_PHASE_ERROR": {
+ "value": "122.577"
+ },
+ "CLKOUT1_REQUESTED_OUT_FREQ": {
+ "value": "100"
+ },
+ "CLKOUT2_JITTER": {
+ "value": "201.826"
+ },
+ "CLKOUT2_PHASE_ERROR": {
+ "value": "122.577"
+ },
+ "CLKOUT2_REQUESTED_OUT_FREQ": {
+ "value": "22.579"
+ },
+ "CLKOUT2_USED": {
+ "value": "true"
+ },
+ "CLK_IN1_BOARD_INTERFACE": {
+ "value": "sys_clock"
+ },
+ "MMCM_CLKFBOUT_MULT_F": {
+ "value": "7.000"
+ },
+ "MMCM_CLKOUT0_DIVIDE_F": {
+ "value": "7.000"
+ },
+ "MMCM_CLKOUT1_DIVIDE": {
+ "value": "31"
+ },
+ "MMCM_DIVCLK_DIVIDE": {
+ "value": "1"
+ },
+ "NUM_OUT_CLKS": {
+ "value": "2"
+ },
+ "RESET_BOARD_INTERFACE": {
+ "value": "reset"
+ },
+ "USE_BOARD_FLOW": {
+ "value": "true"
+ },
+ "USE_LOCKED": {
+ "value": "true"
+ }
+ }
+ },
+ "proc_sys_reset_0": {
+ "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
+ "xci_name": "lab_3_proc_sys_reset_0_0",
+ "xci_path": "ip\\lab_3_proc_sys_reset_0_0\\lab_3_proc_sys_reset_0_0.xci",
+ "inst_hier_path": "proc_sys_reset_0"
+ },
+ "proc_sys_reset_1": {
+ "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
+ "xci_name": "lab_3_proc_sys_reset_1_0",
+ "xci_path": "ip\\lab_3_proc_sys_reset_1_0\\lab_3_proc_sys_reset_1_0.xci",
+ "inst_hier_path": "proc_sys_reset_1"
+ },
+ "digilent_jstk2_0": {
+ "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
+ "xci_name": "lab_3_digilent_jstk2_0_0",
+ "xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci",
+ "inst_hier_path": "digilent_jstk2_0",
+ "parameters": {
+ "CLKFREQ": {
+ "value": "215000000"
+ }
+ },
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "digilent_jstk2",
+ "boundary_crc": "0x0"
+ },
+ "interface_ports": {
+ "m_axis": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "m_axis_tdata",
+ "direction": "O",
+ "left": "7",
+ "right": "0"
+ },
+ "TVALID": {
+ "physical_name": "m_axis_tvalid",
+ "direction": "O"
+ },
+ "TREADY": {
+ "physical_name": "m_axis_tready",
+ "direction": "I"
+ }
+ }
+ },
+ "s_axis": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "s_axis_tdata",
+ "direction": "I",
+ "left": "7",
+ "right": "0"
+ },
+ "TVALID": {
+ "physical_name": "s_axis_tvalid",
+ "direction": "I"
+ }
+ }
+ }
+ },
+ "ports": {
+ "aclk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "m_axis:s_axis",
+ "value_src": "constant"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "aresetn",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "aresetn": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "constant"
+ }
+ }
+ },
+ "jstk_x": {
+ "direction": "O",
+ "left": "9",
+ "right": "0"
+ },
+ "jstk_y": {
+ "direction": "O",
+ "left": "9",
+ "right": "0"
+ },
+ "btn_jstk": {
+ "direction": "O"
+ },
+ "btn_trigger": {
+ "direction": "O"
+ },
+ "led_r": {
+ "direction": "I",
+ "left": "7",
+ "right": "0"
+ },
+ "led_g": {
+ "direction": "I",
+ "left": "7",
+ "right": "0"
+ },
+ "led_b": {
+ "direction": "I",
+ "left": "7",
+ "right": "0"
+ }
+ }
+ },
+ "edge_detector_toggle_0": {
+ "vlnv": "xilinx.com:module_ref:edge_detector_toggle:1.0",
+ "xci_name": "lab_3_edge_detector_toggle_0_0",
+ "xci_path": "ip\\lab_3_edge_detector_toggle_0_0\\lab_3_edge_detector_toggle_0_0.xci",
+ "inst_hier_path": "edge_detector_toggle_0",
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "edge_detector_toggle",
+ "boundary_crc": "0x0"
+ },
+ "ports": {
+ "input_signal": {
+ "direction": "I"
+ },
+ "clk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_RESET": {
+ "value": "reset",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "reset": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_HIGH",
+ "value_src": "const_prop"
+ }
+ }
+ },
+ "output_signal": {
+ "direction": "O"
+ }
+ }
+ },
+ "edge_detector_toggle_1": {
+ "vlnv": "xilinx.com:module_ref:edge_detector_toggle:1.0",
+ "xci_name": "lab_3_edge_detector_toggle_1_0",
+ "xci_path": "ip\\lab_3_edge_detector_toggle_1_0\\lab_3_edge_detector_toggle_1_0.xci",
+ "inst_hier_path": "edge_detector_toggle_1",
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "edge_detector_toggle",
+ "boundary_crc": "0x0"
+ },
+ "ports": {
+ "input_signal": {
+ "direction": "I"
+ },
+ "clk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_RESET": {
+ "value": "reset",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "reset": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_HIGH",
+ "value_src": "const_prop"
+ }
+ }
+ },
+ "output_signal": {
+ "direction": "O"
+ }
+ }
+ },
+ "debouncer_0": {
+ "vlnv": "xilinx.com:module_ref:debouncer:1.0",
+ "xci_name": "lab_3_debouncer_0_0",
+ "xci_path": "ip\\lab_3_debouncer_0_0\\lab_3_debouncer_0_0.xci",
+ "inst_hier_path": "debouncer_0",
+ "parameters": {
+ "CLOCK_FREQ": {
+ "value": "200000000"
+ }
+ },
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "debouncer",
+ "boundary_crc": "0x0"
+ },
+ "ports": {
+ "clk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_RESET": {
+ "value": "reset",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "reset": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "const_prop"
+ }
+ }
+ },
+ "input_signal": {
+ "direction": "I"
+ },
+ "debounced": {
+ "direction": "O"
+ }
+ }
+ },
+ "axis_broadcaster_0": {
+ "vlnv": "xilinx.com:ip:axis_broadcaster:1.1",
+ "xci_name": "lab_3_axis_broadcaster_0_0",
+ "xci_path": "ip\\lab_3_axis_broadcaster_0_0\\lab_3_axis_broadcaster_0_0.xci",
+ "inst_hier_path": "axis_broadcaster_0"
+ },
+ "moving_average_filte_0": {
+ "vlnv": "xilinx.com:module_ref:moving_average_filter_en:1.0",
+ "xci_name": "lab_3_moving_average_filte_0_0",
+ "xci_path": "ip\\lab_3_moving_average_filte_0_0\\lab_3_moving_average_filte_0_0.xci",
+ "inst_hier_path": "moving_average_filte_0",
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "moving_average_filter_en",
+ "boundary_crc": "0x0"
+ },
+ "interface_ports": {
+ "m_axis": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "m_axis_tdata",
+ "direction": "O",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "m_axis_tlast",
+ "direction": "O"
+ },
+ "TVALID": {
+ "physical_name": "m_axis_tvalid",
+ "direction": "O"
+ },
+ "TREADY": {
+ "physical_name": "m_axis_tready",
+ "direction": "I"
+ }
+ }
+ },
+ "s_axis": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "s_axis_tdata",
+ "direction": "I",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "s_axis_tlast",
+ "direction": "I"
+ },
+ "TVALID": {
+ "physical_name": "s_axis_tvalid",
+ "direction": "I"
+ },
+ "TREADY": {
+ "physical_name": "s_axis_tready",
+ "direction": "O"
+ }
+ }
+ }
+ },
+ "ports": {
+ "aclk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "m_axis:s_axis",
+ "value_src": "constant"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "aresetn",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "aresetn": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "constant"
+ }
+ }
+ },
+ "enable_filter": {
+ "direction": "I"
+ }
+ }
+ },
+ "volume_controller_0": {
+ "vlnv": "xilinx.com:module_ref:volume_controller:1.0",
+ "xci_name": "lab_3_volume_controller_0_0",
+ "xci_path": "ip\\lab_3_volume_controller_0_0\\lab_3_volume_controller_0_0.xci",
+ "inst_hier_path": "volume_controller_0",
+ "parameters": {
+ "LOWER_BOUND": {
+ "value": "-8388608"
+ }
+ },
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "volume_controller",
+ "boundary_crc": "0x0"
+ },
+ "interface_ports": {
+ "m_axis": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "m_axis_tdata",
+ "direction": "O",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "m_axis_tlast",
+ "direction": "O"
+ },
+ "TVALID": {
+ "physical_name": "m_axis_tvalid",
+ "direction": "O"
+ },
+ "TREADY": {
+ "physical_name": "m_axis_tready",
+ "direction": "I"
+ }
+ }
+ },
+ "s_axis": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "s_axis_tdata",
+ "direction": "I",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "s_axis_tlast",
+ "direction": "I"
+ },
+ "TVALID": {
+ "physical_name": "s_axis_tvalid",
+ "direction": "I"
+ },
+ "TREADY": {
+ "physical_name": "s_axis_tready",
+ "direction": "O"
+ }
+ }
+ }
+ },
+ "ports": {
+ "aclk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "m_axis:s_axis",
+ "value_src": "constant"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "aresetn",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "aresetn": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "constant"
+ }
+ }
+ },
+ "volume": {
+ "direction": "I",
+ "left": "9",
+ "right": "0"
+ }
+ }
+ },
+ "LFO_0": {
+ "vlnv": "xilinx.com:module_ref:LFO:1.0",
+ "xci_name": "lab_3_LFO_0_0",
+ "xci_path": "ip\\lab_3_LFO_0_0\\lab_3_LFO_0_0.xci",
+ "inst_hier_path": "LFO_0",
+ "parameters": {
+ "CLK_PERIOD_NS": {
+ "value": "10"
+ }
+ },
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "LFO",
+ "boundary_crc": "0x0"
+ },
+ "interface_ports": {
+ "m_axis": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "m_axis_tdata",
+ "direction": "O",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "m_axis_tlast",
+ "direction": "O"
+ },
+ "TVALID": {
+ "physical_name": "m_axis_tvalid",
+ "direction": "O"
+ },
+ "TREADY": {
+ "physical_name": "m_axis_tready",
+ "direction": "I"
+ }
+ }
+ },
+ "s_axis": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "s_axis_tdata",
+ "direction": "I",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "s_axis_tlast",
+ "direction": "I"
+ },
+ "TVALID": {
+ "physical_name": "s_axis_tvalid",
+ "direction": "I"
+ },
+ "TREADY": {
+ "physical_name": "s_axis_tready",
+ "direction": "O"
+ }
+ }
+ }
+ },
+ "ports": {
+ "aclk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "m_axis:s_axis",
+ "value_src": "constant"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "aresetn",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "aresetn": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "constant"
+ }
+ }
+ },
+ "lfo_period": {
+ "direction": "I",
+ "left": "9",
+ "right": "0"
+ },
+ "lfo_enable": {
+ "direction": "I"
+ }
+ }
+ },
+ "balance_controller_0": {
+ "vlnv": "xilinx.com:module_ref:balance_controller:1.0",
+ "xci_name": "lab_3_balance_controller_0_0",
+ "xci_path": "ip\\lab_3_balance_controller_0_0\\lab_3_balance_controller_0_0.xci",
+ "inst_hier_path": "balance_controller_0",
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "balance_controller",
+ "boundary_crc": "0x0"
+ },
+ "interface_ports": {
+ "m_axis": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "m_axis_tdata",
+ "direction": "O",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "m_axis_tlast",
+ "direction": "O"
+ },
+ "TVALID": {
+ "physical_name": "m_axis_tvalid",
+ "direction": "O"
+ },
+ "TREADY": {
+ "physical_name": "m_axis_tready",
+ "direction": "I"
+ }
+ }
+ },
+ "s_axis": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "s_axis_tdata",
+ "direction": "I",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "s_axis_tlast",
+ "direction": "I"
+ },
+ "TVALID": {
+ "physical_name": "s_axis_tvalid",
+ "direction": "I"
+ },
+ "TREADY": {
+ "physical_name": "s_axis_tready",
+ "direction": "O"
+ }
+ }
+ }
+ },
+ "ports": {
+ "aclk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "m_axis:s_axis",
+ "value_src": "constant"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "aresetn",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "aresetn": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "constant"
+ }
+ }
+ },
+ "balance": {
+ "direction": "I",
+ "left": "9",
+ "right": "0"
+ }
+ }
+ },
+ "effect_selector_0": {
+ "vlnv": "xilinx.com:module_ref:effect_selector:1.0",
+ "xci_name": "lab_3_effect_selector_0_0",
+ "xci_path": "ip\\lab_3_effect_selector_0_0\\lab_3_effect_selector_0_0.xci",
+ "inst_hier_path": "effect_selector_0",
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "effect_selector",
+ "boundary_crc": "0x0"
+ },
+ "ports": {
+ "aclk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_RESET": {
+ "value": "aresetn",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "aresetn": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "constant"
+ }
+ }
+ },
+ "effect": {
+ "direction": "I"
+ },
+ "jstck_x": {
+ "direction": "I",
+ "left": "9",
+ "right": "0"
+ },
+ "jstck_y": {
+ "direction": "I",
+ "left": "9",
+ "right": "0"
+ },
+ "volume": {
+ "direction": "O",
+ "left": "9",
+ "right": "0"
+ },
+ "balance": {
+ "direction": "O",
+ "left": "9",
+ "right": "0"
+ },
+ "lfo_period": {
+ "direction": "O",
+ "left": "9",
+ "right": "0"
+ }
+ }
+ },
+ "led_controller_0": {
+ "vlnv": "xilinx.com:module_ref:led_controller:1.0",
+ "xci_name": "lab_3_led_controller_0_1",
+ "xci_path": "ip\\lab_3_led_controller_0_1\\lab_3_led_controller_0_1.xci",
+ "inst_hier_path": "led_controller_0",
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "led_controller",
+ "boundary_crc": "0x0"
+ },
+ "ports": {
+ "mute_enable": {
+ "direction": "I"
+ },
+ "filter_enable": {
+ "direction": "I"
+ },
+ "led_r": {
+ "direction": "O",
+ "left": "7",
+ "right": "0"
+ },
+ "led_g": {
+ "direction": "O",
+ "left": "7",
+ "right": "0"
+ },
+ "led_b": {
+ "direction": "O",
+ "left": "7",
+ "right": "0"
+ }
+ }
+ },
+ "led_level_controller_0": {
+ "vlnv": "xilinx.com:module_ref:led_level_controller:1.0",
+ "xci_name": "lab_3_led_level_controller_0_0",
+ "xci_path": "ip\\lab_3_led_level_controller_0_0\\lab_3_led_level_controller_0_0.xci",
+ "inst_hier_path": "led_level_controller_0",
+ "parameters": {
+ "clock_period_ns": {
+ "value": "10"
+ }
+ },
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "led_level_controller",
+ "boundary_crc": "0x0"
+ },
+ "interface_ports": {
+ "s_axis": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "s_axis_tdata",
+ "direction": "I",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "s_axis_tlast",
+ "direction": "I"
+ },
+ "TVALID": {
+ "physical_name": "s_axis_tvalid",
+ "direction": "I"
+ },
+ "TREADY": {
+ "physical_name": "s_axis_tready",
+ "direction": "O"
+ }
+ }
+ }
+ },
+ "ports": {
+ "aclk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "s_axis",
+ "value_src": "constant"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "aresetn",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "aresetn": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "constant"
+ }
+ }
+ },
+ "led": {
+ "direction": "O",
+ "left": "15",
+ "right": "0"
+ }
+ }
+ },
+ "mute_controller_0": {
+ "vlnv": "xilinx.com:module_ref:mute_controller:1.0",
+ "xci_name": "lab_3_mute_controller_0_0",
+ "xci_path": "ip\\lab_3_mute_controller_0_0\\lab_3_mute_controller_0_0.xci",
+ "inst_hier_path": "mute_controller_0",
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "mute_controller",
+ "boundary_crc": "0x0"
+ },
+ "interface_ports": {
+ "m_axis": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "m_axis_tdata",
+ "direction": "O",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "m_axis_tlast",
+ "direction": "O"
+ },
+ "TVALID": {
+ "physical_name": "m_axis_tvalid",
+ "direction": "O"
+ },
+ "TREADY": {
+ "physical_name": "m_axis_tready",
+ "direction": "I"
+ }
+ }
+ },
+ "s_axis": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+ "parameters": {
+ "TDATA_NUM_BYTES": {
+ "value": "3",
+ "value_src": "auto"
+ },
+ "TDEST_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "TUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TREADY": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_TSTRB": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TKEEP": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_TLAST": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ },
+ "port_maps": {
+ "TDATA": {
+ "physical_name": "s_axis_tdata",
+ "direction": "I",
+ "left": "23",
+ "right": "0"
+ },
+ "TLAST": {
+ "physical_name": "s_axis_tlast",
+ "direction": "I"
+ },
+ "TVALID": {
+ "physical_name": "s_axis_tvalid",
+ "direction": "I"
+ },
+ "TREADY": {
+ "physical_name": "s_axis_tready",
+ "direction": "O"
+ }
+ }
+ }
+ },
+ "ports": {
+ "aclk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "m_axis:s_axis",
+ "value_src": "constant"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "aresetn",
+ "value_src": "constant"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "/clk_wiz_0_clk_out1",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "aresetn": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "constant"
+ }
+ }
+ },
+ "mute": {
+ "direction": "I"
+ }
+ }
+ },
+ "axi4stream_spi_master_0": {
+ "vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0",
+ "xci_name": "lab_3_axi4stream_spi_master_0_0",
+ "xci_path": "ip\\lab_3_axi4stream_spi_master_0_0\\lab_3_axi4stream_spi_master_0_0.xci",
+ "inst_hier_path": "axi4stream_spi_master_0",
+ "parameters": {
+ "c_clkfreq": {
+ "value": "215000000"
+ },
+ "c_sclkfreq": {
+ "value": "5000"
+ }
+ }
+ },
+ "axis_dual_i2s_0": {
+ "vlnv": "DigiLAB:ip:axis_dual_i2s:1.0",
+ "xci_name": "lab_3_axis_dual_i2s_0_0",
+ "xci_path": "ip\\lab_3_axis_dual_i2s_0_0\\lab_3_axis_dual_i2s_0_0.xci",
+ "inst_hier_path": "axis_dual_i2s_0"
+ }
+ },
+ "interface_nets": {
+ "volume_controller_0_m_axis": {
+ "interface_ports": [
+ "volume_controller_0/m_axis",
+ "LFO_0/s_axis"
+ ]
+ },
+ "digilent_jstk2_0_m_axis": {
+ "interface_ports": [
+ "digilent_jstk2_0/m_axis",
+ "axi4stream_spi_master_0/S_AXIS"
+ ]
+ },
+ "axis_dual_i2s_0_m_axis": {
+ "interface_ports": [
+ "axis_dual_i2s_0/m_axis",
+ "moving_average_filte_0/s_axis"
+ ]
+ },
+ "mute_controller_0_m_axis": {
+ "interface_ports": [
+ "mute_controller_0/m_axis",
+ "axis_broadcaster_0/S_AXIS"
+ ]
+ },
+ "LFO_0_m_axis": {
+ "interface_ports": [
+ "LFO_0/m_axis",
+ "mute_controller_0/s_axis"
+ ]
+ },
+ "axi4stream_spi_master_0_SPI_M": {
+ "interface_ports": [
+ "SPI_M_0",
+ "axi4stream_spi_master_0/SPI_M"
+ ]
+ },
+ "moving_average_filte_0_m_axis": {
+ "interface_ports": [
+ "balance_controller_0/s_axis",
+ "moving_average_filte_0/m_axis"
+ ]
+ },
+ "balance_controller_0_m_axis": {
+ "interface_ports": [
+ "balance_controller_0/m_axis",
+ "volume_controller_0/s_axis"
+ ]
+ },
+ "axis_broadcaster_0_M01_AXIS": {
+ "interface_ports": [
+ "axis_broadcaster_0/M01_AXIS",
+ "led_level_controller_0/s_axis"
+ ]
+ },
+ "axis_broadcaster_0_M00_AXIS": {
+ "interface_ports": [
+ "axis_broadcaster_0/M00_AXIS",
+ "axis_dual_i2s_0/s_axis"
+ ]
+ },
+ "axi4stream_spi_master_0_M_AXIS": {
+ "interface_ports": [
+ "axi4stream_spi_master_0/M_AXIS",
+ "digilent_jstk2_0/s_axis"
+ ]
+ }
+ },
+ "nets": {
+ "sys_clock_1": {
+ "ports": [
+ "sys_clock",
+ "clk_wiz_0/clk_in1"
+ ]
+ },
+ "clk_wiz_0_clk_out1": {
+ "ports": [
+ "clk_wiz_0/clk_out1",
+ "proc_sys_reset_0/slowest_sync_clk",
+ "digilent_jstk2_0/aclk",
+ "edge_detector_toggle_0/clk",
+ "edge_detector_toggle_1/clk",
+ "debouncer_0/clk",
+ "axis_broadcaster_0/aclk",
+ "moving_average_filte_0/aclk",
+ "volume_controller_0/aclk",
+ "LFO_0/aclk",
+ "balance_controller_0/aclk",
+ "effect_selector_0/aclk",
+ "led_level_controller_0/aclk",
+ "mute_controller_0/aclk",
+ "axi4stream_spi_master_0/aclk",
+ "axis_dual_i2s_0/aclk"
+ ]
+ },
+ "reset_1": {
+ "ports": [
+ "reset",
+ "clk_wiz_0/reset",
+ "proc_sys_reset_0/ext_reset_in",
+ "proc_sys_reset_1/ext_reset_in"
+ ]
+ },
+ "clk_wiz_0_locked": {
+ "ports": [
+ "clk_wiz_0/locked",
+ "proc_sys_reset_0/dcm_locked",
+ "proc_sys_reset_1/dcm_locked"
+ ]
+ },
+ "clk_wiz_0_clk_out2": {
+ "ports": [
+ "clk_wiz_0/clk_out2",
+ "proc_sys_reset_1/slowest_sync_clk",
+ "axis_dual_i2s_0/i2s_clk"
+ ]
+ },
+ "proc_sys_reset_0_peripheral_aresetn": {
+ "ports": [
+ "proc_sys_reset_0/peripheral_aresetn",
+ "digilent_jstk2_0/aresetn",
+ "debouncer_0/reset",
+ "axis_broadcaster_0/aresetn",
+ "moving_average_filte_0/aresetn",
+ "volume_controller_0/aresetn",
+ "LFO_0/aresetn",
+ "balance_controller_0/aresetn",
+ "effect_selector_0/aresetn",
+ "led_level_controller_0/aresetn",
+ "mute_controller_0/aresetn",
+ "axi4stream_spi_master_0/aresetn",
+ "axis_dual_i2s_0/aresetn"
+ ]
+ },
+ "proc_sys_reset_1_peripheral_aresetn": {
+ "ports": [
+ "proc_sys_reset_1/peripheral_aresetn",
+ "axis_dual_i2s_0/i2s_resetn"
+ ]
+ },
+ "axis_dual_i2s_0_tx_lrck": {
+ "ports": [
+ "axis_dual_i2s_0/tx_lrck",
+ "tx_lrck_0"
+ ]
+ },
+ "rx_sdin_0_1": {
+ "ports": [
+ "rx_sdin_0",
+ "axis_dual_i2s_0/rx_sdin"
+ ]
+ },
+ "axis_dual_i2s_0_rx_sclk": {
+ "ports": [
+ "axis_dual_i2s_0/rx_sclk",
+ "rx_sclk_0"
+ ]
+ },
+ "axis_dual_i2s_0_rx_lrck": {
+ "ports": [
+ "axis_dual_i2s_0/rx_lrck",
+ "rx_lrck_0"
+ ]
+ },
+ "axis_dual_i2s_0_rx_mclk": {
+ "ports": [
+ "axis_dual_i2s_0/rx_mclk",
+ "rx_mclk_0"
+ ]
+ },
+ "axis_dual_i2s_0_tx_sdout": {
+ "ports": [
+ "axis_dual_i2s_0/tx_sdout",
+ "tx_sdout_0"
+ ]
+ },
+ "axis_dual_i2s_0_tx_sclk": {
+ "ports": [
+ "axis_dual_i2s_0/tx_sclk",
+ "tx_sclk_0"
+ ]
+ },
+ "axis_dual_i2s_0_tx_mclk": {
+ "ports": [
+ "axis_dual_i2s_0/tx_mclk",
+ "tx_mclk_0"
+ ]
+ },
+ "digilent_jstk2_0_btn_trigger": {
+ "ports": [
+ "digilent_jstk2_0/btn_trigger",
+ "edge_detector_toggle_0/input_signal"
+ ]
+ },
+ "digilent_jstk2_0_btn_jstk": {
+ "ports": [
+ "digilent_jstk2_0/btn_jstk",
+ "edge_detector_toggle_1/input_signal"
+ ]
+ },
+ "edge_detector_toggle_0_output_signal": {
+ "ports": [
+ "edge_detector_toggle_0/output_signal",
+ "led_controller_0/mute_enable",
+ "mute_controller_0/mute"
+ ]
+ },
+ "edge_detector_toggle_1_output_signal": {
+ "ports": [
+ "edge_detector_toggle_1/output_signal",
+ "moving_average_filte_0/enable_filter",
+ "led_controller_0/filter_enable"
+ ]
+ },
+ "led_controller_0_led_r": {
+ "ports": [
+ "led_controller_0/led_r",
+ "digilent_jstk2_0/led_r"
+ ]
+ },
+ "led_controller_0_led_g": {
+ "ports": [
+ "led_controller_0/led_g",
+ "digilent_jstk2_0/led_g"
+ ]
+ },
+ "led_controller_0_led_b": {
+ "ports": [
+ "led_controller_0/led_b",
+ "digilent_jstk2_0/led_b"
+ ]
+ },
+ "Net": {
+ "ports": [
+ "proc_sys_reset_0/peripheral_reset",
+ "edge_detector_toggle_1/reset",
+ "edge_detector_toggle_0/reset"
+ ]
+ },
+ "digilent_jstk2_0_jstk_x": {
+ "ports": [
+ "digilent_jstk2_0/jstk_x",
+ "effect_selector_0/jstck_x"
+ ]
+ },
+ "effect_selector_0_volume": {
+ "ports": [
+ "effect_selector_0/volume",
+ "volume_controller_0/volume"
+ ]
+ },
+ "effect_selector_0_balance": {
+ "ports": [
+ "effect_selector_0/balance",
+ "balance_controller_0/balance"
+ ]
+ },
+ "digilent_jstk2_0_jstk_y": {
+ "ports": [
+ "digilent_jstk2_0/jstk_y",
+ "effect_selector_0/jstck_y"
+ ]
+ },
+ "effect_selector_0_lfo_period": {
+ "ports": [
+ "effect_selector_0/lfo_period",
+ "LFO_0/lfo_period"
+ ]
+ },
+ "lfo_enable_0_1": {
+ "ports": [
+ "lfo_enable",
+ "LFO_0/lfo_enable"
+ ]
+ },
+ "effect_1": {
+ "ports": [
+ "effect",
+ "debouncer_0/input_signal"
+ ]
+ },
+ "led_level_controller_0_led": {
+ "ports": [
+ "led_level_controller_0/led",
+ "LED"
+ ]
+ },
+ "debouncer_0_debounced": {
+ "ports": [
+ "debouncer_0/debounced",
+ "effect_selector_0/effect"
+ ]
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/LAB3/design/lab_3/lab_3.bda b/LAB3/design/lab_3/lab_3.bda
new file mode 100644
index 0000000..3fa1797
--- /dev/null
+++ b/LAB3/design/lab_3/lab_3.bda
@@ -0,0 +1,42 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2
+ lab_3
+ VR
+
+
+ active
+ 2
+ PM
+
+
+ lab_3
+ BC
+
+
+
+
+
+
+
diff --git a/LAB3/ip/axi4-stream-dual-i2s/component.xml b/LAB3/ip/axi4-stream-dual-i2s/component.xml
new file mode 100644
index 0000000..25de804
--- /dev/null
+++ b/LAB3/ip/axi4-stream-dual-i2s/component.xml
@@ -0,0 +1,685 @@
+
+
+ DigiLAB
+ ip
+ axis_dual_i2s
+ 1.0
+
+
+ m_axis
+
+
+
+
+
+
+ TDATA
+
+
+ m_axis_tdata
+
+
+
+
+ TLAST
+
+
+ m_axis_tlast
+
+
+
+
+ TVALID
+
+
+ m_axis_tvalid
+
+
+
+
+ TREADY
+
+
+ m_axis_tready
+
+
+
+
+
+ s_axis
+
+
+
+
+
+
+ TDATA
+
+
+ s_axis_tdata
+
+
+
+
+ TLAST
+
+
+ s_axis_tlast
+
+
+
+
+ TVALID
+
+
+ s_axis_tvalid
+
+
+
+
+ TREADY
+
+
+ s_axis_tready
+
+
+
+
+
+ aresetn
+
+
+
+
+
+
+ RST
+
+
+ aresetn
+
+
+
+
+
+ POLARITY
+ ACTIVE_LOW
+
+
+
+
+ i2s_resetn
+
+
+
+
+
+
+ RST
+
+
+ i2s_resetn
+
+
+
+
+
+ POLARITY
+ ACTIVE_LOW
+
+
+
+
+ aclk
+
+
+
+
+
+
+ CLK
+
+
+ aclk
+
+
+
+
+
+ ASSOCIATED_BUSIF
+ m_axis:s_axis
+
+
+ ASSOCIATED_RESET
+ aresetn
+
+
+
+
+ i2s_clk
+
+
+
+
+
+
+ CLK
+
+
+ i2s_clk
+
+
+
+
+
+ ASSOCIATED_RESET
+ i2s_resetn
+
+
+
+
+
+
+
+ xilinx_anylanguagesynthesis
+ Synthesis
+ :vivado.xilinx.com:synthesis
+ Verilog
+ axis_i2s_wrapper
+
+ xilinx_anylanguagesynthesis_view_fileset
+
+
+
+ viewChecksum
+ 4daa8100
+
+
+
+
+ xilinx_anylanguagebehavioralsimulation
+ Simulation
+ :vivado.xilinx.com:simulation
+ Verilog
+ axis_i2s_wrapper
+
+ xilinx_anylanguagebehavioralsimulation_view_fileset
+
+
+
+ viewChecksum
+ 4daa8100
+
+
+
+
+ xilinx_xpgui
+ UI Layout
+ :vivado.xilinx.com:xgui.ui
+
+ xilinx_xpgui_view_fileset
+
+
+
+ viewChecksum
+ f6c69e0f
+
+
+
+
+
+
+ i2s_clk
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ i2s_resetn
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ aclk
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ aresetn
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_axis_tdata
+
+ in
+
+ 23
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+ 0
+
+
+
+
+ s_axis_tvalid
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_axis_tready
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_axis_tlast
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+ 0
+
+
+
+
+ m_axis_tdata
+
+ out
+
+ 23
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ m_axis_tvalid
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ m_axis_tready
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+ 1
+
+
+
+
+ m_axis_tlast
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ tx_mclk
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ tx_lrck
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ tx_sclk
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ tx_sdout
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ rx_mclk
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ rx_lrck
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ rx_sclk
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ rx_sdin
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+
+
+
+ choice_list_9d8b0d81
+ ACTIVE_HIGH
+ ACTIVE_LOW
+
+
+
+
+ xilinx_anylanguagesynthesis_view_fileset
+
+ hdl/axis_dual_i2s.v
+ verilogSource
+
+
+ hdl/axis_dual_i2s_wrapper.v
+ verilogSource
+ CHECKSUM_f786a01c
+
+
+
+ xilinx_anylanguagebehavioralsimulation_view_fileset
+
+ hdl/axis_dual_i2s.v
+ verilogSource
+
+
+ hdl/axis_dual_i2s_wrapper.v
+ verilogSource
+
+
+
+ xilinx_xpgui_view_fileset
+
+ xgui/axis_dual_i2s_v1_0.tcl
+ tclSource
+ CHECKSUM_f6c69e0f
+ XGUI_VERSION_2
+
+
+
+ AXI4-Stream to Dual I2S
+
+
+ Component_Name
+ axis_i2s_wrapper_v1_0
+
+
+
+
+
+ virtex7
+ qvirtex7
+ versal
+ kintex7
+ kintex7l
+ qkintex7
+ qkintex7l
+ akintex7
+ artix7
+ artix7l
+ aartix7
+ qartix7
+ zynq
+ qzynq
+ azynq
+ spartan7
+ aspartan7
+ virtexuplus
+ virtexuplusHBM
+ kintexuplus
+ zynquplus
+ kintexu
+
+
+ /Communication_&_Networking/Serial_Interfaces
+
+ AXI4-Stream to Dual I2S
+ package_project
+
+ XPM_FIFO
+
+ 3
+
+ user.org:user:axis_i2s_wrapper:1.0
+
+ 2022-05-09T16:06:21Z
+
+
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+ /home/nicola/Documents/Vivado/IPs_DESD/ip_repo/axi4-stream-dual-i2s
+
+
+
+ 2020.2
+
+
+
+
+
+
+
diff --git a/LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s.v b/LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s.v
new file mode 100644
index 0000000..f9605eb
--- /dev/null
+++ b/LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s.v
@@ -0,0 +1,159 @@
+`timescale 1ns / 1ps
+`default_nettype none
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Digilent & Politecnico di Milano
+// Engineer: Arthur Brown, Nicola Corna, Fabio Garzetti, Nicola Lusardi
+//
+// Create Date: 14/05/2019
+// Module Name: axis_i2s
+// Description: AXI-Stream I2S controller
+// Generates clocks and select signals required to place each of the ICs on the Pmod I2S2 into slave mode.
+// Data is 24-bit, shifted one serial clock right from the LRCK boundaries.
+// This module only supports 44.1KHz sample rate, and expects the frequency of axis_clk to be approx 22.591MHz.
+// At the end of each I2S frame, a 2-word packet is made available on the AXIS master interface. Further packets will be discarded
+// until the current packet is accepted by an AXIS slave.
+// Whenever a 2-word packet is received on the AXIS slave interface, it is transmitted over the I2S interface on the next frame.
+// Each packet consists of two 3-byte words, starting with left audio channel data, followed by right channel data.
+//
+// Revision:
+// Revision 0.01 - File Created
+// Revision 0.02 - Use 24-bit interfaces
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module axis_dual_i2s (
+ input wire axis_clk, // require: approx 22.591MHz
+ input wire axis_resetn,
+
+ input wire [23:0] tx_axis_s_data,
+ input wire tx_axis_s_valid,
+ output reg tx_axis_s_ready = 1'b0,
+ input wire tx_axis_s_last,
+
+ output wire [23:0] rx_axis_m_data,
+ output reg rx_axis_m_valid = 1'b0,
+ input wire rx_axis_m_ready,
+ output reg rx_axis_m_last = 1'b0,
+
+ output wire tx_mclk,
+ output wire tx_lrck,
+ output wire tx_sclk,
+ output reg tx_sdout,
+ output wire rx_mclk,
+ output wire rx_lrck,
+ output wire rx_sclk,
+ input wire rx_sdin
+);
+ reg [8:0] count = 9'd0;
+ localparam EOF_COUNT = 9'd455; // end of full I2S frame
+
+ always@(posedge axis_clk)
+ count <= count + 1;
+
+ wire lrck = count[8];
+ wire sclk = count[2];
+ wire mclk = axis_clk;
+ assign tx_lrck = lrck;
+ assign tx_sclk = sclk;
+ assign tx_mclk = mclk;
+ assign rx_lrck = lrck;
+ assign rx_sclk = sclk;
+ assign rx_mclk = mclk;
+
+ /* AXIS SLAVE CONTROLLER */
+ reg [23:0] tx_data_l = 0;
+ reg [23:0] tx_data_r = 0;
+
+ always@(posedge axis_clk)
+ if (axis_resetn == 1'b0)
+ tx_axis_s_ready <= 1'b0;
+ else if (tx_axis_s_ready == 1'b1 && tx_axis_s_valid == 1'b1 && tx_axis_s_last == 1'b1) // end of packet, cannot accept data until current one has been transmitted
+ tx_axis_s_ready <= 1'b0;
+ else if (count == 9'b0) // beginning of I2S frame, in order to avoid tearing, cannot accept data until frame complete
+ tx_axis_s_ready <= 1'b0;
+ else if (count == EOF_COUNT) // end of I2S frame, can accept data
+ tx_axis_s_ready <= 1'b1;
+
+ always@(posedge axis_clk)
+ if (axis_resetn == 1'b0) begin
+ tx_data_r <= 24'b0;
+ tx_data_l <= 24'b0;
+ end else if (tx_axis_s_valid == 1'b1 && tx_axis_s_ready == 1'b1)
+ if (tx_axis_s_last == 1'b1)
+ tx_data_r <= tx_axis_s_data;
+ else
+ tx_data_l <= tx_axis_s_data;
+
+ /* I2S TRANSMIT SHIFT REGISTERS */
+ reg [23:0] tx_data_l_shift = 24'b0;
+ reg [23:0] tx_data_r_shift = 24'b0;
+
+ always@(posedge axis_clk)
+ if (count == 3'b000000111) begin
+ tx_data_l_shift <= tx_data_l[23:0];
+ tx_data_r_shift <= tx_data_r[23:0];
+ end else if (count[2:0] == 3'b111 && count[7:3] >= 5'd1 && count[7:3] <= 5'd24) begin
+ if (count[8] == 1'b1)
+ tx_data_r_shift <= {tx_data_r_shift[22:0], 1'b0};
+ else
+ tx_data_l_shift <= {tx_data_l_shift[22:0], 1'b0};
+ end
+
+ always@(count, tx_data_l_shift, tx_data_r_shift)
+ if (count[7:3] <= 5'd24 && count[7:3] >= 4'd1)
+ if (count[8] == 1'b1)
+ tx_sdout = tx_data_r_shift[23];
+ else
+ tx_sdout = tx_data_l_shift[23];
+ else
+ tx_sdout = 1'b0;
+
+ /* SYNCHRONIZE DATA IN TO AXIS CLOCK DOMAIN */
+ reg [2:0] din_sync_shift = 3'd0;
+ wire din_sync = din_sync_shift[2];
+ always@(posedge axis_clk)
+ din_sync_shift <= {din_sync_shift[1:0], rx_sdin};
+
+ /* I2S RECEIVE SHIFT REGISTERS */
+ reg [23:0] rx_data_l_shift = 24'b0;
+ reg [23:0] rx_data_r_shift = 24'b0;
+ always@(posedge axis_clk)
+ if (count[2:0] == 3'b011 && count[7:3] <= 5'd24 && count[7:3] >= 5'd1)
+ if (lrck == 1'b1)
+ rx_data_r_shift <= {rx_data_r_shift, din_sync};
+ else
+ rx_data_l_shift <= {rx_data_l_shift, din_sync};
+
+ /* AXIS MASTER CONTROLLER */
+ reg [23:0] rx_data_l = 24'b0;
+ reg [23:0] rx_data_r = 24'b0;
+ always@(posedge axis_clk)
+ if (axis_resetn == 1'b0) begin
+ rx_data_l <= 24'b0;
+ rx_data_r <= 24'b0;
+ end else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0) begin
+ rx_data_l <= {8'b0, rx_data_l_shift};
+ rx_data_r <= {8'b0, rx_data_r_shift};
+ end
+
+ assign rx_axis_m_data = (rx_axis_m_last == 1'b1) ? rx_data_r : rx_data_l;
+
+ always@(posedge axis_clk)
+ if (axis_resetn == 1'b0)
+ rx_axis_m_valid <= 1'b0;
+ else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0)
+ rx_axis_m_valid <= 1'b1;
+ else if (rx_axis_m_valid == 1'b1 && rx_axis_m_ready == 1'b1 && rx_axis_m_last == 1'b1)
+ rx_axis_m_valid <= 1'b0;
+
+ always@(posedge axis_clk)
+ if (axis_resetn == 1'b0)
+ rx_axis_m_last <= 1'b0;
+ else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0)
+ rx_axis_m_last <= 1'b0;
+ else if (rx_axis_m_valid == 1'b1 && rx_axis_m_ready == 1'b1)
+ rx_axis_m_last <= ~rx_axis_m_last;
+
+
+endmodule
diff --git a/LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s_wrapper.v b/LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s_wrapper.v
new file mode 100644
index 0000000..8647cfd
--- /dev/null
+++ b/LAB3/ip/axi4-stream-dual-i2s/hdl/axis_dual_i2s_wrapper.v
@@ -0,0 +1,175 @@
+`timescale 1ns / 1ps
+`default_nettype none
+
+module axis_i2s_wrapper (
+ input wire i2s_clk, // require: approx 22.591MHz
+ input wire i2s_resetn,
+
+ input wire aclk,
+ input wire aresetn,
+
+ input wire [23:0] s_axis_tdata,
+ input wire s_axis_tvalid,
+ output wire s_axis_tready,
+ input wire s_axis_tlast,
+
+ output wire [23:0] m_axis_tdata,
+ output wire m_axis_tvalid,
+ input wire m_axis_tready,
+ output wire m_axis_tlast,
+
+ output wire tx_mclk,
+ output wire tx_lrck,
+ output wire tx_sclk,
+ output wire tx_sdout,
+ output wire rx_mclk,
+ output wire rx_lrck,
+ output wire rx_sclk,
+ input wire rx_sdin
+);
+
+wire [23:0] tx_axis_s_data;
+wire tx_axis_s_valid;
+wire tx_axis_s_ready;
+wire tx_axis_s_last;
+
+wire [23:0] rx_axis_m_data;
+wire rx_axis_m_valid;
+wire rx_axis_m_ready;
+wire rx_axis_m_last;
+
+xpm_fifo_axis #(
+ .CDC_SYNC_STAGES(2),
+ .CLOCKING_MODE("independent_clock"),
+ .ECC_MODE("no_ecc"),
+ .FIFO_DEPTH(1024),
+ .FIFO_MEMORY_TYPE("auto"),
+ .PACKET_FIFO("false"),
+ .PROG_EMPTY_THRESH(10),
+ .PROG_FULL_THRESH(10),
+ .RD_DATA_COUNT_WIDTH(1),
+ .RELATED_CLOCKS(0),
+ .SIM_ASSERT_CHK(1),
+ .TDATA_WIDTH(24),
+ .TDEST_WIDTH(1),
+ .TID_WIDTH(1),
+ .TUSER_WIDTH(1),
+ .USE_ADV_FEATURES("0000"),
+ .WR_DATA_COUNT_WIDTH(1)
+)
+rx_fifo (
+ .s_aclk(aclk),
+ .s_aresetn(aresetn),
+ .s_axis_tvalid(s_axis_tvalid),
+ .s_axis_tready(s_axis_tready),
+ .s_axis_tdata(s_axis_tdata),
+ .s_axis_tlast(s_axis_tlast),
+ .s_axis_tdest(1'b0),
+ .s_axis_tid(1'b0),
+ .s_axis_tkeep(1'b111),
+ .s_axis_tstrb(1'b111),
+ .s_axis_tuser(1'b0),
+
+ .m_aclk(i2s_clk),
+ .m_axis_tvalid(tx_axis_s_valid),
+ .m_axis_tready(tx_axis_s_ready),
+ .m_axis_tdata(tx_axis_s_data),
+ .m_axis_tlast(tx_axis_s_last),
+ .m_axis_tdest(),
+ .m_axis_tid(),
+ .m_axis_tkeep(),
+ .m_axis_tstrb(),
+ .m_axis_tuser(),
+
+ .almost_empty_axis(),
+ .almost_full_axis(),
+ .dbiterr_axis(),
+ .prog_empty_axis(),
+ .prog_full_axis(),
+ .rd_data_count_axis(),
+ .sbiterr_axis(),
+ .wr_data_count_axis(),
+ .injectdbiterr_axis(1'b0),
+ .injectsbiterr_axis(1'b0)
+);
+
+axis_dual_i2s axis_dual_i2s_inst (
+ .axis_clk(i2s_clk),
+ .axis_resetn(i2s_resetn),
+
+ .tx_axis_s_data(tx_axis_s_data),
+ .tx_axis_s_valid(tx_axis_s_valid),
+ .tx_axis_s_ready(tx_axis_s_ready),
+ .tx_axis_s_last(tx_axis_s_last),
+
+ .rx_axis_m_data(rx_axis_m_data),
+ .rx_axis_m_valid(rx_axis_m_valid),
+ .rx_axis_m_ready(rx_axis_m_ready),
+ .rx_axis_m_last(rx_axis_m_last),
+
+ .tx_mclk(tx_mclk),
+ .tx_lrck(tx_lrck),
+ .tx_sclk(tx_sclk),
+ .tx_sdout(tx_sdout),
+ .rx_mclk(rx_mclk),
+ .rx_lrck(rx_lrck),
+ .rx_sclk(rx_sclk),
+ .rx_sdin(rx_sdin)
+);
+
+xpm_fifo_axis #(
+ .CDC_SYNC_STAGES(2),
+ .CLOCKING_MODE("independent_clock"),
+ .ECC_MODE("no_ecc"),
+ .FIFO_DEPTH(1024),
+ .FIFO_MEMORY_TYPE("auto"),
+ .PACKET_FIFO("false"),
+ .PROG_EMPTY_THRESH(10),
+ .PROG_FULL_THRESH(10),
+ .RD_DATA_COUNT_WIDTH(1),
+ .RELATED_CLOCKS(0),
+ .SIM_ASSERT_CHK(1),
+ .TDATA_WIDTH(24),
+ .TDEST_WIDTH(1),
+ .TID_WIDTH(1),
+ .TUSER_WIDTH(1),
+ .USE_ADV_FEATURES("0000"),
+ .WR_DATA_COUNT_WIDTH(1)
+)
+tx_fifo (
+ .s_aclk(i2s_clk),
+ .s_aresetn(i2s_resetn),
+ .s_axis_tvalid(rx_axis_m_valid),
+ .s_axis_tready(rx_axis_m_ready),
+ .s_axis_tdata(rx_axis_m_data),
+ .s_axis_tlast(rx_axis_m_last),
+ .s_axis_tdest(1'b0),
+ .s_axis_tid(1'b0),
+ .s_axis_tkeep(1'b111),
+ .s_axis_tstrb(1'b111),
+ .s_axis_tuser(1'b0),
+
+ .m_aclk(aclk),
+ .m_axis_tvalid(m_axis_tvalid),
+ .m_axis_tready(m_axis_tready),
+ .m_axis_tdata(m_axis_tdata),
+ .m_axis_tlast(m_axis_tlast),
+ .m_axis_tdest(),
+ .m_axis_tid(),
+ .m_axis_tkeep(),
+ .m_axis_tstrb(),
+ .m_axis_tuser(),
+
+ .almost_empty_axis(),
+ .almost_full_axis(),
+ .dbiterr_axis(),
+ .prog_empty_axis(),
+ .prog_full_axis(),
+ .rd_data_count_axis(),
+ .sbiterr_axis(),
+ .wr_data_count_axis(),
+ .injectdbiterr_axis(1'b0),
+ .injectsbiterr_axis(1'b0)
+);
+
+endmodule
diff --git a/LAB3/ip/axi4-stream-dual-i2s/xgui/axis_dual_i2s_v1_0.tcl b/LAB3/ip/axi4-stream-dual-i2s/xgui/axis_dual_i2s_v1_0.tcl
new file mode 100644
index 0000000..bf8ae02
--- /dev/null
+++ b/LAB3/ip/axi4-stream-dual-i2s/xgui/axis_dual_i2s_v1_0.tcl
@@ -0,0 +1,12 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_static_text $IPINST -name "Warnings" -parent ${Page_0} -text {The jumper on the board MUST BE in position SLV.
+The input clock axis_clk MUST BE 22.591 MHz.}
+
+
+}
+
+
diff --git a/LAB3/ip/axi4-stream-spi-master/README.md b/LAB3/ip/axi4-stream-spi-master/README.md
new file mode 100644
index 0000000..a6eb213
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/README.md
@@ -0,0 +1,35 @@
+# AXI4-Stream SPI Master
+
+This module implements an SPI Master.
+
+This module is based on the "SPI Master Lightweight" module on OpenCores, freely
+downloadable from [here](https://opencores.org/projects/spi_master_lightweight),
+with minimal modifications to add AXI4-Stream interfaces and reset signal.
+
+The cs signal is automatically asserted half clock cycle (SCLK) before the first
+rising edge of SCLK (with CPOL=0 and CPHA=0) and deasserted half clock cycle
+(SCLK) after the last falling edge of SCLK (with CPOL=0 and CPHA=0).
+
+## Generics
+ * c_clkfreq: aclk frequency (in Hz)
+ * c_sclkfreq: desired sclk frequency (in Hz); must be <= c_clkfreq/8
+ * c_cpol: SPI CPOL
+ * c_cpha: SPI CPHA
+
+## Slave AXI4-Stream
+
+Data passed to this module through this interface are serialized and send
+through the MOSI port, MSbit first.
+
+The CS signal will go low at the beginning of the transfer and will stay low
+until this module has data to send. In other words, keep s_axis_tvalid high and
+keep sending data if you want an uninterrupted transfer with CS always low.
+
+## Master AXI4-Stream
+
+Data received by this module will be sent through this interface. Note that this
+interface lacks a tready signal.
+
+For how the SPI protocol works, data can be received only when data is
+transmitted by the master so, if you want to receive N bytes, you have to send
+N bytes (by writing on the Slave AXI4-Stream interface).
diff --git a/LAB3/ip/axi4-stream-spi-master/cocotb/.gitignore b/LAB3/ip/axi4-stream-spi-master/cocotb/.gitignore
new file mode 100644
index 0000000..3eb4d21
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/cocotb/.gitignore
@@ -0,0 +1,130 @@
+# Byte-compiled / optimized / DLL files
+__pycache__/
+*.py[cod]
+*$py.class
+
+# C extensions
+*.so
+
+# Distribution / packaging
+.Python
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+wheels/
+pip-wheel-metadata/
+share/python-wheels/
+*.egg-info/
+.installed.cfg
+*.egg
+MANIFEST
+
+# PyInstaller
+# Usually these files are written by a python script from a template
+# before PyInstaller builds the exe, so as to inject date/other infos into it.
+*.manifest
+*.spec
+
+# Installer logs
+pip-log.txt
+pip-delete-this-directory.txt
+
+# Unit test / coverage reports
+htmlcov/
+.tox/
+.nox/
+.coverage
+.coverage.*
+.cache
+nosetests.xml
+coverage.xml
+*.cover
+.hypothesis/
+.pytest_cache/
+
+# Translations
+*.mo
+*.pot
+
+# Django stuff:
+*.log
+local_settings.py
+db.sqlite3
+db.sqlite3-journal
+
+# Flask stuff:
+instance/
+.webassets-cache
+
+# Scrapy stuff:
+.scrapy
+
+# Sphinx documentation
+docs/_build/
+
+# PyBuilder
+target/
+
+# Jupyter Notebook
+.ipynb_checkpoints
+
+# IPython
+profile_default/
+ipython_config.py
+
+# pyenv
+.python-version
+
+# pipenv
+# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
+# However, in case of collaboration, if having platform-specific dependencies or dependencies
+# having no cross-platform support, pipenv may install dependencies that don't work, or not
+# install all needed dependencies.
+#Pipfile.lock
+
+# celery beat schedule file
+celerybeat-schedule
+
+# SageMath parsed files
+*.sage.py
+
+# Environments
+.env
+.venv
+env/
+venv/
+ENV/
+env.bak/
+venv.bak/
+
+# Spyder project settings
+.spyderproject
+.spyproject
+
+# Rope project settings
+.ropeproject
+
+# mkdocs documentation
+/site
+
+# mypy
+.mypy_cache/
+.dmypy.json
+dmypy.json
+
+# Pyre type checker
+.pyre/
+
+# Cocotb build folder
+build/
+
+# Cocotb results
+results.xml
diff --git a/LAB3/ip/axi4-stream-spi-master/cocotb/Makefile b/LAB3/ip/axi4-stream-spi-master/cocotb/Makefile
new file mode 100644
index 0000000..934de38
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/cocotb/Makefile
@@ -0,0 +1,20 @@
+export PYTHON_BIN=python3
+
+PWD := $(shell pwd)
+
+SIM ?= ghdl
+SIM_ARGS ?= --wave=$(PWD)/build/waveform.ghw -gc_clkfreq=100000000 -gc_sclkfreq=10000000
+GHDL_ARGS ?= -fsynopsys
+
+TOPLEVEL_LANG = vhdl
+
+SIM_BUILD = $(PWD)/build
+MODULE = tester_axis_lw_spi_master
+TOPLEVEL = axis_lw_spi_master
+
+HDL_DIR = $(PWD)/../hdl
+VHDL_SOURCES = \
+ $(HDL_DIR)/spi_master_lightweight/rtl/lw_spi_master.vhd \
+ $(HDL_DIR)/axis_lw_spi_master.vhd
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/LAB3/ip/axi4-stream-spi-master/cocotb/tester_axis_lw_spi_master.py b/LAB3/ip/axi4-stream-spi-master/cocotb/tester_axis_lw_spi_master.py
new file mode 100644
index 0000000..031fbc1
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/cocotb/tester_axis_lw_spi_master.py
@@ -0,0 +1,82 @@
+#!/usr/bin/env python3
+
+import secrets
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, ClockCycles
+from cocotbext.axi4stream.drivers import Axi4StreamMaster
+from cocotbext.axi4stream.monitors import Axi4Stream
+from cocotbext.spi import SpiSlaveBase, SpiSignals, SpiConfig
+
+CLK_PERIOD = 10
+
+
+class SimpleSpiSlave(SpiSlaveBase):
+ def __init__(self, signals, config, data):
+ self._config = config
+ self.content = 0
+ self.data = data
+ super().__init__(signals)
+
+ async def get_content(self):
+ await self.idle.wait()
+ return self.content
+
+ async def _transaction(self, frame_start, frame_end):
+ await frame_start
+ self.idle.clear()
+
+ self._miso.value = 1 if self.data[0] & 0x80 else 0
+ self.content = int(await self._shift(len(self.data) * 8 - 1, tx_word=int.from_bytes(self.data, 'big')))
+ await RisingEdge(self._sclk)
+ self.content = self.content << 1 | int(self._mosi.value.integer)
+
+ await frame_end
+
+
+async def setup_dut(dut):
+ cocotb.fork(Clock(dut.aclk, CLK_PERIOD, "ns").start())
+
+
+@cocotb.test()
+async def test_spi(dut, length=32):
+ """TODO"""
+
+ spi_signals = SpiSignals(
+ sclk = dut.sclk,
+ mosi = dut.mosi,
+ miso = dut.miso,
+ cs = dut.cs
+ )
+
+ spi_config = SpiConfig(
+ word_width = 8,
+ cpol = False,
+ cpha = False,
+ data_output_idle = 0,
+ msb_first = True
+ )
+
+ mosi_tx = secrets.randbits(length * 8).to_bytes(length, 'little')
+ miso_tx = secrets.randbits(length * 8).to_bytes(length, 'little')
+ spi_slave = SimpleSpiSlave(spi_signals, spi_config, miso_tx)
+
+ miso_rx = bytearray()
+
+ axis_m = Axi4StreamMaster(dut, "s_axis", dut.aclk)
+ axis_monitor = Axi4Stream(dut, "m_axis", dut.aclk, packets=False)
+ axis_monitor.add_callback(lambda data: miso_rx.extend(data))
+
+ await setup_dut(dut)
+ await ClockCycles(dut.aclk, 10)
+
+ await axis_m.write([b for b in mosi_tx])
+
+ mosi_rx = (await spi_slave.get_content()).to_bytes(length, 'big')
+
+ await ClockCycles(dut.aclk, 10)
+
+ assert mosi_tx == mosi_rx, "Received MOSI data does not match transmitted one"
+ assert miso_tx == miso_rx, "Received MISO data does not match transmitted one"
+
diff --git a/LAB3/ip/axi4-stream-spi-master/cocotb/waveforms.gtkw b/LAB3/ip/axi4-stream-spi-master/cocotb/waveforms.gtkw
new file mode 100644
index 0000000..3d9b2c1
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/cocotb/waveforms.gtkw
@@ -0,0 +1,53 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Fri Mar 25 16:24:27 2022
+[*]
+[dumpfile] "/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master/sim/build/waveform.ghw"
+[dumpfile_mtime] "Fri Mar 25 16:23:35 2022"
+[dumpfile_size] 3066
+[savefile] "/home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master/sim/waveforms.gtkw"
+[timestart] 0
+[size] 1920 1001
+[pos] -27 -24
+*-27.176317 7190000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.axis_lw_spi_master.
+[treeopen] top.axis_lw_spi_master.inst_lw_spi_master.
+[sst_width] 281
+[signals_width] 200
+[sst_expanded] 1
+[sst_vpaned_height] 285
+@28
+top.axis_lw_spi_master.clk
+@200
+-
+@28
+top.axis_lw_spi_master.s_axis_tvalid
+top.axis_lw_spi_master.s_axis_tready
+@22
+#{top.axis_lw_spi_master.s_axis_tdata[7:0]} top.axis_lw_spi_master.s_axis_tdata[7] top.axis_lw_spi_master.s_axis_tdata[6] top.axis_lw_spi_master.s_axis_tdata[5] top.axis_lw_spi_master.s_axis_tdata[4] top.axis_lw_spi_master.s_axis_tdata[3] top.axis_lw_spi_master.s_axis_tdata[2] top.axis_lw_spi_master.s_axis_tdata[1] top.axis_lw_spi_master.s_axis_tdata[0]
+@200
+-
+@28
+top.axis_lw_spi_master.m_axis_tvalid
+@22
+#{top.axis_lw_spi_master.m_axis_tdata[7:0]} top.axis_lw_spi_master.m_axis_tdata[7] top.axis_lw_spi_master.m_axis_tdata[6] top.axis_lw_spi_master.m_axis_tdata[5] top.axis_lw_spi_master.m_axis_tdata[4] top.axis_lw_spi_master.m_axis_tdata[3] top.axis_lw_spi_master.m_axis_tdata[2] top.axis_lw_spi_master.m_axis_tdata[1] top.axis_lw_spi_master.m_axis_tdata[0]
+@200
+-
+@28
+top.axis_lw_spi_master.inst_lw_spi_master.en_i
+@22
+#{top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[7:0]} top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[7] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[6] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[5] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[4] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[3] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[2] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[1] top.axis_lw_spi_master.inst_lw_spi_master.mosi_data_i[0]
+#{top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[7:0]} top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[7] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[6] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[5] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[4] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[3] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[2] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[1] top.axis_lw_spi_master.inst_lw_spi_master.miso_data_o[0]
+@28
+top.axis_lw_spi_master.inst_lw_spi_master.data_ready_o
+@200
+-
+@28
+top.axis_lw_spi_master.sclk
+top.axis_lw_spi_master.mosi
+top.axis_lw_spi_master.miso
+@29
+top.axis_lw_spi_master.cs
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/LAB3/ip/axi4-stream-spi-master/component.xml b/LAB3/ip/axi4-stream-spi-master/component.xml
new file mode 100644
index 0000000..653ba5f
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/component.xml
@@ -0,0 +1,761 @@
+
+
+ DigiLAB
+ ip
+ axi4stream_spi_master
+ 1.0
+
+
+ aclk
+
+
+
+
+
+
+ CLK
+
+
+ aclk
+
+
+
+
+
+ ASSOCIATED_BUSIF
+ S_AXIS:M_AXIS
+
+
+ ASSOCIATED_RESET
+
+
+
+
+
+ SPI_M
+
+
+
+
+
+
+ SCK_T
+
+
+ sclk_t
+
+
+
+
+ IO1_O
+
+
+ miso_o
+
+
+
+
+ SS_T
+
+
+ cs_t
+
+
+
+
+ IO0_O
+
+
+ mosi_o
+
+
+
+
+ SCK_I
+
+
+ sclk_i
+
+
+
+
+ SS_O
+
+
+ cs_o
+
+
+
+
+ IO0_T
+
+
+ mosi_t
+
+
+
+
+ IO1_T
+
+
+ miso_t
+
+
+
+
+ SCK_O
+
+
+ sclk_o
+
+
+
+
+ SS_I
+
+
+ cs_i
+
+
+
+
+ IO1_I
+
+
+ miso_i
+
+
+
+
+ IO0_I
+
+
+ mosi_i
+
+
+
+
+
+ S_AXIS
+
+
+
+
+
+
+ TDATA
+
+
+ s_axis_tdata
+
+
+
+
+ TVALID
+
+
+ s_axis_tvalid
+
+
+
+
+ TREADY
+
+
+ s_axis_tready
+
+
+
+
+
+ M_AXIS
+
+
+
+
+
+
+ TDATA
+
+
+ m_axis_tdata
+
+
+
+
+ TVALID
+
+
+ m_axis_tvalid
+
+
+
+
+
+ aresetn
+
+
+
+
+
+
+ RST
+
+
+ aresetn
+
+
+
+
+
+ POLARITY
+ ACTIVE_LOW
+
+
+
+
+
+
+
+ xilinx_anylanguagesynthesis
+ Synthesis
+ :vivado.xilinx.com:synthesis
+ VHDL
+ ipi_axis_lw_spi_master
+
+ xilinx_anylanguagesynthesis_view_fileset
+
+
+
+ viewChecksum
+ 4adf0ae8
+
+
+
+
+ xilinx_anylanguagebehavioralsimulation
+ Simulation
+ :vivado.xilinx.com:simulation
+ VHDL
+ ipi_axis_lw_spi_master
+
+ xilinx_anylanguagebehavioralsimulation_view_fileset
+
+
+
+ viewChecksum
+ 4adf0ae8
+
+
+
+
+ xilinx_xpgui
+ UI Layout
+ :vivado.xilinx.com:xgui.ui
+
+ xilinx_xpgui_view_fileset
+
+
+
+ viewChecksum
+ 30ce0f94
+
+
+
+
+
+
+ aclk
+
+ in
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ aresetn
+
+ in
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_axis_tvalid
+
+ in
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_axis_tdata
+
+ in
+
+ 7
+ 0
+
+
+
+ STD_LOGIC_VECTOR
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+ 0
+
+
+
+
+ s_axis_tready
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ m_axis_tvalid
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ m_axis_tdata
+
+ out
+
+ 7
+ 0
+
+
+
+ STD_LOGIC_VECTOR
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ cs_i
+
+ in
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ cs_o
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ cs_t
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ sclk_i
+
+ in
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ sclk_o
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ sclk_t
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ mosi_i
+
+ in
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ mosi_o
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ mosi_t
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ miso_i
+
+ in
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ miso_o
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ miso_t
+
+ out
+
+
+ STD_LOGIC
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+
+
+ c_clkfreq
+ C Clkfreq
+ 100000000
+
+
+ c_sclkfreq
+ C Sclkfreq
+ 1000000
+
+
+ c_cpol
+ C Cpol
+ 0
+
+
+ c_cpha
+ C Cpha
+ 0
+
+
+
+
+
+ choice_list_74b5137e
+ ACTIVE_HIGH
+ ACTIVE_LOW
+
+
+ choice_list_8af5a703
+ 0
+ 1
+
+
+
+
+ xilinx_anylanguagesynthesis_view_fileset
+
+ hdl/axis_lw_spi_master.vhd
+ vhdlSource
+
+
+ hdl/spi_master_lightweight/rtl/lw_spi_master.vhd
+ vhdlSource
+
+
+ hdl/ipi_axis_lw_spi_master.vhd
+ vhdlSource
+ CHECKSUM_009490da
+
+
+
+ xilinx_anylanguagebehavioralsimulation_view_fileset
+
+ hdl/axis_lw_spi_master.vhd
+ vhdlSource
+
+
+ hdl/spi_master_lightweight/rtl/lw_spi_master.vhd
+ vhdlSource
+
+
+ hdl/ipi_axis_lw_spi_master.vhd
+ vhdlSource
+
+
+
+ xilinx_xpgui_view_fileset
+
+ xgui/axi4stream_spi_master_v1_0.tcl
+ tclSource
+ CHECKSUM_30ce0f94
+ XGUI_VERSION_2
+
+
+
+ Lightweight AXI4-Stream SPI Master
+
+
+ c_clkfreq
+ aclk Frequency (Hz)
+ 100000000
+
+
+ c_sclkfreq
+ Desired SCLK frequency
+ 1000000
+
+
+ c_cpol
+ CPOL
+ 0
+
+
+ c_cpha
+ CPHA
+ 0
+
+
+ Component_Name
+ lw_spi_master_v1_0
+
+
+
+
+
+ virtex7
+ qvirtex7
+ versal
+ kintex7
+ kintex7l
+ qkintex7
+ qkintex7l
+ akintex7
+ artix7
+ artix7l
+ aartix7
+ qartix7
+ zynq
+ qzynq
+ azynq
+ spartan7
+ aspartan7
+ virtexuplus
+ virtexuplusHBM
+ kintexuplus
+ zynquplus
+ kintexu
+
+
+ /UserIP
+
+ AXI4-Stream SPI Master
+ package_project
+ 1
+
+ user.org:user:lw_spi_master:1.0
+
+ 2022-03-31T09:18:07Z
+
+
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+ /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master
+
+
+
+ 2020.2
+
+
+
+
+
+
+
+
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/axis_lw_spi_master.vhd b/LAB3/ip/axi4-stream-spi-master/hdl/axis_lw_spi_master.vhd
new file mode 100644
index 0000000..9356da5
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/hdl/axis_lw_spi_master.vhd
@@ -0,0 +1,104 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity axis_lw_spi_master is
+ generic (
+ c_clkfreq : integer := 100_000_000;
+ c_sclkfreq : integer := 1_000_000;
+ c_cpol : std_logic := '0';
+ c_cpha : std_logic := '0'
+ );
+ Port (
+ aclk : in STD_LOGIC;
+ aresetn : in STD_LOGIC;
+
+ s_axis_tvalid : in STD_LOGIC;
+ s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
+ s_axis_tready : out STD_LOGIC;
+
+ m_axis_tvalid : out STD_LOGIC;
+ m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
+
+ cs : out STD_LOGIC;
+ sclk : out STD_LOGIC;
+ mosi : out STD_LOGIC;
+ miso : in STD_LOGIC
+ );
+end axis_lw_spi_master;
+
+architecture Behavioral of axis_lw_spi_master is
+
+ component lw_spi_master is
+ generic (
+ c_clkfreq : integer := 50_000_000;
+ c_sclkfreq : integer := 5_000_000;
+ c_cpol : std_logic := '0';
+ c_cpha : std_logic := '0'
+ );
+ Port (
+ clk_i : in STD_LOGIC;
+ rst_i : in STD_LOGIC;
+ en_i : in STD_LOGIC;
+ mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
+ miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
+ data_ready_o : out STD_LOGIC;
+ cs_o : out STD_LOGIC;
+ sclk_o : out STD_LOGIC;
+ mosi_o : out STD_LOGIC;
+ miso_i : in STD_LOGIC
+ );
+ end component;
+
+ signal rst : std_logic;
+ signal data_ready : std_logic;
+ signal data_ready_reg : std_logic;
+ signal new_data : std_logic;
+
+begin
+
+ inst_lw_spi_master : lw_spi_master
+ generic map (
+ c_clkfreq => c_clkfreq,
+ c_sclkfreq => c_sclkfreq,
+ c_cpol => c_cpol,
+ c_cpha => c_cpha
+ )
+ Port map (
+ clk_i => aclk,
+ rst_i => rst,
+ en_i => s_axis_tvalid,
+ mosi_data_i => s_axis_tdata,
+ miso_data_o => m_axis_tdata,
+ data_ready_o => data_ready,
+ cs_o => cs,
+ sclk_o => sclk,
+ mosi_o => mosi,
+ miso_i => miso
+ );
+
+ rst <= not aresetn;
+ s_axis_tready <= new_data;
+ m_axis_tvalid <= new_data;
+
+ process (aclk)
+ begin
+ if rising_edge(aclk) then
+ if aresetn = '0' then
+
+ new_data <= '0';
+
+ else
+
+ data_ready_reg <= data_ready;
+
+ if data_ready_reg = '0' and data_ready = '1' then
+ new_data <= '1';
+ else
+ new_data <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+end Behavioral;
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/ipi_axis_lw_spi_master.vhd b/LAB3/ip/axi4-stream-spi-master/hdl/ipi_axis_lw_spi_master.vhd
new file mode 100644
index 0000000..6801b4d
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/hdl/ipi_axis_lw_spi_master.vhd
@@ -0,0 +1,103 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity ipi_axis_lw_spi_master is
+ generic (
+ c_clkfreq : integer := 100_000_000;
+ c_sclkfreq : integer := 1_000_000;
+ c_cpol : integer range 0 to 1 := 0;
+ c_cpha : integer range 0 to 1 := 0
+ );
+ Port (
+ aclk : in STD_LOGIC;
+ aresetn : in STD_LOGIC;
+
+ s_axis_tvalid : in STD_LOGIC;
+ s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
+ s_axis_tready : out STD_LOGIC;
+
+ m_axis_tvalid : out STD_LOGIC;
+ m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
+
+ cs_i : in STD_LOGIC;
+ cs_o : out STD_LOGIC;
+ cs_t : out STD_LOGIC;
+
+ sclk_i : in STD_LOGIC;
+ sclk_o : out STD_LOGIC;
+ sclk_t : out STD_LOGIC;
+
+ mosi_i : in STD_LOGIC;
+ mosi_o : out STD_LOGIC;
+ mosi_t : out STD_LOGIC;
+
+ miso_i : in STD_LOGIC;
+ miso_o : out STD_LOGIC;
+ miso_t : out STD_LOGIC
+ );
+end ipi_axis_lw_spi_master;
+
+architecture Behavioral of ipi_axis_lw_spi_master is
+
+ component axis_lw_spi_master is
+ generic (
+ c_clkfreq : integer := 100_000_000;
+ c_sclkfreq : integer := 1_000_000;
+ c_cpol : std_logic := '0';
+ c_cpha : std_logic := '0'
+ );
+ Port (
+ aclk : in STD_LOGIC;
+ aresetn : in STD_LOGIC;
+
+ s_axis_tvalid : in STD_LOGIC;
+ s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
+ s_axis_tready : out STD_LOGIC;
+
+ m_axis_tvalid : out STD_LOGIC;
+ m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
+
+ cs : out STD_LOGIC;
+ sclk : out STD_LOGIC;
+ mosi : out STD_LOGIC;
+ miso : in STD_LOGIC
+ );
+ end component;
+
+ constant C_CPOL_SLV : std_logic_vector := std_logic_vector(to_unsigned(c_cpol, 1));
+ constant C_CPHA_SLV : std_logic_vector := std_logic_vector(to_unsigned(c_cpha, 1));
+
+begin
+
+ inst_axis_lw_spi_master : axis_lw_spi_master
+ generic map (
+ c_clkfreq => c_clkfreq,
+ c_sclkfreq => c_sclkfreq,
+ c_cpol => C_CPOL_SLV(0),
+ c_cpha => C_CPHA_SLV(0)
+ )
+ Port map (
+ aclk => aclk,
+ aresetn => aresetn,
+
+ s_axis_tvalid => s_axis_tvalid,
+ s_axis_tdata => s_axis_tdata,
+ s_axis_tready => s_axis_tready,
+
+ m_axis_tvalid => m_axis_tvalid,
+ m_axis_tdata => m_axis_tdata,
+
+ cs => cs_o,
+ sclk => sclk_o,
+ mosi => mosi_o,
+ miso => miso_i
+ );
+
+ cs_t <= '0';
+ sclk_t <= '0';
+ mosi_t <= '0';
+ miso_t <= '1';
+ miso_o <= '0';
+
+end Behavioral;
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/README.md b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/README.md
new file mode 100644
index 0000000..954e1fb
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/README.md
@@ -0,0 +1,3 @@
+# SPI Master Lightweight
+
+Taken from [OpenCores](https://opencores.org/projects/spi_master_lightweight).
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/doc/Design and Implementation of a Lightweight SPI Master IP for Low Cost FPGAs.pdf b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/doc/Design and Implementation of a Lightweight SPI Master IP for Low Cost FPGAs.pdf
new file mode 100644
index 0000000..acd6c1c
Binary files /dev/null and b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/doc/Design and Implementation of a Lightweight SPI Master IP for Low Cost FPGAs.pdf differ
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/lic/lgpl.txt b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/lic/lgpl.txt
new file mode 100644
index 0000000..bde60ce
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/lic/lgpl.txt
@@ -0,0 +1,165 @@
+GNU LESSER GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+
+ This version of the GNU Lesser General Public License incorporates
+the terms and conditions of version 3 of the GNU General Public
+License, supplemented by the additional permissions listed below.
+
+ 0. Additional Definitions.
+
+ As used herein, "this License" refers to version 3 of the GNU Lesser
+General Public License, and the "GNU GPL" refers to version 3 of the GNU
+General Public License.
+
+ "The Library" refers to a covered work governed by this License,
+other than an Application or a Combined Work as defined below.
+
+ An "Application" is any work that makes use of an interface provided
+by the Library, but which is not otherwise based on the Library.
+Defining a subclass of a class defined by the Library is deemed a mode
+of using an interface provided by the Library.
+
+ A "Combined Work" is a work produced by combining or linking an
+Application with the Library. The particular version of the Library
+with which the Combined Work was made is also called the "Linked
+Version".
+
+ The "Minimal Corresponding Source" for a Combined Work means the
+Corresponding Source for the Combined Work, excluding any source code
+for portions of the Combined Work that, considered in isolation, are
+based on the Application, and not on the Linked Version.
+
+ The "Corresponding Application Code" for a Combined Work means the
+object code and/or source code for the Application, including any data
+and utility programs needed for reproducing the Combined Work from the
+Application, but excluding the System Libraries of the Combined Work.
+
+ 1. Exception to Section 3 of the GNU GPL.
+
+ You may convey a covered work under sections 3 and 4 of this License
+without being bound by section 3 of the GNU GPL.
+
+ 2. Conveying Modified Versions.
+
+ If you modify a copy of the Library, and, in your modifications, a
+facility refers to a function or data to be supplied by an Application
+that uses the facility (other than as an argument passed when the
+facility is invoked), then you may convey a copy of the modified
+version:
+
+ a) under this License, provided that you make a good faith effort to
+ ensure that, in the event an Application does not supply the
+ function or data, the facility still operates, and performs
+ whatever part of its purpose remains meaningful, or
+
+ b) under the GNU GPL, with none of the additional permissions of
+ this License applicable to that copy.
+
+ 3. Object Code Incorporating Material from Library Header Files.
+
+ The object code form of an Application may incorporate material from
+a header file that is part of the Library. You may convey such object
+code under terms of your choice, provided that, if the incorporated
+material is not limited to numerical parameters, data structure
+layouts and accessors, or small macros, inline functions and templates
+(ten or fewer lines in length), you do both of the following:
+
+ a) Give prominent notice with each copy of the object code that the
+ Library is used in it and that the Library and its use are
+ covered by this License.
+
+ b) Accompany the object code with a copy of the GNU GPL and this license
+ document.
+
+ 4. Combined Works.
+
+ You may convey a Combined Work under terms of your choice that,
+taken together, effectively do not restrict modification of the
+portions of the Library contained in the Combined Work and reverse
+engineering for debugging such modifications, if you also do each of
+the following:
+
+ a) Give prominent notice with each copy of the Combined Work that
+ the Library is used in it and that the Library and its use are
+ covered by this License.
+
+ b) Accompany the Combined Work with a copy of the GNU GPL and this license
+ document.
+
+ c) For a Combined Work that displays copyright notices during
+ execution, include the copyright notice for the Library among
+ these notices, as well as a reference directing the user to the
+ copies of the GNU GPL and this license document.
+
+ d) Do one of the following:
+
+ 0) Convey the Minimal Corresponding Source under the terms of this
+ License, and the Corresponding Application Code in a form
+ suitable for, and under terms that permit, the user to
+ recombine or relink the Application with a modified version of
+ the Linked Version to produce a modified Combined Work, in the
+ manner specified by section 6 of the GNU GPL for conveying
+ Corresponding Source.
+
+ 1) Use a suitable shared library mechanism for linking with the
+ Library. A suitable mechanism is one that (a) uses at run time
+ a copy of the Library already present on the user's computer
+ system, and (b) will operate properly with a modified version
+ of the Library that is interface-compatible with the Linked
+ Version.
+
+ e) Provide Installation Information, but only if you would otherwise
+ be required to provide such information under section 6 of the
+ GNU GPL, and only to the extent that such information is
+ necessary to install and execute a modified version of the
+ Combined Work produced by recombining or relinking the
+ Application with a modified version of the Linked Version. (If
+ you use option 4d0, the Installation Information must accompany
+ the Minimal Corresponding Source and Corresponding Application
+ Code. If you use option 4d1, you must provide the Installation
+ Information in the manner specified by section 6 of the GNU GPL
+ for conveying Corresponding Source.)
+
+ 5. Combined Libraries.
+
+ You may place library facilities that are a work based on the
+Library side by side in a single library together with other library
+facilities that are not Applications and are not covered by this
+License, and convey such a combined library under terms of your
+choice, if you do both of the following:
+
+ a) Accompany the combined library with a copy of the same work based
+ on the Library, uncombined with any other library facilities,
+ conveyed under the terms of this License.
+
+ b) Give prominent notice with the combined library that part of it
+ is a work based on the Library, and explaining where to find the
+ accompanying uncombined form of the same work.
+
+ 6. Revised Versions of the GNU Lesser General Public License.
+
+ The Free Software Foundation may publish revised and/or new versions
+of the GNU Lesser General Public License from time to time. Such new
+versions will be similar in spirit to the present version, but may
+differ in detail to address new problems or concerns.
+
+ Each version is given a distinguishing version number. If the
+Library as you received it specifies that a certain numbered version
+of the GNU Lesser General Public License "or any later version"
+applies to it, you have the option of following the terms and
+conditions either of that published version or of any later version
+published by the Free Software Foundation. If the Library as you
+received it does not specify a version number of the GNU Lesser
+General Public License, you may choose any version of the GNU Lesser
+General Public License ever published by the Free Software Foundation.
+
+ If the Library as you received it specifies that a proxy can decide
+whether future versions of the GNU Lesser General Public License shall
+apply, that proxy's public statement of acceptance of any version is
+permanent authorization for you to choose that version for the
+Library.
\ No newline at end of file
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/rtl/lw_spi_master.vhd b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/rtl/lw_spi_master.vhd
new file mode 100644
index 0000000..d6b5a6a
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/rtl/lw_spi_master.vhd
@@ -0,0 +1,263 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity lw_spi_master is
+generic (
+ c_clkfreq : integer := 50_000_000;
+ c_sclkfreq : integer := 5_000_000;
+ c_cpol : std_logic := '0';
+ c_cpha : std_logic := '0'
+);
+Port (
+ clk_i : in STD_LOGIC;
+ rst_i : in STD_LOGIC;
+ en_i : in STD_LOGIC;
+ mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
+ miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
+ data_ready_o : out STD_LOGIC;
+ cs_o : out STD_LOGIC;
+ sclk_o : out STD_LOGIC;
+ mosi_o : out STD_LOGIC;
+ miso_i : in STD_LOGIC
+);
+end lw_spi_master;
+
+architecture Behavioral of lw_spi_master is
+
+signal write_reg : std_logic_vector (7 downto 0) := (others => '0');
+signal read_reg : std_logic_vector (7 downto 0) := (others => '0');
+
+signal sclk_en : std_logic := '0';
+signal sclk : std_logic := '0';
+signal sclk_prev : std_logic := '0';
+signal sclk_rise : std_logic := '0';
+signal sclk_fall : std_logic := '0';
+
+signal pol_phase : std_logic_vector (1 downto 0) := (others => '0');
+signal mosi_en : std_logic := '0';
+signal miso_en : std_logic := '0';
+
+constant c_edgecntrlimdiv2 : integer := c_clkfreq/(c_sclkfreq*2);
+signal edgecntr : integer range 0 to c_edgecntrlimdiv2 := 0;
+
+signal cntr : integer range 0 to 15 := 0;
+
+type states is (S_IDLE, S_TRANSFER);
+signal state : states := S_IDLE;
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+begin
+
+pol_phase <= c_cpol & c_cpha;
+
+P_SAMPLE_EN : process (pol_phase, sclk_fall, sclk_rise) begin
+
+ case pol_phase is
+
+ when "00" =>
+
+ mosi_en <= sclk_fall;
+ miso_en <= sclk_rise;
+
+ when "01" =>
+
+ mosi_en <= sclk_rise;
+ miso_en <= sclk_fall;
+
+ when "10" =>
+
+ mosi_en <= sclk_rise;
+ miso_en <= sclk_fall;
+
+ when "11" =>
+
+ mosi_en <= sclk_fall;
+ miso_en <= sclk_rise;
+
+ when others =>
+
+ end case;
+
+end process;
+
+P_RISEFALL_DETECT : process (sclk, sclk_prev) begin
+
+ if (sclk = '1' and sclk_prev = '0') then
+ sclk_rise <= '1';
+ else
+ sclk_rise <= '0';
+ end if;
+
+ if (sclk = '0' and sclk_prev = '1') then
+ sclk_fall <= '1';
+ else
+ sclk_fall <= '0';
+ end if;
+
+end process;
+
+
+P_MAIN : process (clk_i) begin
+if (rising_edge(clk_i)) then
+
+ if rst_i = '1' then
+
+ cs_o <= '1';
+ mosi_o <= '0';
+ data_ready_o <= '0';
+ sclk_en <= '0';
+
+ else
+ sclk_prev <= sclk;
+
+ case state is
+
+ when S_IDLE =>
+
+ cs_o <= '1';
+ mosi_o <= '0';
+ data_ready_o <= '0';
+ sclk_en <= '0';
+ cntr <= 0;
+
+ if (c_cpol = '0') then
+ sclk_o <= '0';
+ else
+ sclk_o <= '1';
+ end if;
+
+ if (en_i = '1') then
+ state <= S_TRANSFER;
+ sclk_en <= '1';
+ write_reg <= mosi_data_i;
+ mosi_o <= mosi_data_i(7);
+ read_reg <= x"00";
+ end if;
+
+ when S_TRANSFER =>
+
+ cs_o <= '0';
+ mosi_o <= write_reg(7);
+
+
+ if (c_cpha = '1') then
+
+ if (cntr = 0) then
+ sclk_o <= sclk;
+ if (miso_en = '1') then
+ read_reg(0) <= miso_i;
+ read_reg(7 downto 1) <= read_reg(6 downto 0);
+ cntr <= cntr + 1;
+ end if;
+ elsif (cntr = 8) then
+ data_ready_o <= '1';
+ miso_data_o <= read_reg;
+ if (mosi_en = '1') then
+ data_ready_o <= '0';
+ if (en_i = '1') then
+ write_reg <= mosi_data_i;
+ mosi_o <= mosi_data_i(7);
+ sclk_o <= sclk;
+ cntr <= 0;
+ else
+ state <= S_IDLE;
+ cs_o <= '1';
+ end if;
+ end if;
+ elsif (cntr = 9) then
+ if (miso_en = '1') then
+ state <= S_IDLE;
+ cs_o <= '1';
+ end if;
+ else
+ sclk_o <= sclk;
+ if (miso_en = '1') then
+ read_reg(0) <= miso_i;
+ read_reg(7 downto 1) <= read_reg(6 downto 0);
+ cntr <= cntr + 1;
+ end if;
+ if (mosi_en = '1') then
+ mosi_o <= write_reg(7);
+ write_reg(7 downto 1) <= write_reg(6 downto 0);
+ end if;
+ end if;
+
+ else -- c_cpha = '0'
+
+ if (cntr = 0) then
+ sclk_o <= sclk;
+ if (miso_en = '1') then
+ read_reg(0) <= miso_i;
+ read_reg(7 downto 1) <= read_reg(6 downto 0);
+ cntr <= cntr + 1;
+ end if;
+ elsif (cntr = 8) then
+
+ data_ready_o <= '1';
+ miso_data_o <= read_reg;
+ sclk_o <= sclk;
+ if (mosi_en = '1') then
+ data_ready_o <= '0';
+ if (en_i = '1') then
+ write_reg <= mosi_data_i;
+ mosi_o <= mosi_data_i(7);
+ cntr <= 0;
+ else
+ cntr <= cntr + 1;
+ end if;
+ if (miso_en = '1') then
+ state <= S_IDLE;
+ cs_o <= '1';
+ end if;
+ end if;
+ elsif (cntr = 9) then
+ if (miso_en = '1') then
+ state <= S_IDLE;
+ cs_o <= '1';
+ end if;
+ else
+ sclk_o <= sclk;
+ if (miso_en = '1') then
+ read_reg(0) <= miso_i;
+ read_reg(7 downto 1) <= read_reg(6 downto 0);
+ cntr <= cntr + 1;
+ end if;
+ if (mosi_en = '1') then
+ write_reg(7 downto 1) <= write_reg(6 downto 0);
+ end if;
+ end if;
+
+ end if;
+
+ end case;
+ end if;
+
+end if;
+end process;
+
+P_SCLK_GEN : process (clk_i) begin
+if (rising_edge(clk_i)) then
+
+ if (sclk_en = '1') then
+ if edgecntr = c_edgecntrlimdiv2-1 then
+ sclk <= not sclk;
+ edgecntr <= 0;
+ else
+ edgecntr <= edgecntr + 1;
+ end if;
+ else
+ edgecntr <= 0;
+ if (c_cpol = '0') then
+ sclk <= '0';
+ else
+ sclk <= '1';
+ end if;
+ end if;
+
+end if;
+end process;
+
+end Behavioral;
\ No newline at end of file
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/rtl/spi_master.vhd b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/rtl/spi_master.vhd
new file mode 100644
index 0000000..6eb9ce2
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/rtl/spi_master.vhd
@@ -0,0 +1,315 @@
+--------------------------------------------------------------------------------
+-- AUTHOR: MEHMET BURAK AYKENAR
+-- CREATED: 09.12.2019
+-- REVISION DATE: 09.12.2019
+--
+--------------------------------------------------------------------------------
+-- DESCRIPTION:
+-- This module implements master part of SPI communication interface and can be used to any SPI slave IC.
+
+-- In order to read from a slave IC, mosi_data_i input signal should be assigned to desired value and en_i signal should be high.
+-- In order to write to a slave IC, en_i input signal should be high.
+-- data_ready_o output signal has the logic high value for one clock cycle as read or/and write operation finished. miso_data_o output signal
+-- has the data read from slave IC.
+-- In order to read or/and write consecutively, en_i signal should be kept high. To end the transaction, en_i input signal should be assigned to zero
+-- when data_ready_o output signal gets high.
+--------------------------------------------------------------------------------
+-- Limitation/Assumption: In order to use this module properly, the ratio of (c_clkfreq / c_sclkFreq) should be equal to 8 or more.
+-- For higher SCLK frequencies are possible but more elaboration is needed.
+-- Notes: c_cpol and c_cpha parameters are clock polarity and clock phase, respectively.
+--------------------------------------------------------------------------------
+-- VHDL DIALECT: VHDL '93
+--
+--------------------------------------------------------------------------------
+-- PROJECT : General purpose
+-- BOARD : General purpose
+-- ENTITY : spi_master
+--------------------------------------------------------------------
+-- FILE : spi_master.vhd
+--------------------------------------------------------------------------------
+-- REVISION HISTORY:
+-- REVISION DATE AUTHOR COMMENT
+-- -------- ---------- ------------ -----------
+-- 1.0 19.12.2019 M.B.AYKENAR INITIAL REVISION
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity spi_master is
+generic (
+ c_clkfreq : integer := 50_000_000;
+ c_sclkfreq : integer := 1_000_000;
+ c_cpol : std_logic := '0';
+ c_cpha : std_logic := '0'
+);
+Port (
+ clk_i : in STD_LOGIC;
+ en_i : in STD_LOGIC;
+ mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
+ miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
+ data_ready_o : out STD_LOGIC;
+ cs_o : out STD_LOGIC;
+ sclk_o : out STD_LOGIC;
+ mosi_o : out STD_LOGIC;
+ miso_i : in STD_LOGIC
+);
+end spi_master;
+
+architecture Behavioral of spi_master is
+
+--------------------------------------------------------------------------------
+-- CONSTANTS
+constant c_edgecntrlimdiv2 : integer := c_clkfreq/(c_sclkfreq*2);
+
+--------------------------------------------------------------------------------
+-- INTERNAL SIGNALS
+signal write_reg : std_logic_vector (7 downto 0) := (others => '0');
+signal read_reg : std_logic_vector (7 downto 0) := (others => '0');
+
+signal sclk_en : std_logic := '0';
+signal sclk : std_logic := '0';
+signal sclk_prev : std_logic := '0';
+signal sclk_rise : std_logic := '0';
+signal sclk_fall : std_logic := '0';
+
+signal pol_phase : std_logic_vector (1 downto 0) := (others => '0');
+signal mosi_en : std_logic := '0';
+signal miso_en : std_logic := '0';
+signal once : std_logic := '0';
+
+signal edgecntr : integer range 0 to c_edgecntrlimdiv2 := 0;
+
+signal cntr : integer range 0 to 15 := 0;
+
+--------------------------------------------------------------------------------
+-- STATE DEFINITIONS
+type states is (S_IDLE, S_TRANSFER);
+signal state : states := S_IDLE;
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+begin
+
+pol_phase <= c_cpol & c_cpha;
+
+--------------------------------------------------------------------------------
+-- SAMPLE_EN process assigns mosi_en and miso_en internal signals to sclk_fall or sclk_rise in a combinational logic according to
+-- generic parameters of c_cpol and c_cpha via pol_phase signal.
+P_SAMPLE_EN : process (pol_phase, sclk_fall, sclk_rise) begin
+
+ case pol_phase is
+
+ when "00" =>
+
+ mosi_en <= sclk_fall;
+ miso_en <= sclk_rise;
+
+ when "01" =>
+
+ mosi_en <= sclk_rise;
+ miso_en <= sclk_fall;
+
+ when "10" =>
+
+ mosi_en <= sclk_rise;
+ miso_en <= sclk_fall;
+
+ when "11" =>
+
+ mosi_en <= sclk_fall;
+ miso_en <= sclk_rise;
+
+ when others =>
+
+ end case;
+
+end process P_SAMPLE_EN;
+
+--------------------------------------------------------------------------------
+-- RISEFALL_DETECT process assigns sclk_rise and sclk_fall signals in a combinational logic.
+P_RISEFALL_DETECT : process (sclk, sclk_prev) begin
+
+ if (sclk = '1' and sclk_prev = '0') then
+ sclk_rise <= '1';
+ else
+ sclk_rise <= '0';
+ end if;
+
+ if (sclk = '0' and sclk_prev = '1') then
+ sclk_fall <= '1';
+ else
+ sclk_fall <= '0';
+ end if;
+
+end process P_RISEFALL_DETECT;
+
+--------------------------------------------------------------------------------
+-- In the MAIN process S_IDLE and S_TRANSFER states are implemented. state changes from S_IDLE to S_TRANSFER when en_i input
+-- signal has the logic high value. At that cycle, write_reg signal is assigned to mosi_data_i input signal. According to c_cpha generic
+-- parameter, the transaction operation changes slightly. This operational difference is well explained in the paper that can be found
+-- in Documents folder of the SPI, which is located in SVN server.
+P_MAIN : process (clk_i) begin
+if (rising_edge(clk_i)) then
+
+ data_ready_o <= '0';
+ sclk_prev <= sclk;
+
+ case state is
+
+--------------------------------------------------------------------------------
+ when S_IDLE =>
+
+ cs_o <= '1';
+ mosi_o <= '0';
+ data_ready_o <= '0';
+ sclk_en <= '0';
+ cntr <= 0;
+
+ if (c_cpol = '0') then
+ sclk_o <= '0';
+ else
+ sclk_o <= '1';
+ end if;
+
+ if (en_i = '1') then
+ state <= S_TRANSFER;
+ sclk_en <= '1';
+ write_reg <= mosi_data_i;
+ mosi_o <= mosi_data_i(7);
+ read_reg <= x"00";
+ end if;
+
+--------------------------------------------------------------------------------
+ when S_TRANSFER =>
+
+ cs_o <= '0';
+ mosi_o <= write_reg(7);
+
+
+ if (c_cpha = '1') then
+
+ if (cntr = 0) then
+ sclk_o <= sclk;
+ if (miso_en = '1') then
+ read_reg(0) <= miso_i;
+ read_reg(7 downto 1) <= read_reg(6 downto 0);
+ cntr <= cntr + 1;
+ once <= '1';
+ end if;
+ elsif (cntr = 8) then
+ if (once = '1') then
+ data_ready_o <= '1';
+ once <= '0';
+ end if;
+ miso_data_o <= read_reg;
+ if (mosi_en = '1') then
+ if (en_i = '1') then
+ write_reg <= mosi_data_i;
+ mosi_o <= mosi_data_i(7);
+ sclk_o <= sclk;
+ cntr <= 0;
+ else
+ state <= S_IDLE;
+ cs_o <= '1';
+ end if;
+ end if;
+ elsif (cntr = 9) then
+ if (miso_en = '1') then
+ state <= S_IDLE;
+ cs_o <= '1';
+ end if;
+ else
+ sclk_o <= sclk;
+ if (miso_en = '1') then
+ read_reg(0) <= miso_i;
+ read_reg(7 downto 1) <= read_reg(6 downto 0);
+ cntr <= cntr + 1;
+ end if;
+ if (mosi_en = '1') then
+ mosi_o <= write_reg(7);
+ write_reg(7 downto 1) <= write_reg(6 downto 0);
+ end if;
+ end if;
+
+ else -- c_cpha = '0'
+
+ if (cntr = 0) then
+ sclk_o <= sclk;
+ if (miso_en = '1') then
+ read_reg(0) <= miso_i;
+ read_reg(7 downto 1) <= read_reg(6 downto 0);
+ cntr <= cntr + 1;
+ once <= '1';
+ end if;
+ elsif (cntr = 8) then
+ if (once = '1') then
+ data_ready_o <= '1';
+ once <= '0';
+ end if;
+ miso_data_o <= read_reg;
+ sclk_o <= sclk;
+ if (mosi_en = '1') then
+ if (en_i = '1') then
+ write_reg <= mosi_data_i;
+ mosi_o <= mosi_data_i(7);
+ cntr <= 0;
+ else
+ cntr <= cntr + 1;
+ end if;
+ if (miso_en = '1') then
+ state <= S_IDLE;
+ cs_o <= '1';
+ end if;
+ end if;
+ elsif (cntr = 9) then
+ if (miso_en = '1') then
+ state <= S_IDLE;
+ cs_o <= '1';
+ end if;
+ else
+ sclk_o <= sclk;
+ if (miso_en = '1') then
+ read_reg(0) <= miso_i;
+ read_reg(7 downto 1) <= read_reg(6 downto 0);
+ cntr <= cntr + 1;
+ end if;
+ if (mosi_en = '1') then
+ write_reg(7 downto 1) <= write_reg(6 downto 0);
+ end if;
+ end if;
+
+ end if;
+
+ end case;
+
+end if;
+end process P_MAIN;
+
+--------------------------------------------------------------------------------
+-- In the SCLK_GEN process, internal sclk signal is generated if sclk_en signal is '1'.
+P_SCLK_GEN : process (clk_i) begin
+if (rising_edge(clk_i)) then
+
+ if (sclk_en = '1') then
+ if edgecntr = c_edgecntrlimdiv2-1 then
+ sclk <= not sclk;
+ edgecntr <= 0;
+ else
+ edgecntr <= edgecntr + 1;
+ end if;
+ else
+ edgecntr <= 0;
+ if (c_cpol = '0') then
+ sclk <= '0';
+ else
+ sclk <= '1';
+ end if;
+ end if;
+
+end if;
+end process P_SCLK_GEN;
+
+end Behavioral;
\ No newline at end of file
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/sim/Testbench1.PNG b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/sim/Testbench1.PNG
new file mode 100644
index 0000000..a2036a7
Binary files /dev/null and b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/sim/Testbench1.PNG differ
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/sim/Testbench_simulation.PNG b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/sim/Testbench_simulation.PNG
new file mode 100644
index 0000000..0f85ca1
Binary files /dev/null and b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/sim/Testbench_simulation.PNG differ
diff --git a/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/sim/tb_lw_spi_master.vhd b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/sim/tb_lw_spi_master.vhd
new file mode 100644
index 0000000..85ff558
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/hdl/spi_master_lightweight/sim/tb_lw_spi_master.vhd
@@ -0,0 +1,233 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY tb_lw_spi_master IS
+END tb_lw_spi_master;
+
+ARCHITECTURE behavior OF tb_lw_spi_master IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT lw_spi_master
+ PORT(
+ clk_i : IN std_logic;
+ en_i : IN std_logic;
+ mosi_data_i : IN std_logic_vector(7 downto 0);
+ miso_data_o : OUT std_logic_vector(7 downto 0);
+ data_ready_o : OUT std_logic;
+ cs_o : OUT std_logic;
+ sclk_o : OUT std_logic;
+ mosi_o : OUT std_logic;
+ miso_i : IN std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk_i : std_logic := '0';
+ signal en_i : std_logic := '0';
+ signal mosi_data_i : std_logic_vector(7 downto 0) := (others => '0');
+ signal miso_i : std_logic := '0';
+
+ --Outputs
+ signal miso_data_o : std_logic_vector(7 downto 0);
+ signal data_ready_o : std_logic;
+ signal cs_o : std_logic;
+ signal sclk_o : std_logic;
+ signal mosi_o : std_logic;
+
+ -- Clock period definitions
+-- Clock period definitions
+constant clk_i_period : time := 20 ns;
+constant sckPeriod : time := 200 ns;
+
+signal SPISIGNAL : std_logic_vector(7 downto 0) := (others => '0');
+signal spiWrite : std_logic := '0';
+signal spiWriteDone : std_logic := '0';
+
+BEGIN
+
+
+
+-- Instantiate the Unit Under Test (UUT)
+uut: lw_spi_master PORT MAP (
+clk_i => clk_i,
+en_i => en_i,
+mosi_data_i => mosi_data_i,
+miso_data_o => miso_data_o,
+data_ready_o => data_ready_o,
+cs_o => cs_o,
+sclk_o => sclk_o,
+mosi_o => mosi_o,
+miso_i => miso_i
+);
+
+-- Clock process definitions
+clk_i_process :process
+begin
+ clk_i <= '0';
+ wait for clk_i_period/2;
+ clk_i <= '1';
+ wait for clk_i_period/2;
+end process;
+
+SPIWRITE_P : process begin
+
+ wait until rising_edge(spiWrite);
+
+ -- for cpol = 1 cpha = 1
+ -- for cpol = 0 cpha = 0
+
+ miso_i <= SPISIGNAL(7);
+ wait until falling_edge(sclk_o);
+ miso_i <= SPISIGNAL(6);
+ wait until falling_edge(sclk_o);
+ miso_i <= SPISIGNAL(5);
+ wait until falling_edge(sclk_o);
+ miso_i <= SPISIGNAL(4);
+ wait until falling_edge(sclk_o);
+ miso_i <= SPISIGNAL(3);
+ wait until falling_edge(sclk_o);
+ miso_i <= SPISIGNAL(2);
+ wait until falling_edge(sclk_o);
+ miso_i <= SPISIGNAL(1);
+ wait until falling_edge(sclk_o);
+ miso_i <= SPISIGNAL(0);
+
+ -- for cpol = 0 cpha = 1
+ -- for cpol = 1 cpha = 0
+
+ -- miso_i <= SPISIGNAL(7);
+ -- wait until rising_edge(sclk_o);
+ -- miso_i <= SPISIGNAL(6);
+ -- wait until rising_edge(sclk_o);
+ -- miso_i <= SPISIGNAL(5);
+ -- wait until rising_edge(sclk_o);
+ -- miso_i <= SPISIGNAL(4);
+ -- wait until rising_edge(sclk_o);
+ -- miso_i <= SPISIGNAL(3);
+ -- wait until rising_edge(sclk_o);
+ -- miso_i <= SPISIGNAL(2);
+ -- wait until rising_edge(sclk_o);
+ -- miso_i <= SPISIGNAL(1);
+ -- wait until rising_edge(sclk_o);
+ -- miso_i <= SPISIGNAL(0);
+
+ spiWriteDone <= '1';
+ wait for 1 ps;
+ spiWriteDone <= '0';
+
+end process;
+
+
+-- Stimulus process
+stim_proc: process
+begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for clk_i_period*10;
+
+ -- insert stimulus here
+
+----------------------------------------------------------------
+-- -- CPOL,CPHA = 00
+ en_i <= '1';
+
+ -- write 0xA7, read 0xB2
+ mosi_data_i <= x"A7";
+ wait until falling_edge(cs_o);
+ SPISIGNAL <= x"B2";
+ spiWrite <= '1';
+ wait until rising_edge(spiWriteDone);
+ spiWrite <= '0';
+
+ -- write 0xB8, read 0xC3
+ wait until rising_edge(data_ready_o);
+ mosi_data_i <= x"B8";
+ wait until falling_edge(data_ready_o);
+ SPISIGNAL <= x"C3";
+ spiWrite <= '1';
+ wait until rising_edge(spiWriteDone);
+ spiWrite <= '0';
+ en_i <= '0';
+
+----------------------------------------------------------------
+-- -- CPOL,CPHA = 10
+-- en_i <= '1';
+--
+-- -- write 0xA7, read 0xB2
+-- mosi_data_i <= x"A7";
+-- wait until falling_edge(cs_o);
+-- wait for 50 ns;
+-- SPISIGNAL <= x"B2";
+-- spiWrite <= '1';
+-- wait until rising_edge(spiWriteDone);
+-- spiWrite <= '0';
+--
+-- -- write 0xB8, read 0xC3
+-- wait until rising_edge(data_ready_o);
+-- mosi_data_i <= x"B8";
+-- wait until falling_edge(data_ready_o);
+-- SPISIGNAL <= x"C3";
+-- spiWrite <= '1';
+-- wait until rising_edge(spiWriteDone);
+-- spiWrite <= '0';
+-- en_i <= '0';
+
+----------------------------------------------------------------
+ -- CPOL,CPHA = 01
+-- en_i <= '1';
+--
+-- -- write 0xA7, read 0xB2
+-- mosi_data_i <= x"A7";
+-- wait until falling_edge(cs_o);
+-- wait until rising_edge(sclk_o);
+-- SPISIGNAL <= x"B2";
+-- spiWrite <= '1';
+-- wait until rising_edge(spiWriteDone);
+-- spiWrite <= '0';
+--
+-- -- write 0xB8, read 0xC3
+-- wait until rising_edge(data_ready_o);
+-- mosi_data_i <= x"B8";
+-- wait until rising_edge(sclk_o);
+-- SPISIGNAL <= x"C3";
+-- spiWrite <= '1';
+-- wait until rising_edge(spiWriteDone);
+-- spiWrite <= '0';
+-- en_i <= '0';
+
+----------------------------------------------------------------
+-- -- CPOL,CPHA = 11
+-- en_i <= '1';
+--
+-- -- write 0xA7, read 0xB2
+-- mosi_data_i <= x"A7";
+-- wait until falling_edge(cs_o);
+-- wait until falling_edge(sclk_o);
+-- SPISIGNAL <= x"B2";
+-- spiWrite <= '1';
+-- wait until rising_edge(spiWriteDone);
+-- spiWrite <= '0';
+--
+-- -- write 0xB8, read 0xC3
+-- wait until rising_edge(data_ready_o);
+-- mosi_data_i <= x"B8";
+-- wait until falling_edge(sclk_o);
+-- SPISIGNAL <= x"C3";
+-- spiWrite <= '1';
+-- wait until rising_edge(spiWriteDone);
+-- spiWrite <= '0';
+-- en_i <= '0';
+
+
+
+ wait for 1 us;
+
+ assert false
+ report "SIM DONE"
+ severity failure;
+end process;
+
+END;
diff --git a/LAB3/ip/axi4-stream-spi-master/xgui/axi4stream_spi_master_v1_0.tcl b/LAB3/ip/axi4-stream-spi-master/xgui/axi4stream_spi_master_v1_0.tcl
new file mode 100644
index 0000000..5bd7cde
--- /dev/null
+++ b/LAB3/ip/axi4-stream-spi-master/xgui/axi4stream_spi_master_v1_0.tcl
@@ -0,0 +1,74 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "c_clkfreq" -parent ${Page_0}
+ #Adding Group
+ set SPI_parameters [ipgui::add_group $IPINST -name "SPI parameters" -parent ${Page_0}]
+ set c_sclkfreq [ipgui::add_param $IPINST -name "c_sclkfreq" -parent ${SPI_parameters}]
+ set_property tooltip {Desired SCLK frequency (must be less or equal than aclk_freq/8)} ${c_sclkfreq}
+ ipgui::add_param $IPINST -name "c_cpol" -parent ${SPI_parameters}
+ ipgui::add_param $IPINST -name "c_cpha" -parent ${SPI_parameters}
+
+
+
+}
+
+proc update_PARAM_VALUE.c_clkfreq { PARAM_VALUE.c_clkfreq } {
+ # Procedure called to update c_clkfreq when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.c_clkfreq { PARAM_VALUE.c_clkfreq } {
+ # Procedure called to validate c_clkfreq
+ return true
+}
+
+proc update_PARAM_VALUE.c_cpha { PARAM_VALUE.c_cpha } {
+ # Procedure called to update c_cpha when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.c_cpha { PARAM_VALUE.c_cpha } {
+ # Procedure called to validate c_cpha
+ return true
+}
+
+proc update_PARAM_VALUE.c_cpol { PARAM_VALUE.c_cpol } {
+ # Procedure called to update c_cpol when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.c_cpol { PARAM_VALUE.c_cpol } {
+ # Procedure called to validate c_cpol
+ return true
+}
+
+proc update_PARAM_VALUE.c_sclkfreq { PARAM_VALUE.c_sclkfreq } {
+ # Procedure called to update c_sclkfreq when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.c_sclkfreq { PARAM_VALUE.c_sclkfreq } {
+ # Procedure called to validate c_sclkfreq
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.c_clkfreq { MODELPARAM_VALUE.c_clkfreq PARAM_VALUE.c_clkfreq } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.c_clkfreq}] ${MODELPARAM_VALUE.c_clkfreq}
+}
+
+proc update_MODELPARAM_VALUE.c_sclkfreq { MODELPARAM_VALUE.c_sclkfreq PARAM_VALUE.c_sclkfreq } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.c_sclkfreq}] ${MODELPARAM_VALUE.c_sclkfreq}
+}
+
+proc update_MODELPARAM_VALUE.c_cpol { MODELPARAM_VALUE.c_cpol PARAM_VALUE.c_cpol } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.c_cpol}] ${MODELPARAM_VALUE.c_cpol}
+}
+
+proc update_MODELPARAM_VALUE.c_cpha { MODELPARAM_VALUE.c_cpha PARAM_VALUE.c_cpha } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.c_cpha}] ${MODELPARAM_VALUE.c_cpha}
+}
+
diff --git a/LAB3/sim/ReadMe.md b/LAB3/sim/ReadMe.md
new file mode 100644
index 0000000..0f8aee3
--- /dev/null
+++ b/LAB3/sim/ReadMe.md
@@ -0,0 +1,3 @@
+# Placeholder
+
+This is a placeholder.
\ No newline at end of file
diff --git a/LAB3/vivado/lab3/lab3.xpr b/LAB3/vivado/lab3/lab3.xpr
new file mode 100644
index 0000000..bb6e17f
--- /dev/null
+++ b/LAB3/vivado/lab3/lab3.xpr
@@ -0,0 +1,313 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ default_dashboard
+
+
+
diff --git a/vhdl_ls.toml b/vhdl_ls.toml
index 2653b30..3d2c067 100644
--- a/vhdl_ls.toml
+++ b/vhdl_ls.toml
@@ -15,10 +15,10 @@ lab2_lib.files = [
"LAB2/sim/**/*.vhd"
]
-# lab3_lib.files = [
-# "LAB3/src/**/*.vhd",
-# "LAB3/sim/**/*.vhd"
-# ]
+lab3_lib.files = [
+ "LAB3/src/**/*.vhd",
+ "LAB3/sim/**/*.vhd"
+]
xpm.files = [
"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd"