From 3e1f49f0436ab87677ebfa0da835704daeb91392 Mon Sep 17 00:00:00 2001 From: Davide Cavagnola Date: Tue, 18 Mar 2025 11:53:08 +0100 Subject: [PATCH] Update README.md --- README.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/README.md b/README.md index e69de29..93887c3 100644 --- a/README.md +++ b/README.md @@ -0,0 +1,14 @@ +# VHDL Laboratory – Digital Electronic System Design +Politecnico di Milano (2024-2025) + +## Overview +This repository contains VHDL projects and exercises from the **Digital Electronic System Design Laboratory** at **Politecnico di Milano** (Course Code: 054083). The course focuses on **FPGA-based digital design** using VHDL, simulation, synthesis, and implementation. + +## Tools & Hardware +- **Software**: Xilinx Vivado 2020.2 (WebPack Edition) +- **Hardware**: Digilent Basys 3 (Xilinx Artix-7 FPGA - XC7A35T-1CPG236C) + +## Course Goals +- Develop practical skills for FPGA-based digital system design +- Implement and test VHDL architectures using Vivado and Basys 3 +- Learn FPGA timing, power, I/O, and memory management \ No newline at end of file