diff --git a/LAB2/src/depacketizer.vhd b/LAB2/src/depacketizer.vhd index d1437ef..ef19282 100644 --- a/LAB2/src/depacketizer.vhd +++ b/LAB2/src/depacketizer.vhd @@ -1,7 +1,9 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; + ENTITY depacketizer IS + GENERIC ( HEADER : INTEGER := 16#FF#; FOOTER : INTEGER := 16#F1# @@ -16,79 +18,86 @@ ENTITY depacketizer IS m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; - m_axis_tready : IN STD_LOGIC; - m_axis_tlast : OUT STD_LOGIC + m_axis_tlast : OUT STD_LOGIC; + m_axis_tready : IN STD_LOGIC ); + END ENTITY depacketizer; ARCHITECTURE rtl OF depacketizer IS - -- Enumeration for the state machine - -- IDLE: Waiting for the start of a new packet - -- STREAMING: Actively processing and forwarding packet data - TYPE state_type IS (IDLE, STREAMING); + TYPE state_type IS (IDLE, RECEIVING); SIGNAL state : state_type := IDLE; - -- Buffer to handle backpressure - SIGNAL buffer_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); - SIGNAL buffer_valid : STD_LOGIC := '0'; -- Indicates if buffer_in contains valid data + SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL s_axis_tready_int : STD_LOGIC; + SIGNAL m_axis_tvalid_int : STD_LOGIC; + BEGIN - depacketizer_fsm : PROCESS (clk) + s_axis_tready <= s_axis_tready_int; + m_axis_tvalid <= m_axis_tvalid_int; + + PROCESS (clk) + VARIABLE trigger : STD_LOGIC := '0'; BEGIN + IF rising_edge(clk) THEN IF aresetn = '0' THEN - -- Reset: back to idle and clear everything - state <= IDLE; - s_axis_tready <= '0'; - m_axis_tvalid <= '0'; + + data_buffer <= (OTHERS => '0'); + + s_axis_tready_int <= '0'; + m_axis_tvalid_int <= '0'; m_axis_tlast <= '0'; - m_axis_tdata <= (OTHERS => '0'); - buffer_in <= (OTHERS => '0'); - buffer_valid <= '0'; ELSE - -- Defaults for each clock cycle - s_axis_tready <= '1'; - m_axis_tvalid <= '0'; - m_axis_tlast <= '0'; CASE state IS - WHEN IDLE => - -- Wait for start of a new packet - IF s_axis_tvalid = '1' THEN - m_axis_tvalid <= '0'; - IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)) THEN - state <= STREAMING; + IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN + IF data_buffer = STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)) THEN + state <= RECEIVING; END IF; END IF; - WHEN STREAMING => - IF s_axis_tvalid = '1' THEN - - -- End of packet detected + WHEN RECEIVING => + IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)) THEN - -- Send the last data and transition to IDLE - m_axis_tdata <= buffer_in; -- Send the last buffered data + m_axis_tlast <= '1'; state <= IDLE; - m_axis_tlast <= '1'; -- Let receiver know packet ends ELSE - -- Valid payload: send to output - IF buffer_valid = '1' AND m_axis_tready = '1' THEN - m_axis_tdata <= buffer_in; - m_axis_tvalid <= '1'; - buffer_valid <= '0'; -- Clear the buffer - END IF; - - buffer_in <= s_axis_tdata; - buffer_valid <= '1'; + m_axis_tlast <= '0'; END IF; + + trigger := '1'; END IF; END CASE; + + -- Output data - master + IF m_axis_tready = '1' THEN + m_axis_tvalid_int <= '0'; + END IF; + + IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN + m_axis_tvalid_int <= '1'; + m_axis_tdata <= data_buffer; + + trigger := '0'; + END IF; + + -- Input data - slave + s_axis_tready_int <= m_axis_tready; + + IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN + data_buffer <= s_axis_tdata; + END IF; + END IF; END IF; + END PROCESS; END ARCHITECTURE; \ No newline at end of file diff --git a/LAB2/src/lab_2/lab_2.bd b/LAB2/src/lab_2/lab_2.bd index b8c417a..363b655 100644 --- a/LAB2/src/lab_2/lab_2.bd +++ b/LAB2/src/lab_2/lab_2.bd @@ -11,13 +11,13 @@ "design_tree": { "bram_writer_0": "", "led_blinker_0": "", - "img_conv_0": "", "led_blinker_1": "", "led_blinker_2": "", "system_ila_0": "", "clk_wiz_0": "", "proc_sys_reset_1": "", "AXI4Stream_UART_0": "", + "img_conv_0": "", "depacketizer_0": "", "packetizer_0": "", "rgb2gray_0": "" @@ -258,143 +258,6 @@ } } }, - "img_conv_0": { - "vlnv": "xilinx.com:module_ref:img_conv:1.0", - "xci_name": "lab_2_img_conv_0_0", - "xci_path": "ip\\lab_2_img_conv_0_0\\lab_2_img_conv_0_0.xci", - "inst_hier_path": "img_conv_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "img_conv", - "boundary_crc": "0x0" - }, - "interface_ports": { - "m_axis": { - "mode": "Master", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "m_axis_tdata", - "direction": "O", - "left": "7", - "right": "0" - }, - "TLAST": { - "physical_name": "m_axis_tlast", - "direction": "O" - }, - "TVALID": { - "physical_name": "m_axis_tvalid", - "direction": "O" - }, - "TREADY": { - "physical_name": "m_axis_tready", - "direction": "I" - } - } - } - }, - "ports": { - "clk": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "m_axis", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "aresetn", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - } - }, - "aresetn": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - }, - "conv_addr": { - "direction": "O", - "left": "15", - "right": "0" - }, - "conv_data": { - "direction": "I", - "left": "6", - "right": "0" - }, - "start_conv": { - "direction": "I" - }, - "done_conv": { - "direction": "O" - } - } - }, "led_blinker_1": { "vlnv": "xilinx.com:module_ref:led_blinker:1.0", "xci_name": "lab_2_led_blinker_1_0", @@ -585,6 +448,119 @@ } } }, + "img_conv_0": { + "vlnv": "xilinx.com:module_ref:img_conv:1.0", + "xci_name": "lab_2_img_conv_0_0", + "xci_path": "ip\\lab_2_img_conv_0_0\\lab_2_img_conv_0_0.xci", + "inst_hier_path": "img_conv_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "img_conv", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "conv_addr": { + "direction": "O", + "left": "15", + "right": "0" + }, + "conv_data": { + "direction": "I", + "left": "6", + "right": "0" + }, + "start_conv": { + "direction": "I" + }, + "done_conv": { + "direction": "O" + } + } + }, "depacketizer_0": { "vlnv": "xilinx.com:module_ref:depacketizer:1.0", "xci_name": "lab_2_depacketizer_0_0", @@ -780,7 +756,7 @@ "value_src": "constant" }, "HAS_TLAST": { - "value": "0", + "value": "1", "value_src": "constant" } }, @@ -791,6 +767,10 @@ "left": "7", "right": "0" }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, "TVALID": { "physical_name": "m_axis_tvalid", "direction": "O" @@ -834,7 +814,7 @@ "value_src": "constant" }, "HAS_TLAST": { - "value": "1", + "value": "0", "value_src": "constant" } }, @@ -845,10 +825,6 @@ "left": "7", "right": "0" }, - "TLAST": { - "physical_name": "s_axis_tlast", - "direction": "I" - }, "TVALID": { "physical_name": "s_axis_tvalid", "direction": "I" @@ -1051,6 +1027,12 @@ "system_ila_0/SLOT_0_AXIS" ] }, + "AXI4Stream_UART_0_UART": { + "interface_ports": [ + "usb_uart", + "AXI4Stream_UART_0/UART" + ] + }, "AXI4Stream_UART_0_M00_AXIS_RX": { "interface_ports": [ "AXI4Stream_UART_0/M00_AXIS_RX", @@ -1063,12 +1045,6 @@ "AXI4Stream_UART_0/S00_AXIS_TX" ] }, - "AXI4Stream_UART_0_UART": { - "interface_ports": [ - "usb_uart", - "AXI4Stream_UART_0/UART" - ] - }, "rgb2gray_0_m_axis": { "interface_ports": [ "rgb2gray_0/m_axis", @@ -1088,7 +1064,6 @@ "clk_wiz_0_clk_out1": { "ports": [ "clk_wiz_0/clk_out1", - "img_conv_0/clk", "led_blinker_0/clk", "led_blinker_1/clk", "led_blinker_2/clk", @@ -1098,6 +1073,7 @@ "AXI4Stream_UART_0/clk_uart", "AXI4Stream_UART_0/m00_axis_rx_aclk", "AXI4Stream_UART_0/s00_axis_tx_aclk", + "img_conv_0/clk", "depacketizer_0/clk", "packetizer_0/clk", "rgb2gray_0/clk" @@ -1106,7 +1082,6 @@ "proc_sys_reset_0_peripheral_aresetn": { "ports": [ "proc_sys_reset_1/peripheral_aresetn", - "img_conv_0/aresetn", "led_blinker_0/aresetn", "led_blinker_1/aresetn", "led_blinker_2/aresetn", @@ -1114,6 +1089,7 @@ "system_ila_0/resetn", "AXI4Stream_UART_0/m00_axis_rx_aresetn", "AXI4Stream_UART_0/s00_axis_tx_aresetn", + "img_conv_0/aresetn", "depacketizer_0/aresetn", "packetizer_0/aresetn", "rgb2gray_0/resetn" diff --git a/LAB2/src/lab_2/lab_2.bda b/LAB2/src/lab_2/lab_2.bda index 8223b12..0bd21fd 100644 --- a/LAB2/src/lab_2/lab_2.bda +++ b/LAB2/src/lab_2/lab_2.bda @@ -21,22 +21,22 @@ + lab_2 + BC + + 2 lab_2 VR - - lab_2 - BC - active 2 PM - + - + diff --git a/LAB2/src/packetizer.vhd b/LAB2/src/packetizer.vhd index 9f45000..7161607 100644 --- a/LAB2/src/packetizer.vhd +++ b/LAB2/src/packetizer.vhd @@ -1,115 +1,125 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; - -entity packetizer is - generic ( - HEADER: INTEGER :=16#FF#; - FOOTER: INTEGER :=16#F1# +ENTITY packetizer IS + GENERIC ( + HEADER : INTEGER := 16#FF#; + FOOTER : INTEGER := 16#F1# ); - port ( - clk : in std_logic; - aresetn : in std_logic; + PORT ( + clk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; - s_axis_tdata : in std_logic_vector(7 downto 0); - s_axis_tvalid : in std_logic; - s_axis_tready : out std_logic; - s_axis_tlast : in std_logic; + s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s_axis_tvalid : IN STD_LOGIC; + s_axis_tready : OUT STD_LOGIC; + s_axis_tlast : IN STD_LOGIC; - m_axis_tdata : out std_logic_vector(7 downto 0); - m_axis_tvalid : out std_logic; - m_axis_tready : in std_logic - + m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m_axis_tvalid : OUT STD_LOGIC; + m_axis_tready : IN STD_LOGIC; + m_axis_tlast : OUT STD_LOGIC ); -end entity packetizer; +END ENTITY packetizer; -architecture rtl of packetizer is +ARCHITECTURE rtl OF packetizer IS - type state_type is (IDLE, SEND_HEADER, FORWARD_PAYLOAD, SEND_FOOTER); - signal state : state_type := IDLE; + TYPE state_type IS (IDLE, SENDING_HEADER, SENDING_DATA, SENDING_FOOTER); + SIGNAL state : state_type := IDLE; - signal payload_buffer : std_logic_vector(7 downto 0); - signal last_seen : std_logic := '0'; -- Tracks s_axis_tlast - signal data_valid : std_logic := '0'; + SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0); -begin + SIGNAL s_axis_tready_int : STD_LOGIC; + SIGNAL m_axis_tvalid_int : STD_LOGIC; - process(clk) - begin - if rising_edge(clk) then - if aresetn = '0' then - -- Reset all states and outputs - state <= IDLE; - s_axis_tready <= '0'; - m_axis_tvalid <= '0'; - m_axis_tdata <= (others => '0'); - data_valid <= '0'; - last_seen <= '0'; + SIGNAL last_seen : STD_LOGIC := '0'; - else - -- Defaults - s_axis_tready <= '0'; - m_axis_tvalid <= '0'; +BEGIN - case state is + s_axis_tready <= s_axis_tready_int; + m_axis_tvalid <= m_axis_tvalid_int; - when IDLE => - -- Wait for input data to start a new packet - if s_axis_tvalid = '1' then - state <= SEND_HEADER; - payload_buffer <= s_axis_tdata; - data_valid <= '1'; - last_seen <= s_axis_tlast; - end if; + PROCESS (clk) + VARIABLE trigger : STD_LOGIC := '0'; + BEGIN - when SEND_HEADER => - -- Send HEADER byte - if m_axis_tready = '1' then - m_axis_tdata <= std_logic_vector(to_unsigned(HEADER, 8)); - m_axis_tvalid <= '1'; - state <= FORWARD_PAYLOAD; - end if; + IF rising_edge(clk) THEN + IF aresetn = '0' THEN - when FORWARD_PAYLOAD => - -- Send buffered payload from IDLE phase - if m_axis_tready = '1' and data_valid = '1' then - m_axis_tdata <= payload_buffer; - m_axis_tvalid <= '1'; - data_valid <= '0'; + data_buffer <= (OTHERS => '0'); - -- Ready to receive next payload byte - s_axis_tready <= '1'; - end if; + s_axis_tready_int <= '0'; + m_axis_tvalid_int <= '0'; + m_axis_tlast <= '0'; - -- Check for new data while output is valid - if s_axis_tready = '1' and s_axis_tvalid = '1' then - payload_buffer <= s_axis_tdata; - data_valid <= '1'; - last_seen <= s_axis_tlast; + ELSE - -- If last payload byte, next state is FOOTER - if s_axis_tlast = '1' then - state <= SEND_FOOTER; - end if; - end if; + m_axis_tlast <= '0'; - when SEND_FOOTER => - if m_axis_tready = '1' and data_valid = '1' then - -- Send last payload byte - m_axis_tdata <= payload_buffer; - m_axis_tvalid <= '1'; - data_valid <= '0'; - elsif m_axis_tready = '1' then - -- Send FOOTER byte after last payload - m_axis_tdata <= std_logic_vector(to_unsigned(FOOTER, 8)); - m_axis_tvalid <= '1'; - state <= IDLE; - end if; + IF m_axis_tready = '1' THEN + m_axis_tvalid_int <= '0'; + END IF; - end case; - end if; - end if; - end process; + CASE state IS + WHEN IDLE => + IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN + state <= SENDING_HEADER; + END IF; -end architecture; \ No newline at end of file + WHEN SENDING_HEADER => + IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN + m_axis_tvalid_int <= '1'; + m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)); + + state <= SENDING_DATA; + END IF; + + WHEN SENDING_DATA => + IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN + IF s_axis_tlast = '1' THEN + last_seen <= '1'; + END IF; + + trigger := '1'; + END IF; + + IF last_seen = '1' THEN + state <= SENDING_FOOTER; + last_seen <= '0'; + + trigger := '1'; + END IF; + + WHEN SENDING_FOOTER => + IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN + m_axis_tvalid_int <= '1'; + m_axis_tlast <= '1'; + m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)); + + state <= IDLE; + END IF; + + END CASE; + + -- Output data - master + IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN + m_axis_tvalid_int <= '1'; + m_axis_tdata <= data_buffer; + + trigger := '0'; + END IF; + + -- Input data - slave + s_axis_tready_int <= m_axis_tready; + + IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN + data_buffer <= s_axis_tdata; + END IF; + + END IF; + END IF; + + END PROCESS; + +END ARCHITECTURE rtl; \ No newline at end of file diff --git a/LAB2/src/pak_depak/hdl/pak_depak_wrapper.vhd b/LAB2/src/pak_depak/hdl/pak_depak_wrapper.vhd new file mode 100644 index 0000000..8d5b668 --- /dev/null +++ b/LAB2/src/pak_depak/hdl/pak_depak_wrapper.vhd @@ -0,0 +1,40 @@ +--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +--Date : Mon Apr 14 16:01:03 2025 +--Host : Davide-Samsung running 64-bit major release (build 9200) +--Command : generate_target pak_depak_wrapper.bd +--Design : pak_depak_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pak_depak_wrapper is + port ( + reset : in STD_LOGIC; + sys_clock : in STD_LOGIC; + usb_uart_rxd : in STD_LOGIC; + usb_uart_txd : out STD_LOGIC + ); +end pak_depak_wrapper; + +architecture STRUCTURE of pak_depak_wrapper is + component pak_depak is + port ( + reset : in STD_LOGIC; + sys_clock : in STD_LOGIC; + usb_uart_txd : out STD_LOGIC; + usb_uart_rxd : in STD_LOGIC + ); + end component pak_depak; +begin +pak_depak_i: component pak_depak + port map ( + reset => reset, + sys_clock => sys_clock, + usb_uart_rxd => usb_uart_rxd, + usb_uart_txd => usb_uart_txd + ); +end STRUCTURE; diff --git a/LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/pak_depak_AXI4Stream_UART_0_0.xml b/LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/pak_depak_AXI4Stream_UART_0_0.xml new file mode 100644 index 0000000..519245c --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/pak_depak_AXI4Stream_UART_0_0.xml @@ -0,0 +1,1210 @@ + + + DigiLAB + customized_ip + pak_depak_AXI4Stream_UART_0_0 + 1.0 + + + M00_AXIS_RX + + + + + + + TDATA + + + m00_axis_rx_tdata + + + + + TVALID + + + m00_axis_rx_tvalid + + + + + TREADY + + + m00_axis_rx_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S00_AXIS_TX + + + + + + + TDATA + + + s00_axis_tx_tdata + + + + + TVALID + + + s00_axis_tx_tvalid + + + + + TREADY + + + s00_axis_tx_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + M00_AXIS_RX_RST + + + + + + + RST + + + m00_axis_rx_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + M00_AXIS_RX_CLK + + + + + + + CLK + + + m00_axis_rx_aclk + + + + + + ASSOCIATED_BUSIF + M00_AXIS_RX + + + ASSOCIATED_RESET + m00_axis_rx_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S00_AXIS_TX_RST + + + + + + + RST + + + s00_axis_tx_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + S00_AXIS_TX_CLK + + + + + + + CLK + + + s00_axis_tx_aclk + + + + + + ASSOCIATED_BUSIF + S00_AXIS_TX + + + ASSOCIATED_RESET + s00_axis_tx_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + reset + + + + + + + RST + + + rst + + + + + + POLARITY + ACTIVE_HIGH + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + ClockUART + Clock used to calculate the delay for UART + + + + + + + CLK + + + clk_uart + + + + + + ASSOCIATED_BUSIF + UART + + + ASSOCIATED_RESET + rst + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + UART + UART + + + + + + + TxD + + + UART_TX + + + + + RxD + + + UART_RX + + + + + + BOARD.ASSOCIATED_PARAM + UART_BOARD_INTERFACE + + + + required + + + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + AXI4Stream_UART_v1_0 + + xilinx_anylanguagesynthesis_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:ce2e8a48 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:ce2e8a48 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + pak_depak_AXI4Stream_UART_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:ce2e8a48 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + AXI4Stream_UART_v1_0 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:6d0bd665 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + pak_depak_AXI4Stream_UART_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:6d0bd665 + + + sim_type + rtl + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:ce2e8a48 + + + + + + + clk_uart + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rst + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + UART_TX + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + UART_RX + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_rx_aclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_rx_aresetn + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_rx_tvalid + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_rx_tdata + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_rx_tready + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_tx_aclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_tx_aresetn + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_tx_tready + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_tx_tdata + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s00_axis_tx_tvalid + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + UART_BAUD_RATE + Rs232 Baud Rate + 115200 + + + UART_CLOCK_FREQUENCY + Rs232 Clock Frequency + 100000000 + + + C_M00_AXIS_RX_TDATA_WIDTH + C M00 Axis Rx Tdata Width + 8 + + + C_S00_AXIS_TX_TDATA_WIDTH + C S00 Axis Tx Tdata Width + 8 + + + + + + choice_list_23c37a81 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 230400 + 460800 + 921600 + 1000000 + 1500000 + 2000000 + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_d8920bdd + 8 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../../ipshared/453d/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd + vhdlSource + + + ../../ipshared/453d/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd + vhdlSource + + + ../../ipshared/453d/hdl/UART_Engine.vhd + vhdlSource + + + ../../ipshared/453d/hdl/UART_Manager.vhd + vhdlSource + + + ../../ipshared/453d/hdl/AXI4Stream_UART_v1_0.vhd + vhdlSource + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/pak_depak_AXI4Stream_UART_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/453d/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd + vhdlSource + + + ../../ipshared/453d/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd + vhdlSource + + + ../../ipshared/453d/hdl/UART_Engine.vhd + vhdlSource + + + ../../ipshared/453d/hdl/UART_Manager.vhd + vhdlSource + + + ../../ipshared/453d/hdl/AXI4Stream_UART_v1_0.vhd + vhdlSource + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/pak_depak_AXI4Stream_UART_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_implementation_view_fileset + + pak_depak_AXI4Stream_UART_0_0_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output + + + Component_Name + pak_depak_AXI4Stream_UART_0_0 + + + UART_BAUD_RATE + Baud Rate + 115200 + + + UART_CLOCK_FREQUENCY + Rs232 Clock Frequency + 100000000 + + + C_M00_AXIS_RX_TDATA_WIDTH + C M00 Axis Rx Tdata Width + 8 + + + + false + + + + + + C_S00_AXIS_TX_TDATA_WIDTH + C S00 Axis Tx Tdata Width + 8 + + + USE_BOARD_FLOW + true + + + UART_BOARD_INTERFACE + usb_uart + + + + + AXI4-Stream UART + + XPM_FIFO + + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/sim/pak_depak_AXI4Stream_UART_0_0.vhd b/LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/sim/pak_depak_AXI4Stream_UART_0_0.vhd new file mode 100644 index 0000000..29821e4 --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/sim/pak_depak_AXI4Stream_UART_0_0.vhd @@ -0,0 +1,151 @@ +-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: DigiLAB:ip:AXI4Stream_UART:1.1 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY pak_depak_AXI4Stream_UART_0_0 IS + PORT ( + clk_uart : IN STD_LOGIC; + rst : IN STD_LOGIC; + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + m00_axis_rx_aclk : IN STD_LOGIC; + m00_axis_rx_aresetn : IN STD_LOGIC; + m00_axis_rx_tvalid : OUT STD_LOGIC; + m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m00_axis_rx_tready : IN STD_LOGIC; + s00_axis_tx_aclk : IN STD_LOGIC; + s00_axis_tx_aresetn : IN STD_LOGIC; + s00_axis_tx_tready : OUT STD_LOGIC; + s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s00_axis_tx_tvalid : IN STD_LOGIC + ); +END pak_depak_AXI4Stream_UART_0_0; + +ARCHITECTURE pak_depak_AXI4Stream_UART_0_0_arch OF pak_depak_AXI4Stream_UART_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF pak_depak_AXI4Stream_UART_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT AXI4Stream_UART_v1_0 IS + GENERIC ( + UART_BAUD_RATE : INTEGER; + UART_CLOCK_FREQUENCY : INTEGER; + C_M00_AXIS_RX_TDATA_WIDTH : INTEGER; + C_S00_AXIS_TX_TDATA_WIDTH : INTEGER + ); + PORT ( + clk_uart : IN STD_LOGIC; + rst : IN STD_LOGIC; + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + m00_axis_rx_aclk : IN STD_LOGIC; + m00_axis_rx_aresetn : IN STD_LOGIC; + m00_axis_rx_tvalid : OUT STD_LOGIC; + m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m00_axis_rx_tready : IN STD_LOGIC; + s00_axis_tx_aclk : IN STD_LOGIC; + s00_axis_tx_aresetn : IN STD_LOGIC; + s00_axis_tx_tready : OUT STD_LOGIC; + s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s00_axis_tx_tvalid : IN STD_LOGIC + ); + END COMPONENT AXI4Stream_UART_v1_0; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_tready: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX, WIZ_DATA_WIDTH 32, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TREADY"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXIS_TX_RST RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX_CLK, ASSOCIATED_BUSIF S00_AXIS_TX, ASSOCIATED_RESET s00_axis_tx_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXIS_TX_CLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_tvalid: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX, WIZ_DATA_WIDTH 32, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXIS_RX_RST RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX_CLK, ASSOCIATED_BUSIF M00_AXIS_RX, ASSOCIATED_RESET m00_axis_rx_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXIS_RX_CLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF UART_RX: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD"; + ATTRIBUTE X_INTERFACE_PARAMETER OF UART_TX: SIGNAL IS "XIL_INTERFACENAME UART, BOARD.ASSOCIATED_PARAM UART_BOARD_INTERFACE"; + ATTRIBUTE X_INTERFACE_INFO OF UART_TX: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD"; + ATTRIBUTE X_INTERFACE_PARAMETER OF rst: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk_uart: SIGNAL IS "XIL_INTERFACENAME ClockUART, ASSOCIATED_BUSIF UART, ASSOCIATED_RESET rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk_uart: SIGNAL IS "xilinx.com:signal:clock:1.0 ClockUART CLK"; +BEGIN + U0 : AXI4Stream_UART_v1_0 + GENERIC MAP ( + UART_BAUD_RATE => 115200, + UART_CLOCK_FREQUENCY => 100000000, + C_M00_AXIS_RX_TDATA_WIDTH => 8, + C_S00_AXIS_TX_TDATA_WIDTH => 8 + ) + PORT MAP ( + clk_uart => clk_uart, + rst => rst, + UART_TX => UART_TX, + UART_RX => UART_RX, + m00_axis_rx_aclk => m00_axis_rx_aclk, + m00_axis_rx_aresetn => m00_axis_rx_aresetn, + m00_axis_rx_tvalid => m00_axis_rx_tvalid, + m00_axis_rx_tdata => m00_axis_rx_tdata, + m00_axis_rx_tready => m00_axis_rx_tready, + s00_axis_tx_aclk => s00_axis_tx_aclk, + s00_axis_tx_aresetn => s00_axis_tx_aresetn, + s00_axis_tx_tready => s00_axis_tx_tready, + s00_axis_tx_tdata => s00_axis_tx_tdata, + s00_axis_tx_tvalid => s00_axis_tx_tvalid + ); +END pak_depak_AXI4Stream_UART_0_0_arch; diff --git a/LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/synth/pak_depak_AXI4Stream_UART_0_0.vhd b/LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/synth/pak_depak_AXI4Stream_UART_0_0.vhd new file mode 100644 index 0000000..d0729fa --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_AXI4Stream_UART_0_0/synth/pak_depak_AXI4Stream_UART_0_0.vhd @@ -0,0 +1,155 @@ +-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: DigiLAB:ip:AXI4Stream_UART:1.1 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY pak_depak_AXI4Stream_UART_0_0 IS + PORT ( + clk_uart : IN STD_LOGIC; + rst : IN STD_LOGIC; + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + m00_axis_rx_aclk : IN STD_LOGIC; + m00_axis_rx_aresetn : IN STD_LOGIC; + m00_axis_rx_tvalid : OUT STD_LOGIC; + m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m00_axis_rx_tready : IN STD_LOGIC; + s00_axis_tx_aclk : IN STD_LOGIC; + s00_axis_tx_aresetn : IN STD_LOGIC; + s00_axis_tx_tready : OUT STD_LOGIC; + s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s00_axis_tx_tvalid : IN STD_LOGIC + ); +END pak_depak_AXI4Stream_UART_0_0; + +ARCHITECTURE pak_depak_AXI4Stream_UART_0_0_arch OF pak_depak_AXI4Stream_UART_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF pak_depak_AXI4Stream_UART_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT AXI4Stream_UART_v1_0 IS + GENERIC ( + UART_BAUD_RATE : INTEGER; + UART_CLOCK_FREQUENCY : INTEGER; + C_M00_AXIS_RX_TDATA_WIDTH : INTEGER; + C_S00_AXIS_TX_TDATA_WIDTH : INTEGER + ); + PORT ( + clk_uart : IN STD_LOGIC; + rst : IN STD_LOGIC; + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + m00_axis_rx_aclk : IN STD_LOGIC; + m00_axis_rx_aresetn : IN STD_LOGIC; + m00_axis_rx_tvalid : OUT STD_LOGIC; + m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m00_axis_rx_tready : IN STD_LOGIC; + s00_axis_tx_aclk : IN STD_LOGIC; + s00_axis_tx_aresetn : IN STD_LOGIC; + s00_axis_tx_tready : OUT STD_LOGIC; + s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s00_axis_tx_tvalid : IN STD_LOGIC + ); + END COMPONENT AXI4Stream_UART_v1_0; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF pak_depak_AXI4Stream_UART_0_0_arch: ARCHITECTURE IS "AXI4Stream_UART_v1_0,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF pak_depak_AXI4Stream_UART_0_0_arch : ARCHITECTURE IS "pak_depak_AXI4Stream_UART_0_0,AXI4Stream_UART_v1_0,{}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_tready: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX, WIZ_DATA_WIDTH 32, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S00_AXIS_TX TREADY"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXIS_TX_RST RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axis_tx_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXIS_TX_CLK, ASSOCIATED_BUSIF S00_AXIS_TX, ASSOCIATED_RESET s00_axis_tx_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s00_axis_tx_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXIS_TX_CLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_tvalid: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX, WIZ_DATA_WIDTH 32, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M00_AXIS_RX TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXIS_RX_RST RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axis_rx_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXIS_RX_CLK, ASSOCIATED_BUSIF M00_AXIS_RX, ASSOCIATED_RESET m00_axis_rx_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m00_axis_rx_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXIS_RX_CLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF UART_RX: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD"; + ATTRIBUTE X_INTERFACE_PARAMETER OF UART_TX: SIGNAL IS "XIL_INTERFACENAME UART, BOARD.ASSOCIATED_PARAM UART_BOARD_INTERFACE"; + ATTRIBUTE X_INTERFACE_INFO OF UART_TX: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD"; + ATTRIBUTE X_INTERFACE_PARAMETER OF rst: SIGNAL IS "XIL_INTERFACENAME reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF clk_uart: SIGNAL IS "XIL_INTERFACENAME ClockUART, ASSOCIATED_BUSIF UART, ASSOCIATED_RESET rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF clk_uart: SIGNAL IS "xilinx.com:signal:clock:1.0 ClockUART CLK"; +BEGIN + U0 : AXI4Stream_UART_v1_0 + GENERIC MAP ( + UART_BAUD_RATE => 115200, + UART_CLOCK_FREQUENCY => 100000000, + C_M00_AXIS_RX_TDATA_WIDTH => 8, + C_S00_AXIS_TX_TDATA_WIDTH => 8 + ) + PORT MAP ( + clk_uart => clk_uart, + rst => rst, + UART_TX => UART_TX, + UART_RX => UART_RX, + m00_axis_rx_aclk => m00_axis_rx_aclk, + m00_axis_rx_aresetn => m00_axis_rx_aresetn, + m00_axis_rx_tvalid => m00_axis_rx_tvalid, + m00_axis_rx_tdata => m00_axis_rx_tdata, + m00_axis_rx_tready => m00_axis_rx_tready, + s00_axis_tx_aclk => s00_axis_tx_aclk, + s00_axis_tx_aresetn => s00_axis_tx_aresetn, + s00_axis_tx_tready => s00_axis_tx_tready, + s00_axis_tx_tdata => s00_axis_tx_tdata, + s00_axis_tx_tvalid => s00_axis_tx_tvalid + ); +END pak_depak_AXI4Stream_UART_0_0_arch; diff --git a/LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1.v b/LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1.v new file mode 100644 index 0000000..c0dfb9e --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1.v @@ -0,0 +1,92 @@ + +// file: pak_depak_clk_wiz_0_1.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1__100.00000______0.000______50.0______130.958_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "pak_depak_clk_wiz_0_1,clk_wiz_v6_0_6_0_0,{component_name=pak_depak_clk_wiz_0_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) + +module pak_depak_clk_wiz_0_1 + ( + // Clock out ports + output clk_out1, + // Status and control signals + input reset, + output locked, + // Clock in ports + input clk_in1 + ); + + pak_depak_clk_wiz_0_1_clk_wiz inst + ( + // Clock out ports + .clk_out1(clk_out1), + // Status and control signals + .reset(reset), + .locked(locked), + // Clock in ports + .clk_in1(clk_in1) + ); + +endmodule diff --git a/LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1.xml b/LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1.xml new file mode 100644 index 0000000..961d8db --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1.xml @@ -0,0 +1,4855 @@ + + + xilinx.com + customized_ip + pak_depak_clk_wiz_0_1 + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 1 + + + none + + + + + HAS_LOCK + 1 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 1 + + + none + + + + + HAS_QOS + 1 + + + none + + + + + HAS_REGION + 1 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 1 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 256 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axi_aclk + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi_lite + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + ref_clk + ref_clk + + + + + + + CLK + + + ref_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axi_resetn + S_AXI_RESETN + + + + + + + RST + + + s_axi_aresetn + + + + + + ASSOCIATED_RESET + aresetn + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + intr + Intr + + + + + + + INTERRUPT + + + interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + CLK_IN1_D + CLK_IN1_D + Differential Clock input + + + + + + + CLK_N + + + clk_in1_n + + + + + CLK_P + + + clk_in1_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN1_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLK_IN2_D + CLK_IN2_D + Differential Clock input + + + + + + + CLK_N + + + clk_in2_n + + + + + CLK_P + + + clk_in2_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN2_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_IN_D + CLKFB_IN_D + Differential Feedback Clock input + + + + + + + CLK_N + + + clkfb_in_n + + + + + CLK_P + + + clkfb_in_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_OUT_D + CLKFB_OUT_D + Differential Feeback Clock Output + + + + + + + CLK_N + + + clkfb_out_n + + + + + CLK_P + + + clkfb_out_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + reset + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + true + + + + + + resetn + resetn + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + clock_CLK_IN1 + + + + + + + CLK_IN1 + + + clk_in1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + pak_depak_sys_clock + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN1_BOARD_INTERFACE + + + + + clock_CLK_OUT1 + + + + + + + CLK_OUT1 + + + clk_out1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_elaborateports + Elaborate Ports + :vivado.xilinx.com:elaborate.ports + + + outputProductCRC + 9:3db5dffe + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + clk_wiz_v6_0_6 + + xilinx_anylanguagesynthesis_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:02107661 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:02107661 + + + + + xilinx_anylanguagesynthesiswrapper + Synthesis Wrapper + :vivado.xilinx.com:synthesis.wrapper + pak_depak_clk_wiz_0_1 + + xilinx_anylanguagesynthesiswrapper_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:02107661 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + clk_wiz_v6_0_6 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:efd97062 + + + + + xilinx_anylanguagesimulationwrapper + Simulation Wrapper + :vivado.xilinx.com:simulation.wrapper + pak_depak_clk_wiz_0_1 + + xilinx_anylanguagesimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:efd97062 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:13 UTC 2025 + + + outputProductCRC + 9:02107661 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awaddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + 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xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in1_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in1_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in2_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in2_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clkfb_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clkfb_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clkfb_out_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clkfb_out_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + ref_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_stop + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_glitch + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + interrupt + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_oor + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + user_clk0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + user_clk1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + user_clk2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + user_clk3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_out1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + locked + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_CLKOUT2_USED + 0 + + + C_USER_CLK_FREQ0 + 100.0 + + + C_AUTO_PRIMITIVE + MMCM + + + C_USER_CLK_FREQ1 + 100.0 + + + C_USER_CLK_FREQ2 + 100.0 + + + C_USER_CLK_FREQ3 + 100.0 + + + C_ENABLE_CLOCK_MONITOR + 0 + + + C_ENABLE_USER_CLOCK0 + 0 + + + C_ENABLE_USER_CLOCK1 + 0 + + + C_ENABLE_USER_CLOCK2 + 0 + + + C_ENABLE_USER_CLOCK3 + 0 + + + C_Enable_PLL0 + 0 + + + C_Enable_PLL1 + 0 + + + C_REF_CLK_FREQ + 100.0 + + + C_PRECISION + 1 + + + C_CLKOUT3_USED + 0 + + + C_CLKOUT4_USED + 0 + + + C_CLKOUT5_USED + 0 + + + C_CLKOUT6_USED + 0 + + + C_CLKOUT7_USED + 0 + + + C_USE_CLKOUT1_BAR + 0 + + + C_USE_CLKOUT2_BAR + 0 + + + C_USE_CLKOUT3_BAR + 0 + + + C_USE_CLKOUT4_BAR + 0 + + + c_component_name + pak_depak_clk_wiz_0_1 + + + C_PLATFORM + UNKNOWN + + + C_USE_FREQ_SYNTH + 1 + + + C_USE_PHASE_ALIGNMENT + 1 + + + C_PRIM_IN_JITTER + 0.010 + + + C_SECONDARY_IN_JITTER + 0.010 + + + C_JITTER_SEL + No_Jitter + + + C_USE_MIN_POWER + 0 + + + C_USE_MIN_O_JITTER + 0 + + + C_USE_MAX_I_JITTER + 0 + + + C_USE_DYN_PHASE_SHIFT + 0 + + + C_USE_INCLK_SWITCHOVER + 0 + + + C_USE_DYN_RECONFIG + 0 + + + C_USE_SPREAD_SPECTRUM + 0 + + + C_USE_FAST_SIMULATION + 0 + + + C_PRIMTYPE_SEL + AUTO + + + C_USE_CLK_VALID + 0 + + + C_PRIM_IN_FREQ + 100.000 + + + C_PRIM_IN_TIMEPERIOD + 10.000 + + + C_IN_FREQ_UNITS + Units_MHz + + + C_SECONDARY_IN_FREQ + 100.000 + + + C_SECONDARY_IN_TIMEPERIOD + 10.000 + + + C_FEEDBACK_SOURCE + FDBK_AUTO + + + C_PRIM_SOURCE + Single_ended_clock_capable_pin + + + C_PHASESHIFT_MODE + WAVEFORM + + + C_SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + C_CLKFB_IN_SIGNALING + SINGLE + + + C_USE_RESET + 1 + + + C_RESET_LOW + 0 + + + C_USE_LOCKED + 1 + + + C_USE_INCLK_STOPPED + 0 + + + C_USE_CLKFB_STOPPED + 0 + + + C_USE_POWER_DOWN + 0 + + + C_USE_STATUS + 0 + + + C_USE_FREEZE + 0 + + + C_NUM_OUT_CLKS + 1 + + + C_CLKOUT1_DRIVES + BUFG + + + C_CLKOUT2_DRIVES + BUFG + + + C_CLKOUT3_DRIVES + BUFG + + + C_CLKOUT4_DRIVES + BUFG + + + C_CLKOUT5_DRIVES + BUFG + + + C_CLKOUT6_DRIVES + BUFG + + + C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________100.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_out1__100.00000______0.000______50.0______130.958_____98.575 + + + C_OUTCLK_SUM_ROW2 + no_CLK_OUT2_output + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 100.00000 + + + C_CLKOUT2_OUT_FREQ + 100.000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 10.000 + + + C_MMCM_CLKIN1_PERIOD + 10.000 + + + C_MMCM_CLKIN2_PERIOD + 10.000 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + ZHOLD + + + C_MMCM_DIVCLK_DIVIDE + 1 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 10.000 + + + C_MMCM_CLKOUT1_DIVIDE + 1 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_out1 + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 100.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 1.0 + + + C_DIVIDE3_AUTO + 1.0 + + + C_DIVIDE4_AUTO + 1.0 + + + C_DIVIDE5_AUTO + 1.0 + + + C_DIVIDE6_AUTO + 1.0 + + + C_DIVIDE7_AUTO + 1.0 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 100.00000 + + + C_CLKOUT1_ACTUAL_FREQ + 100.000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + C_M_MAX + 64.000 + + + C_M_MIN + 2.000 + + + C_D_MAX + 80.000 + + + C_D_MIN + 1.000 + + + C_O_MAX + 128.000 + + + C_O_MIN + 1.000 + + + C_VCO_MIN + 600.000 + + + C_VCO_MAX + 1200.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_ce26ebdb + Custom + reset + + + choice_list_e099fe6c + MMCM + PLL + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_502d9f23 + ZHOLD + EXTERNAL + INTERNAL + BUF_IN + + + choice_pairs_66e4c81f + BUFG + BUFH + BUFGCE + BUFHCE + No_buffer + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_c6542ce1 + Custom + sys_clock + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + + + xilinx_anylanguagesynthesis_view_fileset + + pak_depak_clk_wiz_0_1.xdc + xdc + + processing_order + early + + + + pak_depak_clk_wiz_0_1_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + ../../ipshared/d0f7/mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_7s_pll.vh + verilogSource + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_us_mmcm.vh + verilogSource + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_us_pll.vh + verilogSource + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + true + clk_wiz_v6_0_6 + + + pak_depak_clk_wiz_0_1_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesynthesiswrapper_view_fileset + + pak_depak_clk_wiz_0_1.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/d0f7/mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_7s_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_us_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_us_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_6 + + + ../../ipshared/d0f7/mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_6 + + + pak_depak_clk_wiz_0_1_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesimulationwrapper_view_fileset + + pak_depak_clk_wiz_0_1.v + verilogSource + + + + xilinx_implementation_view_fileset + + pak_depak_clk_wiz_0_1_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + pak_depak_clk_wiz_0_1 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + true + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 100.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 100.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + false + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 1 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_out1 + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + Single_ended_clock_capable_pin + + + CLKOUT1_DRIVES + BUFG + + + CLKOUT2_DRIVES + BUFG + + + CLKOUT3_DRIVES + BUFG + + + CLKOUT4_DRIVES + BUFG + + + CLKOUT5_DRIVES + BUFG + + + CLKOUT6_DRIVES + BUFG + + + CLKOUT7_DRIVES + BUFG + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + true + + + CALC_DONE + empty + + + USE_RESET + true + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 1 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 10.000 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 10.000 + + + MMCM_CLKIN2_PERIOD + 10.000 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + ZHOLD + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 10.000 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 1 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + true + + + CLK_IN1_BOARD_INTERFACE + sys_clock + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + MMCM + + + RESET_BOARD_INTERFACE + reset + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 130.958 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 98.575 + + + CLKOUT2_JITTER + Clkout2 Jitter + 0.0 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 0.0 + + + CLKOUT3_JITTER + Clkout3 Jitter + 0.0 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 0.0 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 6 + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1_clk_wiz.v b/LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1_clk_wiz.v new file mode 100644 index 0000000..efb6963 --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_clk_wiz_0_1/pak_depak_clk_wiz_0_1_clk_wiz.v @@ -0,0 +1,204 @@ + +// file: pak_depak_clk_wiz_0_1.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1__100.00000______0.000______50.0______130.958_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +module pak_depak_clk_wiz_0_1_clk_wiz + + (// Clock in ports + // Clock out ports + output clk_out1, + // Status and control signals + input reset, + output locked, + input clk_in1 + ); + // Input buffering + //------------------------------------ +wire clk_in1_pak_depak_clk_wiz_0_1; +wire clk_in2_pak_depak_clk_wiz_0_1; + IBUF clkin1_ibufg + (.O (clk_in1_pak_depak_clk_wiz_0_1), + .I (clk_in1)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire clk_out1_pak_depak_clk_wiz_0_1; + wire clk_out2_pak_depak_clk_wiz_0_1; + wire clk_out3_pak_depak_clk_wiz_0_1; + wire clk_out4_pak_depak_clk_wiz_0_1; + wire clk_out5_pak_depak_clk_wiz_0_1; + wire clk_out6_pak_depak_clk_wiz_0_1; + wire clk_out7_pak_depak_clk_wiz_0_1; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire locked_int; + wire clkfbout_pak_depak_clk_wiz_0_1; + wire clkfbout_buf_pak_depak_clk_wiz_0_1; + wire clkfboutb_unused; + wire clkout0b_unused; + wire clkout1_unused; + wire clkout1b_unused; + wire clkout2_unused; + wire clkout2b_unused; + wire clkout3_unused; + wire clkout3b_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + wire reset_high; + + MMCME2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (10.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (10.000), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (10.000)) + mmcm_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_pak_depak_clk_wiz_0_1), + .CLKFBOUTB (clkfboutb_unused), + .CLKOUT0 (clk_out1_pak_depak_clk_wiz_0_1), + .CLKOUT0B (clkout0b_unused), + .CLKOUT1 (clkout1_unused), + .CLKOUT1B (clkout1b_unused), + .CLKOUT2 (clkout2_unused), + .CLKOUT2B (clkout2b_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT3B (clkout3b_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .CLKOUT6 (clkout6_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_pak_depak_clk_wiz_0_1), + .CLKIN1 (clk_in1_pak_depak_clk_wiz_0_1), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (psdone_unused), + // Other control and status signals + .LOCKED (locked_int), + .CLKINSTOPPED (clkinstopped_unused), + .CLKFBSTOPPED (clkfbstopped_unused), + .PWRDWN (1'b0), + .RST (reset_high)); + assign reset_high = reset; + + assign locked = locked_int; +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_pak_depak_clk_wiz_0_1), + .I (clkfbout_pak_depak_clk_wiz_0_1)); + + + + + + + BUFG clkout1_buf + (.O (clk_out1), + .I (clk_out1_pak_depak_clk_wiz_0_1)); + + + + +endmodule diff --git a/LAB2/src/pak_depak/ip/pak_depak_depacketizer_0_0/pak_depak_depacketizer_0_0.xml b/LAB2/src/pak_depak/ip/pak_depak_depacketizer_0_0/pak_depak_depacketizer_0_0.xml new file mode 100644 index 0000000..d053c97 --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_depacketizer_0_0/pak_depak_depacketizer_0_0.xml @@ -0,0 +1,626 @@ + + + xilinx.com + customized_ip + pak_depak_depacketizer_0_0 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + clk + + in + + + STD_LOGIC + dummy_view + + + + + + aresetn + + in + + + STD_LOGIC + dummy_view + + + + + + s_axis_tdata + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + 0 + + + + + s_axis_tvalid + + in + + + STD_LOGIC + dummy_view + + + + + + s_axis_tready + + out + + + STD_LOGIC + dummy_view + + + + + + m_axis_tdata + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + dummy_view + + + + + + m_axis_tready + + in + + + STD_LOGIC + dummy_view + + + + 1 + + + + + m_axis_tlast + + out + + + STD_LOGIC + dummy_view + + + + + + + + HEADER + Header + 255 + + + FOOTER + Footer + 241 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + xilinx.com:module_ref:depacketizer:1.0 + + + HEADER + Header + 255 + + + FOOTER + Footer + 241 + + + Component_Name + pak_depak_depacketizer_0_0 + + + + + depacketizer_v1_0 + module_ref + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + diff --git a/LAB2/src/pak_depak/ip/pak_depak_packetizer_0_0/pak_depak_packetizer_0_0.xml b/LAB2/src/pak_depak/ip/pak_depak_packetizer_0_0/pak_depak_packetizer_0_0.xml new file mode 100644 index 0000000..9941eaa --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_packetizer_0_0/pak_depak_packetizer_0_0.xml @@ -0,0 +1,649 @@ + + + xilinx.com + customized_ip + pak_depak_packetizer_0_0 + 1.0 + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + TDATA_NUM_BYTES + 1 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 1 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 1 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + aresetn + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + m_axis:s_axis + + + ASSOCIATED_RESET + aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + clk + + in + + + STD_LOGIC + dummy_view + + + + + + aresetn + + in + + + STD_LOGIC + dummy_view + + + + + + s_axis_tdata + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + 0 + + + + + s_axis_tvalid + + in + + + STD_LOGIC + dummy_view + + + + + + s_axis_tready + + out + + + STD_LOGIC + dummy_view + + + + + + s_axis_tlast + + in + + + STD_LOGIC + dummy_view + + + + 0 + + + + + m_axis_tdata + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + dummy_view + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + dummy_view + + + + + + m_axis_tready + + in + + + STD_LOGIC + dummy_view + + + + 1 + + + + + m_axis_tlast + + out + + + STD_LOGIC + dummy_view + + + + + + + + HEADER + Header + 255 + + + FOOTER + Footer + 241 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + xilinx.com:module_ref:packetizer:1.0 + + + HEADER + Header + 255 + + + FOOTER + Footer + 241 + + + Component_Name + pak_depak_packetizer_0_0 + + + + + packetizer_v1_0 + module_ref + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + diff --git a/LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/pak_depak_proc_sys_reset_0_0.xml b/LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/pak_depak_proc_sys_reset_0_0.xml new file mode 100644 index 0000000..30b971f --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/pak_depak_proc_sys_reset_0_0.xml @@ -0,0 +1,900 @@ + + + xilinx.com + customized_ip + pak_depak_proc_sys_reset_0_0 + 1.0 + + + clock + Clock + + + + + + + CLK + + + slowest_sync_clk + + + + + + ASSOCIATED_RESET + mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset + + + FREQ_HZ + Slowest Sync clock frequency + Slowest Synchronous clock frequency + 100000000 + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + ext_reset + Ext_Reset + + + + + + + RST + + + ext_reset_in + + + + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + required + + + + + + POLARITY + ACTIVE_HIGH + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + aux_reset + aux_reset + + + + + + + RST + + + aux_reset_in + + + + + + POLARITY + ACTIVE_LOW + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + dbg_reset + DBG_Reset + + + + + + + RST + + + mb_debug_sys_rst + + + + + + POLARITY + ACTIVE_HIGH + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + mb_rst + MB_rst + + + + + + + RST + + + mb_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PROCESSOR + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + bus_struct_reset + bus_struct_reset + + + + + + + RST + + + bus_struct_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + interconnect_low_rst + interconnect_low_rst + + + + + + + RST + + + interconnect_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + INTERCONNECT + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + peripheral_high_rst + peripheral_high_rst + + + + + + + RST + + + peripheral_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + peripheral_low_rst + peripheral_low_rst + + + + + + + RST + + + peripheral_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + PERIPHERAL + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + proc_sys_reset + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:12 UTC 2025 + + + outputProductCRC + 9:615ca7b1 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:615ca7b1 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + pak_depak_proc_sys_reset_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:12 UTC 2025 + + + outputProductCRC + 9:615ca7b1 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + proc_sys_reset + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:12 UTC 2025 + + + outputProductCRC + 9:b3cbf1ce + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + pak_depak_proc_sys_reset_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:12 UTC 2025 + + + outputProductCRC + 9:b3cbf1ce + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Mon Apr 14 13:11:12 UTC 2025 + + + outputProductCRC + 9:615ca7b1 + + + + + + + slowest_sync_clk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + ext_reset_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + aux_reset_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + mb_debug_sys_rst + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + dcm_locked + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + mb_reset + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + bus_struct_reset + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + peripheral_reset + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + interconnect_aresetn + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + peripheral_aresetn + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + + C_FAMILY + artix7 + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RESET_HIGH + Ext Reset High + 1 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + + + + choice_list_ce26ebdb + Custom + reset + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd + vhdlSource + lib_cdc_v1_0_2 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + ../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd + vhdlSource + proc_sys_reset_v5_0_13 + + + pak_depak_proc_sys_reset_0_0.xdc + xdc + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/pak_depak_proc_sys_reset_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd + vhdlSource + USED_IN_ipstatic + lib_cdc_v1_0_2 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + proc_sys_reset_v5_0_13 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/pak_depak_proc_sys_reset_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_implementation_view_fileset + + pak_depak_proc_sys_reset_0_0_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + Processor Reset System + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_EXT_RESET_HIGH + Ext Reset High + 1 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + Component_Name + pak_depak_proc_sys_reset_0_0 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + true + + + RESET_BOARD_INTERFACE + reset + + + + + Processor System Reset + 13 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + + + + + + diff --git a/LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/sim/pak_depak_proc_sys_reset_0_0.vhd b/LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/sim/pak_depak_proc_sys_reset_0_0.vhd new file mode 100644 index 0000000..b7c9ac7 --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/sim/pak_depak_proc_sys_reset_0_0.vhd @@ -0,0 +1,147 @@ +-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 +-- IP Revision: 13 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY proc_sys_reset_v5_0_13; +USE proc_sys_reset_v5_0_13.proc_sys_reset; + +ENTITY pak_depak_proc_sys_reset_0_0 IS + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END pak_depak_proc_sys_reset_0_0; + +ARCHITECTURE pak_depak_proc_sys_reset_0_0_arch OF pak_depak_proc_sys_reset_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF pak_depak_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT proc_sys_reset IS + GENERIC ( + C_FAMILY : STRING; + C_EXT_RST_WIDTH : INTEGER; + C_AUX_RST_WIDTH : INTEGER; + C_EXT_RESET_HIGH : STD_LOGIC; + C_AUX_RESET_HIGH : STD_LOGIC; + C_NUM_BUS_RST : INTEGER; + C_NUM_PERP_RST : INTEGER; + C_NUM_INTERCONNECT_ARESETN : INTEGER; + C_NUM_PERP_ARESETN : INTEGER + ); + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT proc_sys_reset; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; +BEGIN + U0 : proc_sys_reset + GENERIC MAP ( + C_FAMILY => "artix7", + C_EXT_RST_WIDTH => 4, + C_AUX_RST_WIDTH => 4, + C_EXT_RESET_HIGH => '1', + C_AUX_RESET_HIGH => '0', + C_NUM_BUS_RST => 1, + C_NUM_PERP_RST => 1, + C_NUM_INTERCONNECT_ARESETN => 1, + C_NUM_PERP_ARESETN => 1 + ) + PORT MAP ( + slowest_sync_clk => slowest_sync_clk, + ext_reset_in => ext_reset_in, + aux_reset_in => aux_reset_in, + mb_debug_sys_rst => mb_debug_sys_rst, + dcm_locked => dcm_locked, + mb_reset => mb_reset, + bus_struct_reset => bus_struct_reset, + peripheral_reset => peripheral_reset, + interconnect_aresetn => interconnect_aresetn, + peripheral_aresetn => peripheral_aresetn + ); +END pak_depak_proc_sys_reset_0_0_arch; diff --git a/LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/synth/pak_depak_proc_sys_reset_0_0.vhd b/LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/synth/pak_depak_proc_sys_reset_0_0.vhd new file mode 100644 index 0000000..6248b10 --- /dev/null +++ b/LAB2/src/pak_depak/ip/pak_depak_proc_sys_reset_0_0/synth/pak_depak_proc_sys_reset_0_0.vhd @@ -0,0 +1,153 @@ +-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 +-- IP Revision: 13 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY proc_sys_reset_v5_0_13; +USE proc_sys_reset_v5_0_13.proc_sys_reset; + +ENTITY pak_depak_proc_sys_reset_0_0 IS + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END pak_depak_proc_sys_reset_0_0; + +ARCHITECTURE pak_depak_proc_sys_reset_0_0_arch OF pak_depak_proc_sys_reset_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF pak_depak_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT proc_sys_reset IS + GENERIC ( + C_FAMILY : STRING; + C_EXT_RST_WIDTH : INTEGER; + C_AUX_RST_WIDTH : INTEGER; + C_EXT_RESET_HIGH : STD_LOGIC; + C_AUX_RESET_HIGH : STD_LOGIC; + C_NUM_BUS_RST : INTEGER; + C_NUM_PERP_RST : INTEGER; + C_NUM_INTERCONNECT_ARESETN : INTEGER; + C_NUM_PERP_ARESETN : INTEGER + ); + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT proc_sys_reset; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF pak_depak_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2020.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF pak_depak_proc_sys_reset_0_0_arch : ARCHITECTURE IS "pak_depak_proc_sys_reset_0_0,proc_sys_reset,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF pak_depak_proc_sys_reset_0_0_arch: ARCHITECTURE IS "pak_depak_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; +BEGIN + U0 : proc_sys_reset + GENERIC MAP ( + C_FAMILY => "artix7", + C_EXT_RST_WIDTH => 4, + C_AUX_RST_WIDTH => 4, + C_EXT_RESET_HIGH => '1', + C_AUX_RESET_HIGH => '0', + C_NUM_BUS_RST => 1, + C_NUM_PERP_RST => 1, + C_NUM_INTERCONNECT_ARESETN => 1, + C_NUM_PERP_ARESETN => 1 + ) + PORT MAP ( + slowest_sync_clk => slowest_sync_clk, + ext_reset_in => ext_reset_in, + aux_reset_in => aux_reset_in, + mb_debug_sys_rst => mb_debug_sys_rst, + dcm_locked => dcm_locked, + mb_reset => mb_reset, + bus_struct_reset => bus_struct_reset, + peripheral_reset => peripheral_reset, + interconnect_aresetn => interconnect_aresetn, + peripheral_aresetn => peripheral_aresetn + ); +END pak_depak_proc_sys_reset_0_0_arch; diff --git a/LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0.vhd b/LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0.vhd new file mode 100644 index 0000000..2561dec --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0.vhd @@ -0,0 +1,398 @@ + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ---- * ) ---- + ----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ---- + ---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ---- + ----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ---- + ----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ---- + ---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ---- + ---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ---- + ---- |___/ |___/ ---- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +---- _____ _ ___ __ _ _ _ __ _ ---- +---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ---- +---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ---- +---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ---- +---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ---- +----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ---- +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ + +-------------------------------------DESCRIPTION------------------------------------------ +------------------------------------------------------------------------------------------ +-- Bridge FT245Async to AXI4-Stream. -- +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library xpm; + use xpm.vcomponents.all; + +entity AXI4Stream_UART_v1_0 is + generic ( + ------------------UART PARAMETER------------------- + UART_BAUD_RATE : positive := 115_200; + UART_CLOCK_FREQUENCY : positive := 100_000_000; --The associated clock frequency + ---------------------------------------------------- + + -- Parameters of Axi Master Bus Interface M00_AXIS_RX + C_M00_AXIS_RX_TDATA_WIDTH : integer := 8; + -- Parameters of Axi Slave Bus Interface S00_AXIS_TX + C_S00_AXIS_TX_TDATA_WIDTH : integer := 8 + ); + port ( + ---------Global--------- + clk_uart : IN STD_LOGIC; + rst : IN STD_LOGIC; + ------------------------ + + ---------Connessioni comunicazione UART----------- + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + --------------------------------------------------- + + ---Ports of Axi Master Bus Interface M00_AXIS_RX--- + m00_axis_rx_aclk : IN STD_LOGIC; + m00_axis_rx_aresetn : IN STD_LOGIC; + m00_axis_rx_tvalid : OUT STD_LOGIC; + m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(C_M00_AXIS_RX_TDATA_WIDTH-1 DOWNTO 0); + m00_axis_rx_tready : IN STD_LOGIC; + -------------------------------------------------- + ---Ports of Axi Slave Bus Interface S00_AXIS_TX--- + s00_axis_tx_aclk : IN STD_LOGIC; + s00_axis_tx_aresetn : IN STD_LOGIC; + s00_axis_tx_tready : OUT STD_LOGIC; + s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(C_S00_AXIS_TX_TDATA_WIDTH-1 DOWNTO 0); + s00_axis_tx_tvalid : IN STD_LOGIC + -------------------------------------------------- + ); +end AXI4Stream_UART_v1_0; + +architecture arch_imp of AXI4Stream_UART_v1_0 is + + --------------------------------COMPONENTS DECLARATION----------------------------------- + component UART_Manager is + generic( + UART_BAUD_RATE : positive; + UART_CLOCK_FREQUENCY : positive --The associated clock frequency + ); + Port ( + ---------Global--------- + clk_uart : IN STD_LOGIC; + reset : IN STD_LOGIC; + ------------------------ + + ---------Connessioni comunicazione UART----------- + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + --------------------------------------------------- + + ------------FIFO_DATA_RX (8bit)------------- + FIFO_DATA_RX_rst : OUT STD_LOGIC; + FIFO_DATA_RX_clk : OUT STD_LOGIC; + FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_RX_wr_en : OUT STD_LOGIC; + FIFO_DATA_RX_full : IN STD_LOGIC; + FIFO_DATA_RX_almost_full : IN STD_LOGIC; + -------------------------------------------- + + ------------FIFO_DATA_TX (8bit)------------- + --FIFO_DATA_RX_rst : OUT STD_LOGIC; + FIFO_DATA_TX_clk : OUT STD_LOGIC; + FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_TX_rd_en : OUT STD_LOGIC; + FIFO_DATA_TX_empty : IN STD_LOGIC; + FIFO_DATA_TX_almost_empty : IN STD_LOGIC + -------------------------------------------- + ); + end component UART_Manager; + + component AXI4Stream_UART_v1_0_M00_AXIS_RX is + generic ( + -- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + C_M_AXIS_TDATA_WIDTH : integer := 8 + ); + port ( + --------------FIFO_DATA (8bit)-------------- + --FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO + FIFO_DATA_clk : OUT STD_LOGIC; + FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_rd_en : OUT STD_LOGIC; + FIFO_DATA_empty : IN STD_LOGIC; + FIFO_DATA_almost_empty : IN STD_LOGIC; + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream Clock + M_AXIS_ACLK : IN STD_LOGIC; + -- AXI4Stream Reset + M_AXIS_ARESETN : IN STD_LOGIC; + -- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + M_AXIS_TVALID : OUT STD_LOGIC; + -- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0); + -- TREADY indicates that the slave can accept a transfer in the current cycle. + M_AXIS_TREADY : IN STD_LOGIC + -------------------------------------------- + ); + end component AXI4Stream_UART_v1_0_M00_AXIS_RX; + + component AXI4Stream_UART_v1_0_S00_AXIS_TX is + generic ( + -- AXI4Stream sink: Data Width + C_S_AXIS_TDATA_WIDTH : integer := 8 + ); + port ( + + --------------FIFO_DATA------------- + FIFO_DATA_rst : OUT STD_LOGIC; + FIFO_DATA_clk : OUT STD_LOGIC; + FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0); + FIFO_DATA_wr_en : OUT STD_LOGIC; + FIFO_DATA_full : IN STD_LOGIC; + FIFO_DATA_almost_full : IN STD_LOGIC; + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream sink: Clock + S_AXIS_ACLK : IN STD_LOGIC; + -- AXI4Stream sink: Reset + S_AXIS_ARESETN : IN STD_LOGIC; + -- Ready to accept data in + S_AXIS_TREADY : OUT STD_LOGIC; + -- Data in + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0); + -- Data is in valid + S_AXIS_TVALID : IN STD_LOGIC + -------------------------------------------- + ); + end component AXI4Stream_UART_v1_0_S00_AXIS_TX; + ----------------------------------------------------------------------------------------- + + ---------------------------------------SIGNALS------------------------------------------- + -----------------FIFO_DATA_RX----------------- + signal FIFO_DATA_RX_rst : STD_LOGIC; + signal FIFO_DATA_RX_wr_clk : STD_LOGIC; + signal FIFO_DATA_RX_rd_clk : STD_LOGIC; + signal FIFO_DATA_RX_din : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal FIFO_DATA_RX_wr_en : STD_LOGIC; + signal FIFO_DATA_RX_rd_en : STD_LOGIC; + signal FIFO_DATA_RX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal FIFO_DATA_RX_full : STD_LOGIC; + signal FIFO_DATA_RX_almost_full : STD_LOGIC; + signal FIFO_DATA_RX_empty : STD_LOGIC; + signal FIFO_DATA_RX_almost_empty : STD_LOGIC; + ---------------------------------------------- + + -----------------FIFO_DATA_TX----------------- + signal FIFO_DATA_TX_rst : STD_LOGIC; + signal FIFO_DATA_TX_wr_clk : STD_LOGIC; + signal FIFO_DATA_TX_rd_clk : STD_LOGIC; + signal FIFO_DATA_TX_din : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal FIFO_DATA_TX_wr_en : STD_LOGIC; + signal FIFO_DATA_TX_rd_en : STD_LOGIC; + signal FIFO_DATA_TX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal FIFO_DATA_TX_full : STD_LOGIC; + signal FIFO_DATA_TX_almost_full : STD_LOGIC; + signal FIFO_DATA_TX_empty : STD_LOGIC; + signal FIFO_DATA_TX_almost_empty : STD_LOGIC; + ---------------------------------------------- + + ----------------------------------------------------------------------------------------- + +begin + + -----------------------MODULE INSTANTIATION------------------------- + AXI4Stream_UART_v1_0_S00_AXIS_TX_inst : AXI4Stream_UART_v1_0_S00_AXIS_TX + generic map( + -- AXI4Stream sink: Data Width + C_S_AXIS_TDATA_WIDTH => C_S00_AXIS_TX_TDATA_WIDTH + ) + port map( + + --------------FIFO_DATA------------- + FIFO_DATA_rst => FIFO_DATA_TX_rst, + FIFO_DATA_clk => FIFO_DATA_TX_wr_clk, + FIFO_DATA_din => FIFO_DATA_TX_din, + FIFO_DATA_wr_en => FIFO_DATA_TX_wr_en, + FIFO_DATA_full => FIFO_DATA_TX_full, + FIFO_DATA_almost_full => FIFO_DATA_TX_almost_full, + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream sink: Clock + S_AXIS_ACLK => s00_axis_tx_aclk, + -- AXI4Stream sink: Reset + S_AXIS_ARESETN => s00_axis_tx_aresetn, + -- Ready to accept data in + S_AXIS_TREADY => s00_axis_tx_tready, + -- Data in + S_AXIS_TDATA => s00_axis_tx_tdata, + -- Data is in valid + S_AXIS_TVALID => s00_axis_tx_tvalid + -------------------------------------------- + ); + + -- xpm_fifo_async: Asynchronous FIFO + -- Xilinx Parameterized Macro, Version 2017.3 + FIFO_DATA_TX : xpm_fifo_async + generic map ( + FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra"; + FIFO_WRITE_DEPTH => 2048, --positive integer; + RELATED_CLOCKS => 0, --positive integer; 0 or 1; + WRITE_DATA_WIDTH => 8, --positive integer; + WR_DATA_COUNT_WIDTH => 1, --positive integer; + READ_MODE => "fwft", --string; "std" or "fwft"; + FIFO_READ_LATENCY => 0, --positive integer; + --FULL_RESET_VALUE => 0, --positive integer; 0 or 1; + READ_DATA_WIDTH => 8, --positive integer; + RD_DATA_COUNT_WIDTH => 1, --positive integer; + CDC_SYNC_STAGES => 2, --positive integer; + ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; + --PROG_FULL_THRESH => 10, --positive integer + --PROG_EMPTY_THRESH => 10, --positive integer + --DOUT_RESET_VALUE => "0", --string + WAKEUP_TIME => 0, --positive integer; 0 or 2; + USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty + ) + port map ( + wr_clk => FIFO_DATA_TX_wr_clk, + wr_en => FIFO_DATA_TX_wr_en, + din => FIFO_DATA_TX_din, + full => FIFO_DATA_TX_full, + overflow => open, + wr_rst_busy => open, + sleep => '0', + rst => FIFO_DATA_TX_rst, + rd_clk => FIFO_DATA_TX_rd_clk, + rd_en => FIFO_DATA_TX_rd_en, + dout => FIFO_DATA_TX_dout, + empty => FIFO_DATA_TX_empty, + underflow => open, + rd_rst_busy => open, + injectsbiterr => '0', + injectdbiterr => '0', + almost_full => FIFO_DATA_TX_almost_full, + almost_empty => FIFO_DATA_TX_almost_empty + ); + + UART_Manager_inst : UART_Manager + Generic map( + UART_BAUD_RATE => UART_BAUD_RATE, + UART_CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY + ) + Port map( + ---------Global--------- + clk_uart => clk_uart, + reset => rst, + ------------------------ + + ---------Connessioni comunicazione UART----------- + UART_TX => UART_TX, + UART_RX => UART_RX, + --------------------------------------------------- + + ------------FIFO_DATA_RX (8bit)------------- + FIFO_DATA_RX_rst => FIFO_DATA_RX_rst, + FIFO_DATA_RX_clk => FIFO_DATA_RX_wr_clk, + FIFO_DATA_RX_din => FIFO_DATA_RX_din, + FIFO_DATA_RX_wr_en => FIFO_DATA_RX_wr_en, + FIFO_DATA_RX_full => FIFO_DATA_RX_full, + FIFO_DATA_RX_almost_full => FIFO_DATA_RX_almost_full, + -------------------------------------------- + + ------------FIFO_DATA_TX (8bit)------------- + FIFO_DATA_TX_clk => FIFO_DATA_TX_rd_clk, + FIFO_DATA_TX_dout => FIFO_DATA_TX_dout, + FIFO_DATA_TX_rd_en => FIFO_DATA_TX_rd_en, + FIFO_DATA_TX_empty => FIFO_DATA_TX_empty, + FIFO_DATA_TX_almost_empty => FIFO_DATA_TX_almost_empty + -------------------------------------------- + ); + + -- xpm_fifo_async: Asynchronous FIFO + -- Xilinx Parameterized Macro, Version 2017.3 + FIFO_DATA_RX : xpm_fifo_async + generic map ( + FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra"; + FIFO_WRITE_DEPTH => 2048, --positive integer; + RELATED_CLOCKS => 0, --positive integer; 0 or 1; + WRITE_DATA_WIDTH => 8, --positive integer; + WR_DATA_COUNT_WIDTH => 1, --positive integer; + READ_MODE => "fwft", --string; "std" or "fwft"; + FIFO_READ_LATENCY => 0, --positive integer; + --FULL_RESET_VALUE => 0, --positive integer; 0 or 1; + READ_DATA_WIDTH => 8, --positive integer; + RD_DATA_COUNT_WIDTH => 1, --positive integer; + CDC_SYNC_STAGES => 2, --positive integer; + ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; + --PROG_FULL_THRESH => 10, --positive integer + --PROG_EMPTY_THRESH => 10, --positive integer + --DOUT_RESET_VALUE => "0", --string + WAKEUP_TIME => 0, --positive integer; 0 or 2; + USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty + ) + port map ( + wr_clk => FIFO_DATA_RX_wr_clk, + wr_en => FIFO_DATA_RX_wr_en, + din => FIFO_DATA_RX_din, + full => FIFO_DATA_RX_full, + overflow => open, + wr_rst_busy => open, + sleep => '0', + rst => FIFO_DATA_RX_rst, + rd_clk => FIFO_DATA_RX_rd_clk, + rd_en => FIFO_DATA_RX_rd_en, + dout => FIFO_DATA_RX_dout, + empty => FIFO_DATA_RX_empty, + underflow => open, + rd_rst_busy => open, + injectsbiterr => '0', + injectdbiterr => '0', + almost_full => FIFO_DATA_RX_almost_full, + almost_empty => FIFO_DATA_RX_almost_empty + ); + + AXI4Stream_UART_v1_0_M00_AXIS_RX_inst : AXI4Stream_UART_v1_0_M00_AXIS_RX + generic map( + -- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + C_M_AXIS_TDATA_WIDTH => C_M00_AXIS_RX_TDATA_WIDTH + + ) + port map( + --------------FIFO_DATA (8bit)-------------- + FIFO_DATA_clk => FIFO_DATA_RX_rd_clk, + FIFO_DATA_dout => FIFO_DATA_RX_dout, + FIFO_DATA_rd_en => FIFO_DATA_RX_rd_en, + FIFO_DATA_empty => FIFO_DATA_RX_empty, + FIFO_DATA_almost_empty => FIFO_DATA_RX_almost_empty, + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream Clock + M_AXIS_ACLK => m00_axis_rx_aclk, + -- AXI4Stream Reset + M_AXIS_ARESETN => m00_axis_rx_aresetn, + -- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + M_AXIS_TVALID => m00_axis_rx_tvalid, + -- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + M_AXIS_TDATA => m00_axis_rx_tdata, + -- TREADY indicates that the slave can accept a transfer in the current cycle. + M_AXIS_TREADY => m00_axis_rx_tready + -------------------------------------------- + ); + + -------------------------------------------------------------------- + +end arch_imp; diff --git a/LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd b/LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd new file mode 100644 index 0000000..5353ffd --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd @@ -0,0 +1,91 @@ + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ---- * ) ---- + ----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ---- + ---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ---- + ----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ---- + ----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ---- + ---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ---- + ---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ---- + ---- |___/ |___/ ---- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +---- _____ _ ___ __ _ _ _ __ _ ---- +---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ---- +---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ---- +---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ---- +---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ---- +----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ---- +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ + +-------------------------------------DESCRIPTION------------------------------------------ +------------------------------------------------------------------------------------------ +-- Bridge da FIFO 8bit to AXI4 Stream. -- +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity AXI4Stream_UART_v1_0_M00_AXIS_RX is + generic ( + -- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + C_M_AXIS_TDATA_WIDTH : integer := 8 + ); + port ( + --------------FIFO_DATA (8bit)-------------- + --FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO + FIFO_DATA_clk : OUT STD_LOGIC; + FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_rd_en : OUT STD_LOGIC; + FIFO_DATA_empty : IN STD_LOGIC; + FIFO_DATA_almost_empty : IN STD_LOGIC; + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream Clock + M_AXIS_ACLK : IN STD_LOGIC; + -- AXI4Stream Reset + M_AXIS_ARESETN : IN STD_LOGIC; + -- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + M_AXIS_TVALID : OUT STD_LOGIC; + -- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0); + -- TREADY indicates that the slave can accept a transfer in the current cycle. + M_AXIS_TREADY : IN STD_LOGIC + -------------------------------------------- + ); +end AXI4Stream_UART_v1_0_M00_AXIS_RX; + +architecture implementation of AXI4Stream_UART_v1_0_M00_AXIS_RX is + + ----------------------------SIGNALS----------------------------- + signal M_AXIS_TVALID_int : STD_LOGIC; + ---------------------------------------------------------------- + +begin + + ---------DIRECT ASSIGNMENT---------- + FIFO_DATA_clk <= M_AXIS_ACLK; + --FIFO_DATA_rst <= not M_AXIS_ARESETN; + + M_AXIS_TDATA <= FIFO_DATA_dout; + + FIFO_DATA_rd_en <= M_AXIS_TREADY and M_AXIS_TVALID_int; + + M_AXIS_TVALID_int <= not FIFO_DATA_empty and M_AXIS_ARESETN; + M_AXIS_TVALID <= M_AXIS_TVALID_int; + + ------------------------------------ + +end implementation; \ No newline at end of file diff --git a/LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd b/LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd new file mode 100644 index 0000000..4ff7986 --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd @@ -0,0 +1,90 @@ + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ---- * ) ---- + ----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ---- + ---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ---- + ----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ---- + ----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ---- + ---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ---- + ---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ---- + ---- |___/ |___/ ---- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +---- _____ _ ___ __ _ _ _ __ _ ---- +---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ---- +---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ---- +---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ---- +---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ---- +----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ---- +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ + +-------------------------------------DESCRIPTION------------------------------------------ +------------------------------------------------------------------------------------------ +-- Bridge da FIFO 8bit to AXI4 Stream. -- +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity AXI4Stream_UART_v1_0_S00_AXIS_TX is + generic ( + -- AXI4Stream sink: Data Width + C_S_AXIS_TDATA_WIDTH : integer := 8 + ); + port ( + + --------------FIFO_DATA (32bit)------------- + FIFO_DATA_rst : OUT STD_LOGIC; + FIFO_DATA_clk : OUT STD_LOGIC; + FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0); + FIFO_DATA_wr_en : OUT STD_LOGIC; + FIFO_DATA_full : IN STD_LOGIC; + FIFO_DATA_almost_full : IN STD_LOGIC; + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream sink: Clock + S_AXIS_ACLK : IN STD_LOGIC; + -- AXI4Stream sink: Reset + S_AXIS_ARESETN : IN STD_LOGIC; + -- Ready to accept data in + S_AXIS_TREADY : OUT STD_LOGIC; + -- Data in + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0); + -- Data is in valid + S_AXIS_TVALID : IN STD_LOGIC + -------------------------------------------- + ); +end AXI4Stream_UART_v1_0_S00_AXIS_TX; + +architecture arch_imp of AXI4Stream_UART_v1_0_S00_AXIS_TX is + + -----------------------------SIGNALS---------------------------- + signal S_AXIS_TREADY_int : STD_LOGIC; + ---------------------------------------------------------------- + +begin + + ---------DIRECT ASSIGNMENT---------- + FIFO_DATA_clk <= S_AXIS_ACLK; + FIFO_DATA_rst <= not S_AXIS_ARESETN; + + FIFO_DATA_din <= S_AXIS_TDATA; + + FIFO_DATA_wr_en <= S_AXIS_TREADY_int and S_AXIS_TVALID; + + S_AXIS_TREADY_int <= not FIFO_DATA_almost_full and S_AXIS_ARESETN; + S_AXIS_TREADY <= S_AXIS_TREADY_int; + ------------------------------------ + +end arch_imp; diff --git a/LAB2/src/pak_depak/ipshared/453d/hdl/UART_Engine.vhd b/LAB2/src/pak_depak/ipshared/453d/hdl/UART_Engine.vhd new file mode 100644 index 0000000..6ccdf10 --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/453d/hdl/UART_Engine.vhd @@ -0,0 +1,343 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:02:15 01/23/2016 +-- Design Name: +-- Module Name: uart - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +------------------------------------------------------------------------------ +-- UART +-- Implements a universal asynchronous receiver transmitter +------------------------------------------------------------------------------- +-- clock +-- Input clock, must match frequency value given on clock_frequency +-- generic input. +-- reset +-- Synchronous reset. +-- data_stream_in +-- Input data bus for bytes to transmit. +-- data_stream_in_stb +-- Input strobe to qualify the input data bus. +-- data_stream_in_ack +-- Output acknowledge to indicate the UART has begun sending the byte +-- provided on the data_stream_in port. +-- data_stream_in_done +-- Output pulse che arriva quando fine tx +-- data_stream_out +-- Data output port for received bytes. +-- data_stream_out_stb +-- Output strobe to qualify the received byte. Will be valid for one clock +-- cycle only. +-- tx +-- Serial transmit. +-- rx +-- Serial receive +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity UART_Engine is + generic ( + BAUD_RATE : integer range 110 to 2000000; + CLOCK_FREQUENCY : positive + ); + port ( + clock : in std_logic; + reset : in std_logic; + data_stream_in : in std_logic_vector(7 downto 0); + data_stream_in_stb : in std_logic; + data_stream_in_ack : out std_logic; + data_stream_in_done : out std_logic; + data_stream_out : out std_logic_vector(7 downto 0); + data_stream_out_stb : out std_logic; + tx : out std_logic; + rx : in std_logic + ); +end UART_Engine; + +architecture rtl of UART_Engine is + --------------------------------------------------------------------------- + -- Baud generation constants + --------------------------------------------------------------------------- + constant c_tx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE))); + constant c_rx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE * 16))); + --------------------------------------------------------------------------- + -- Baud generation signals + --------------------------------------------------------------------------- + signal tx_baud_counter : integer range 0 to c_tx_div-1 := 0; + signal tx_baud_tick : std_logic := '0'; + signal rx_baud_counter : integer range 0 to c_rx_div-1 := 0; + signal rx_baud_tick : std_logic := '0'; + --------------------------------------------------------------------------- + -- Transmitter signals + --------------------------------------------------------------------------- + type uart_tx_states is ( + tx_send_start_bit, + tx_send_data, + tx_send_stop_bit + ); + signal uart_tx_state : uart_tx_states := tx_send_start_bit; + signal uart_tx_data_vec : std_logic_vector(7 downto 0) := (others => '0'); + signal uart_tx_data : std_logic := '1'; + signal uart_tx_count : unsigned(2 downto 0) := (others => '0'); + signal uart_rx_data_in_ack : std_logic := '0'; + signal uart_rx_data_in_done : std_logic := '0'; + --------------------------------------------------------------------------- + -- Receiver signals + --------------------------------------------------------------------------- + type uart_rx_states is ( + rx_get_start_bit, + rx_get_data, + rx_get_stop_bit + ); + signal uart_rx_state : uart_rx_states := rx_get_start_bit; + signal uart_rx_bit : std_logic := '1'; + signal uart_rx_data_vec : std_logic_vector(7 downto 0) := (others => '0'); + signal uart_rx_data_sr : std_logic_vector(1 downto 0) := (others => '1'); + signal uart_rx_filter : unsigned(1 downto 0) := (others => '1'); + signal uart_rx_count : unsigned(2 downto 0) := (others => '0'); + signal uart_rx_data_out_stb : std_logic := '0'; + signal uart_rx_bit_spacing : unsigned (3 downto 0) := (others => '0'); + signal uart_rx_bit_tick : std_logic := '0'; +begin + -- Connect IO + data_stream_in_ack <= uart_rx_data_in_ack; + data_stream_in_done <= uart_rx_data_in_done; + data_stream_out <= uart_rx_data_vec; + data_stream_out_stb <= uart_rx_data_out_stb; + tx <= uart_tx_data; + --------------------------------------------------------------------------- + -- OVERSAMPLE_CLOCK_DIVIDER + -- generate an oversampled tick (baud * 16) + --------------------------------------------------------------------------- + oversample_clock_divider : process (clock) + begin + if rising_edge (clock) then + if reset = '1' then + rx_baud_counter <= 0; + rx_baud_tick <= '0'; + else + if rx_baud_counter = c_rx_div - 1 then + rx_baud_counter <= 0; + rx_baud_tick <= '1'; + else + rx_baud_counter <= rx_baud_counter + 1; + rx_baud_tick <= '0'; + end if; + end if; + end if; + end process oversample_clock_divider; + --------------------------------------------------------------------------- + -- RXD_SYNCHRONISE + -- Synchronise rxd to the oversampled baud + --------------------------------------------------------------------------- + rxd_synchronise : process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + uart_rx_data_sr <= (others => '1'); + else + if rx_baud_tick = '1' then + uart_rx_data_sr(0) <= rx; + uart_rx_data_sr(1) <= uart_rx_data_sr(0); + end if; + end if; + end if; + end process rxd_synchronise; + --------------------------------------------------------------------------- + -- RXD_FILTER + -- Filter rxd with a 2 bit counter. + --------------------------------------------------------------------------- + rxd_filter : process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + uart_rx_filter <= (others => '1'); + uart_rx_bit <= '1'; + else + if rx_baud_tick = '1' then + -- filter rxd. + if uart_rx_data_sr(1) = '1' and uart_rx_filter < 3 then + uart_rx_filter <= uart_rx_filter + 1; + elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then + uart_rx_filter <= uart_rx_filter - 1; + end if; + -- set the rx bit. + if uart_rx_filter = 3 then + uart_rx_bit <= '1'; + elsif uart_rx_filter = 0 then + uart_rx_bit <= '0'; + end if; + end if; + end if; + end if; + end process rxd_filter; + --------------------------------------------------------------------------- + -- RX_BIT_SPACING + --------------------------------------------------------------------------- + rx_bit_spacing : process (clock) + begin + if rising_edge(clock) then + uart_rx_bit_tick <= '0'; + if rx_baud_tick = '1' then + if uart_rx_bit_spacing = 15 then + uart_rx_bit_tick <= '1'; + uart_rx_bit_spacing <= (others => '0'); + else + uart_rx_bit_spacing <= uart_rx_bit_spacing + 1; + end if; + if uart_rx_state = rx_get_start_bit then + uart_rx_bit_spacing <= (others => '0'); + end if; + end if; + end if; + end process rx_bit_spacing; + --------------------------------------------------------------------------- + -- UART_RECEIVE_DATA + --------------------------------------------------------------------------- + uart_receive_data : process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + uart_rx_state <= rx_get_start_bit; + uart_rx_data_vec <= (others => '0'); + uart_rx_count <= (others => '0'); + uart_rx_data_out_stb <= '0'; + else + uart_rx_data_out_stb <= '0'; + case uart_rx_state is + when rx_get_start_bit => + if rx_baud_tick = '1' and uart_rx_bit = '0' then + uart_rx_state <= rx_get_data; + end if; + when rx_get_data => + if uart_rx_bit_tick = '1' then + uart_rx_data_vec(uart_rx_data_vec'high) + <= uart_rx_bit; + uart_rx_data_vec( + uart_rx_data_vec'high-1 downto 0 + ) <= uart_rx_data_vec( + uart_rx_data_vec'high downto 1 + ); + if uart_rx_count < 7 then + uart_rx_count <= uart_rx_count + 1; + else + uart_rx_count <= (others => '0'); + uart_rx_state <= rx_get_stop_bit; + end if; + end if; + when rx_get_stop_bit => + if uart_rx_bit_tick = '1' then + if uart_rx_bit = '1' then + uart_rx_state <= rx_get_start_bit; + uart_rx_data_out_stb <= '1'; + end if; + end if; + when others => + uart_rx_state <= rx_get_start_bit; + end case; + end if; + end if; + end process uart_receive_data; + --------------------------------------------------------------------------- + -- TX_CLOCK_DIVIDER + -- Generate baud ticks at the required rate based on the input clock + -- frequency and baud rate + --------------------------------------------------------------------------- + tx_clock_divider : process (clock) + begin + if rising_edge (clock) then + if reset = '1' then + tx_baud_counter <= 0; + tx_baud_tick <= '0'; + else + if tx_baud_counter = c_tx_div - 1 then + tx_baud_counter <= 0; + tx_baud_tick <= '1'; + else + tx_baud_counter <= tx_baud_counter + 1; + tx_baud_tick <= '0'; + end if; + end if; + end if; + end process tx_clock_divider; + --------------------------------------------------------------------------- + -- UART_SEND_DATA + -- Get data from data_stream_in and send it one bit at a time upon each + -- baud tick. Send data lsb first. + -- wait 1 tick, send start bit (0), send data 0-7, send stop bit (1) + --------------------------------------------------------------------------- + uart_send_data : process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + uart_tx_data <= '1'; + uart_tx_data_vec <= (others => '0'); + uart_tx_count <= (others => '0'); + uart_tx_state <= tx_send_start_bit; + uart_rx_data_in_ack <= '0'; + uart_rx_data_in_done <= '0'; + else + uart_rx_data_in_ack <= '0'; + uart_rx_data_in_done <= '0'; --new + case uart_tx_state is + when tx_send_start_bit => + if tx_baud_tick = '1' and data_stream_in_stb = '1' then + uart_tx_data <= '0'; + uart_tx_state <= tx_send_data; + uart_tx_count <= (others => '0'); + uart_rx_data_in_ack <= '1'; + uart_tx_data_vec <= data_stream_in; + end if; + when tx_send_data => + if tx_baud_tick = '1' then + uart_tx_data <= uart_tx_data_vec(0); + uart_tx_data_vec( + uart_tx_data_vec'high-1 downto 0 + ) <= uart_tx_data_vec( + uart_tx_data_vec'high downto 1 + ); + if uart_tx_count < 7 then + uart_tx_count <= uart_tx_count + 1; + else + uart_tx_count <= (others => '0'); + uart_tx_state <= tx_send_stop_bit; + end if; + end if; + when tx_send_stop_bit => + if tx_baud_tick = '1' then + uart_tx_data <= '1'; + uart_tx_state <= tx_send_start_bit; + uart_rx_data_in_done <= '1'; --new + end if; + when others => + uart_tx_data <= '1'; + uart_tx_state <= tx_send_start_bit; + end case; + end if; + end if; + end process uart_send_data; +end rtl; diff --git a/LAB2/src/pak_depak/ipshared/453d/hdl/UART_Manager.vhd b/LAB2/src/pak_depak/ipshared/453d/hdl/UART_Manager.vhd new file mode 100644 index 0000000..5ab7704 --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/453d/hdl/UART_Manager.vhd @@ -0,0 +1,238 @@ + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ---- * ) ---- + ----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ---- + ---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ---- + ----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ---- + ----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ---- + ---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ---- + ---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ---- + ---- |___/ |___/ ---- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +---- _____ _ ___ __ _ _ _ __ _ ---- +---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ---- +---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ---- +---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ---- +---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ---- +----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ---- +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ + +-------------------------------------DESCRIPTION------------------------------------------ +------------------------------------------------------------------------------------------ +-- Modulo di più basso livello per la gestione dei dati tra FIFO in e FIFO out ed il -- +-- modulo FTDI 2232H in modalita FT245 Asynchronous. La priorità è data ai dati in -- +-- arrivo dal PC verso FPGA. -- +-- Il clock in ingresso deve avere un periodo di 10 ns per garantire i tempi -- +-- rischiesti dal 2232H -- +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + +entity UART_Manager is + generic( + UART_BAUD_RATE : positive; + UART_CLOCK_FREQUENCY : positive --The associated clock frequency + ); + Port ( + ---------Global--------- + clk_uart : IN STD_LOGIC; + reset : IN STD_LOGIC; + ------------------------ + + ---------Connessioni comunicazione UART----------- + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + --------------------------------------------------- + + ------------FIFO_DATA_RX (8bit)------------- + FIFO_DATA_RX_rst : OUT STD_LOGIC; + FIFO_DATA_RX_clk : OUT STD_LOGIC; + FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_RX_wr_en : OUT STD_LOGIC; + FIFO_DATA_RX_full : IN STD_LOGIC; + FIFO_DATA_RX_almost_full : IN STD_LOGIC; + -------------------------------------------- + + ------------FIFO_DATA_TX (8bit)------------- + --FIFO_DATA_RX_rst : OUT STD_LOGIC; + FIFO_DATA_TX_clk : OUT STD_LOGIC; + FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_TX_rd_en : OUT STD_LOGIC; + FIFO_DATA_TX_empty : IN STD_LOGIC; + FIFO_DATA_TX_almost_empty : IN STD_LOGIC + -------------------------------------------- + ); +end UART_Manager; + +architecture Behavioral of UART_Manager is + + -------------------COMPONENT------------------ + COMPONENT UART_engine + GENERIC( + BAUD_RATE : positive; + CLOCK_FREQUENCY : positive + ); + PORT( + --SYSTEM UART + clock : IN std_logic; + reset : IN std_logic; + + -- FPGA-->PC + data_stream_in : IN std_logic_vector(7 downto 0); + data_stream_in_stb : IN std_logic; + data_stream_in_ack : OUT std_logic; + data_stream_in_done : OUT std_logic; + tx : OUT std_logic; + + -- PC-->FPGA + data_stream_out : OUT std_logic_vector(7 downto 0); + data_stream_out_stb : OUT std_logic; + rx : IN std_logic + + ); + END COMPONENT; + ---------------------------------------------- + + --------------------SIGNALS------------------- + signal state : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"00"; + + --TX:fromFPGAtoPC + signal data_stream_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0'); + signal data_stream_in_stb : STD_LOGIC := '0'; + signal data_stream_in_ack : STD_LOGIC := '0'; + signal data_stream_in_done : STD_LOGIC := '0'; + + signal state_TX : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF"; + + --RX:fromPCtoFPGA + signal data_stream_out : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0'); + signal data_stream_out_stb : STD_LOGIC := '0'; + ---------------------------------------------- + +begin + + Inst_uart: UART_engine + GENERIC MAP ( + BAUD_RATE => UART_BAUD_RATE, + CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY + ) + PORT MAP( + clock => clk_uart, + reset => reset, + + -- FPGA-->PC + data_stream_in => data_stream_in, --byte FPGA->PC, (in) + data_stream_in_stb => data_stream_in_stb, --'1' per 1 clock inizia la fase di trasmisisone a PC di data_stream_in (in) + data_stream_in_ack => data_stream_in_ack, --'1' per 1 clock vuol dire che START TX (data_stream_in_stb='1') è stata capita (in) + data_stream_in_done => data_stream_in_done, --'1' indica la fine della trasmisione (out) + tx => UART_TX, + + -- PC-->FPGA + data_stream_out => data_stream_out, --byte PC->FPGA, (out) + data_stream_out_stb => data_stream_out_stb, --'1' per 1 clock indica che su data_stream_out c'è un nuovo dato (out) +-- data_stream_out => FIFO_RX_din, +-- data_stream_out_stb => FIFO_RX_wr_en, + rx => UART_RX + + ); + + fromFPGAtoPC : process(clk_uart, reset) + begin + if (reset = '1') then + state_TX <= x"00"; + --UART + data_stream_in <= (others => '0'); + data_stream_in_stb <= '0'; + --FIFO_TX + FIFO_DATA_TX_rd_en <= '0'; + + elsif rising_edge(clk_uart) then + case state_TX is + + when x"FF" => + if(reset = '0') then + state_TX <= x"00"; + else + state_TX <= x"FF"; + end if; + --UART + data_stream_in <= (others => '0'); + data_stream_in_stb <= '0'; + --FIFO_TX + FIFO_DATA_TX_rd_en <= '0'; + + + when x"00" => + FIFO_DATA_TX_rd_en <= '0'; + data_stream_in_stb <= '0'; + + if (FIFO_DATA_TX_empty = '0') then --nessun dato da trasmettere al PC + state_TX <= x"01"; --si hanno dati in FIFO TX da passare al PC + FIFO_DATA_TX_rd_en <= '1'; --abilita lettura FIFO + data_stream_in <= FIFO_DATA_TX_dout; --dai alla UART il byte in uscita dalla fifo già pronto + data_stream_in_stb <= '1'; --abilita TX della UART + end if; + + + when x"01" => + FIFO_DATA_TX_rd_en <= '0'; --blocca la lettura FIFO + --tieni data_stream_in_stb attivo finche la UART non inizia a trasferire data_stream_in_ack='0' + if (data_stream_in_ack = '1') then + state_TX <= x"02"; + data_stream_in_stb <= '0'; + end if; + + + when x"02" => + -- data_stream_in_done = '1' significa fin trasmisisone UART + if (data_stream_in_done = '1') then + state_TX <= x"00"; + end if; + + + when others => + state_TX <= x"00"; + + + end case; + end if; + end process; + + + + fromPCtoFPGA : process(clk_uart, reset) + begin + if (reset = '1') then + FIFO_DATA_RX_din <= (others => '0'); + FIFO_DATA_RX_wr_en <= '0'; + + elsif rising_edge(clk_uart) then + FIFO_DATA_RX_wr_en <= '0'; + if (data_stream_out_stb = '1') then --arrivato nuovo dato sulla UART, caricalo in FIGO RX + FIFO_DATA_RX_wr_en <= '1'; + FIFO_DATA_RX_din <= data_stream_out; + end if; + end if; + + end process; + + --------------------ASSIGMENT------------------ + FIFO_DATA_RX_clk <= clk_uart; + FIFO_DATA_TX_clk <= clk_uart; + + FIFO_DATA_RX_rst <= reset; + ----------------------------------------------- + +end Behavioral; + diff --git a/LAB2/src/pak_depak/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd b/LAB2/src/pak_depak/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd new file mode 100644 index 0000000..5102183 --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd @@ -0,0 +1,1646 @@ +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- upcnt_n - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- ************************************************************************ +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This file contains proprietary and confidential information of ** +-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +-- ** from Xilinx, and may be used, copied and/or disclosed only ** +-- ** pursuant to the terms of a valid license agreement with Xilinx. ** +-- ** ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +-- ** does not warrant that functions included in the Materials will ** +-- ** meet the requirements of Licensee, or that the operation of the ** +-- ** Materials will be uninterrupted or error-free, or that defects ** +-- ** in the Materials will be corrected. Furthermore, Xilinx does ** +-- ** not warrant or make any representations regarding use, or the ** +-- ** results of the use, of the Materials in terms of correctness, ** +-- ** accuracy, reliability or otherwise. ** +-- ** ** +-- ** Xilinx products are not designed or intended to be fail-safe, ** +-- ** or for use in any application requiring fail-safe performance, ** +-- ** such as life-support or safety devices or systems, Class III ** +-- ** medical devices, nuclear facilities, applications related to ** +-- ** the deployment of airbags, or any other applications that could ** +-- ** lead to death, personal injury or severe property or ** +-- ** environmental damage (individually and collectively, "critical ** +-- ** applications"). Customer assumes the sole risk and liability ** +-- ** of any use of Xilinx products in critical applications, ** +-- ** subject only to applicable laws and regulations governing ** +-- ** limitations on product liability. ** +-- ** ** +-- ** Copyright 2010 Xilinx, Inc. ** +-- ** All rights reserved. ** +-- ** ** +-- ** This disclaimer and copyright notice must be retained as part ** +-- ** of this file at all times. ** +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: upcnt_n.vhd +-- Version: v4.00a +-- Description: Parameterizeable top level processor reset module. +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: This section should show the hierarchical structure of the +-- designs.Separate lines with blank lines if necessary to improve +-- readability. +-- +-- proc_sys_reset.vhd +-- upcnt_n.vhd +-- lpf.vhd +-- sequence.vhd +------------------------------------------------------------------------------- +-- Author: Kurt Conover +-- History: +-- Kurt Conover 11/07/01 -- First Release +-- +-- ~~~~~~~ +-- SK 03/11/10 +-- ^^^^^^^ +-- 1. Updated the core so support the active low "Interconnect_aresetn" and +-- "Peripheral_aresetn" signals. +-- ^^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +------------------------------------------------------------------------------- +-- Port Declaration +------------------------------------------------------------------------------- +-- Definition of Generics: +-- C_SIZE -- Number of bits in counter +-- +-- +-- Definition of Ports: +-- Data -- parallel data input +-- Cnt_en -- count enable +-- Load -- Load Data +-- Clr -- reset +-- Clk -- Clock +-- Qout -- Count output +-- +------------------------------------------------------------------------------- +entity upcnt_n is + generic( + C_SIZE : Integer + ); + + port( + Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); + Cnt_en : in STD_LOGIC; + Load : in STD_LOGIC; + Clr : in STD_LOGIC; + Clk : in STD_LOGIC; + Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) + ); + +end upcnt_n; + +architecture imp of upcnt_n is + +constant CLEAR : std_logic := '0'; + +signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1'); + +begin + process(Clk) + begin + + if (Clk'event) and Clk = '1' then + -- Clear output register + if (Clr = CLEAR) then + q_int <= (others => '0'); + -- Load in start value + elsif (Load = '1') then + q_int <= UNSIGNED(Data); + -- If count enable is high + elsif Cnt_en = '1' then + q_int <= q_int + 1; + end if; + end if; + end process; + + Qout <= STD_LOGIC_VECTOR(q_int); + +end imp; + + + + +------------------------------------------------------------------------------- +-- sequence - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- ************************************************************************ +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This file contains proprietary and confidential information of ** +-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +-- ** from Xilinx, and may be used, copied and/or disclosed only ** +-- ** pursuant to the terms of a valid license agreement with Xilinx. ** +-- ** ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +-- ** does not warrant that functions included in the Materials will ** +-- ** meet the requirements of Licensee, or that the operation of the ** +-- ** Materials will be uninterrupted or error-free, or that defects ** +-- ** in the Materials will be corrected. Furthermore, Xilinx does ** +-- ** not warrant or make any representations regarding use, or the ** +-- ** results of the use, of the Materials in terms of correctness, ** +-- ** accuracy, reliability or otherwise. ** +-- ** ** +-- ** Xilinx products are not designed or intended to be fail-safe, ** +-- ** or for use in any application requiring fail-safe performance, ** +-- ** such as life-support or safety devices or systems, Class III ** +-- ** medical devices, nuclear facilities, applications related to ** +-- ** the deployment of airbags, or any other applications that could ** +-- ** lead to death, personal injury or severe property or ** +-- ** environmental damage (individually and collectively, "critical ** +-- ** applications"). Customer assumes the sole risk and liability ** +-- ** of any use of Xilinx products in critical applications, ** +-- ** subject only to applicable laws and regulations governing ** +-- ** limitations on product liability. ** +-- ** ** +-- ** Copyright 2012 Xilinx, Inc. ** +-- ** All rights reserved. ** +-- ** ** +-- ** This disclaimer and copyright notice must be retained as part ** +-- ** of this file at all times. ** +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: proc_sys_reset.vhd +-- Version: v4.00a +-- Description: Parameterizeable top level processor reset module. +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: This section should show the hierarchical structure of the +-- designs.Separate lines with blank lines if necessary to improve +-- readability. +-- -- proc_sys_reset.vhd +-- -- upcnt_n.vhd +-- -- lpf.vhd +-- -- sequence.vhd +------------------------------------------------------------------------------- +-- Filename: sequence.vhd +-- +-- Description: +-- This file control the sequencing coming out of a reset. +-- The sequencing is as follows: +-- Bus_Struct_Reset comes out of reset first. Either when the +-- external or auxiliary reset goes inactive or 16 clocks +-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC +-- System_Reset_Request. +-- Peripheral_Reset comes out of reset 16 clocks after +-- Bus_Struct_Reset. +-- The PPC resetcore, comes out of reset +-- 16 clocks after Peripheral_Reset. +-- The PPC resetchip and resetsystem come out of reset +-- at the same time as Bus_Struct_Reset. +------------------------------------------------------------------------------- +-- Author: Kurt Conover +-- History: +-- Kurt Conover 11/12/01 -- First Release +-- LC Whittle 10/11/2004 -- Update for NCSim +-- rolandp 04/16/2007 -- v2.00a +-- +-- ~~~~~~~ +-- SK 03/11/10 +-- ^^^^^^^ +-- 1. Updated the core so support the active low "Interconnect_aresetn" and +-- "Peripheral_aresetn" signals. +-- ^^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +library unisim; +use unisim.vcomponents.all; +library proc_sys_reset_v5_0_13; + +------------------------------------------------------------------------------- +-- Port Declaration +------------------------------------------------------------------------------- +-- Definition of Generics: +-- +-- Definition of Ports: +-- Lpf_reset -- Low Pass Filtered in +-- System_Reset_Req -- System Reset Request +-- Chip_Reset_Req -- Chip Reset Request +-- Slowest_Sync_Clk -- Clock +-- Bsr_out -- Bus Structure Reset out +-- Pr_out -- Peripheral Reset out +-- Core_out -- Core reset out +-- Chip_out -- Chip reset out +-- Sys_out -- System reset out +-- MB_out -- MB reset out +-- +------------------------------------------------------------------------------- +entity sequence_psr is + port( + Lpf_reset : in std_logic; + -- System_Reset_Req : in std_logic; + -- Chip_Reset_Req : in std_logic; + Slowest_Sync_Clk : in std_logic; + Bsr_out : out std_logic; + Pr_out : out std_logic; + -- Core_out : out std_logic; + -- Chip_out : out std_logic; + -- Sys_out : out std_logic; + MB_out : out std_logic + ); +end sequence_psr; + +architecture imp of sequence_psr is + +constant CLEAR : std_logic := '0'; +constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12 +constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25 +constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28 +constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41 +constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44 +constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57 +constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP; +constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS; +constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP; +constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS; + +signal bsr : std_logic := '1'; +signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal pr : std_logic := '1'; +signal pr_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal Core : std_logic := '1'; +signal core_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal Chip : std_logic := '0'; +signal chip_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal Sys : std_logic := '0'; +signal sys_dec : std_logic_vector(2 downto 0) := (others => '0'); +signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req +signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req +signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req +signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req +signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req +signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req +signal seq_cnt : std_logic_vector(5 downto 0); +signal seq_cnt_en : std_logic := '0'; +signal seq_clr : std_logic := '0'; + +signal ris_edge : std_logic := '0'; +signal sys_edge : std_logic := '0'; +signal from_sys : std_logic; + +------------------------------------------------------------------------------- +-- Component Declarations +------------------------------------------------------------------------------- + +begin + + Pr_out <= pr; + Bsr_out <= bsr; + MB_out <= core; + -- Core_out <= core; + -- Chip_out <= chip or sys; + -- Sys_out <= sys; + +------------------------------------------------------------------------------- +-- This process remembers that the reset was caused be +-- System_Reset_Req +------------------------------------------------------------------------------- + SYS_FROM_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + --if Lpf_reset='1' or system_reset_req_d3='1' then + if (Lpf_reset = '1') then + from_sys <= '1'; + --elsif Chip_Reset_Req_d3='1' then + -- from_sys <= '0'; + elsif (Core = '0') then + from_sys <='0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This instantiates a counter to control the sequencing +------------------------------------------------------------------------------- + SEQ_COUNTER : entity proc_sys_reset_v5_0_13.UPCNT_N + generic map (C_SIZE => 6) + port map( + Data => "000000", + Cnt_en => seq_cnt_en, + Load => '0', + Clr => seq_clr, + Clk => Slowest_sync_clk, + Qout => seq_cnt + ); + +------------------------------------------------------------------------------- +-- SEQ_CNT_EN_PROCESS +------------------------------------------------------------------------------- +-- This generates the reset pulse and the count enable to core reset counter +-- count until all outputs are inactive +------------------------------------------------------------------------------- + SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if (Lpf_reset='1' --or + --System_Reset_Req_d3='1' or + --Chip_Reset_Req_d3='1' or + --ris_edge = '1' + ) then + seq_cnt_en <= '1'; + elsif (Core='0') then -- Core always present and always last + seq_cnt_en <= '0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- SEQ_CLR_PROCESS +------------------------------------------------------------------------------- +-- This generates the reset to the sequence counter +-- Clear the counter on a rising edge of chip or system request or low pass +-- filter output +------------------------------------------------------------------------------- + SEQ_CLR_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + -- if ris_edge = '1' or Lpf_reset = '1' then + if (Lpf_reset = '1') then + seq_clr <= '0'; + else + seq_clr <= '1'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This process defines the Peripheral_Reset output signal +------------------------------------------------------------------------------- + PR_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + --if ris_edge = '1' or Lpf_reset = '1' then + if (Lpf_reset = '1') then + pr <= '1'; + elsif (pr_dec(2) = '1') then + pr <= '0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This process decodes the sequence counter for PR to use +------------------------------------------------------------------------------- + PR_DECODE_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if ( + (seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0') + or + (seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1') + ) then + pr_dec(0) <= '1'; + else + pr_dec(0) <= '0'; + end if; + if ( + (seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0') + or + (seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1') + )then + pr_dec(1) <= '1'; + else + pr_dec(1) <= '0'; + end if; + pr_dec(2) <= pr_dec(1) and pr_dec(0); + end if; + end process; + +------------------------------------------------------------------------------- +-- This process defines the Bus_Struct_Reset output signal +------------------------------------------------------------------------------- + BSR_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + --if ris_edge = '1' or Lpf_reset = '1' then + if (Lpf_reset = '1') then + bsr <= '1'; + elsif (bsr_dec(2) = '1') then + bsr <= '0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This process decodes the sequence counter for BSR to use +------------------------------------------------------------------------------- + BSR_DECODE_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if ( + (seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0') + or + (seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1') + )then + bsr_dec(0) <= '1'; + else + bsr_dec(0) <= '0'; + end if; + if ( + (seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0') + or + (seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1') + )then + bsr_dec(1) <= '1'; + else + bsr_dec(1) <= '0'; + end if; + bsr_dec(2) <= bsr_dec(1) and bsr_dec(0); + end if; + end process; + + +------------------------------------------------------------------------------- +-- This process defines the Peripheral_Reset output signal +------------------------------------------------------------------------------- + CORE_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + -- if ris_edge = '1' or Lpf_reset = '1' then + if (Lpf_reset = '1') then + core <= '1'; + elsif (core_dec(2) = '1') then + core <= '0'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- This process decodes the sequence counter for PR to use +------------------------------------------------------------------------------- + CORE_DECODE_PROCESS: process (Slowest_sync_clk) + begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if ( + (seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0') + or + (seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1') + )then + core_dec(0) <= '1'; + else + core_dec(0) <= '0'; + end if; + if ( + (seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0') + or + (seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1') + )then + core_dec(1) <= '1'; + else + core_dec(1) <= '0'; + end if; + core_dec(2) <= core_dec(1) and core_dec(0); + end if; + end process; + +--------------------------------------------------------------------------------- +---- This process defines the Chip output signal +--------------------------------------------------------------------------------- +-- CHIP_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- -- if ris_edge = '1' or Lpf_reset = '1' then +-- if Lpf_reset = '1' then +-- chip <= '1'; +-- elsif chip_dec(2) = '1' then +-- chip <= '0'; +-- end if; +-- end if; +-- end process; +-- +--------------------------------------------------------------------------------- +---- This process decodes the sequence counter for Chip to use +---- sys is overlapping the chip reset and thus no need to decode this here +--------------------------------------------------------------------------------- +-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then +-- chip_dec(0) <= '1'; +-- else +-- chip_dec(0) <= '0'; +-- end if; +-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then +-- chip_dec(1) <= '1'; +-- else +-- chip_dec(1) <= '0'; +-- end if; +-- chip_dec(2) <= chip_dec(1) and chip_dec(0); +-- end if; +-- end process; + +--------------------------------------------------------------------------------- +---- This process defines the Sys output signal +--------------------------------------------------------------------------------- +-- SYS_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if sys_edge = '1' or Lpf_reset = '1' then +-- sys <= '1'; +-- elsif sys_dec(2) = '1' then +-- sys <= '0'; +-- end if; +-- end if; +-- end process; +-- +--------------------------------------------------------------------------------- +---- This process decodes the sequence counter for Sys to use +--------------------------------------------------------------------------------- +-- SYS_DECODE_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or +-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then +-- sys_dec(0) <= '1'; +-- else +-- sys_dec(0) <= '0'; +-- end if; +-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or +-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then +-- sys_dec(1) <= '1'; +-- else +-- sys_dec(1) <= '0'; +-- end if; +-- sys_dec(2) <= sys_dec(1) and sys_dec(0); +-- end if; +-- end process; +-- +--------------------------------------------------------------------------------- +---- This process delays signals so the the edge can be detected and used +--------------------------------------------------------------------------------- +-- DELAY_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- chip_reset_req_d1 <= Chip_Reset_Req ; +-- chip_reset_req_d2 <= chip_Reset_Req_d1 ; +-- chip_reset_req_d3 <= chip_Reset_Req_d2 ; +-- system_reset_req_d1 <= System_Reset_Req; +-- system_reset_req_d2 <= system_Reset_Req_d1; +-- system_reset_req_d3 <= system_Reset_Req_d2; +-- end if; +-- end process; + +------------------------------------------------------------------------------- +-- This process creates a signal that goes high on the rising edge of either +-- Chip_Reset_Req or System_Reset_Req +------------------------------------------------------------------------------- +-- RIS_EDGE_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge +-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then +-- ris_edge <= '1'; +-- else +-- ris_edge <='0'; +-- end if; +-- end if; +-- end process; + +------------------------------------------------------------------------------- +-- This process creates a signal that goes high on the rising edge of +-- System_Reset_Req +------------------------------------------------------------------------------- +-- SYS_EDGE_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then +-- sys_edge <= '1'; +-- else +-- sys_edge <='0'; +-- end if; +-- end if; +-- end process; + + + +end architecture imp; + + + + +------------------------------------------------------------------------------- +-- lpf - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- ************************************************************************ +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This file contains proprietary and confidential information of ** +-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +-- ** from Xilinx, and may be used, copied and/or disclosed only ** +-- ** pursuant to the terms of a valid license agreement with Xilinx. ** +-- ** ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +-- ** does not warrant that functions included in the Materials will ** +-- ** meet the requirements of Licensee, or that the operation of the ** +-- ** Materials will be uninterrupted or error-free, or that defects ** +-- ** in the Materials will be corrected. Furthermore, Xilinx does ** +-- ** not warrant or make any representations regarding use, or the ** +-- ** results of the use, of the Materials in terms of correctness, ** +-- ** accuracy, reliability or otherwise. ** +-- ** ** +-- ** Xilinx products are not designed or intended to be fail-safe, ** +-- ** or for use in any application requiring fail-safe performance, ** +-- ** such as life-support or safety devices or systems, Class III ** +-- ** medical devices, nuclear facilities, applications related to ** +-- ** the deployment of airbags, or any other applications that could ** +-- ** lead to death, personal injury or severe property or ** +-- ** environmental damage (individually and collectively, "critical ** +-- ** applications"). Customer assumes the sole risk and liability ** +-- ** of any use of Xilinx products in critical applications, ** +-- ** subject only to applicable laws and regulations governing ** +-- ** limitations on product liability. ** +-- ** ** +-- ** Copyright 2012 Xilinx, Inc. ** +-- ** All rights reserved. ** +-- ** ** +-- ** This disclaimer and copyright notice must be retained as part ** +-- ** of this file at all times. ** +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: lpf.vhd +-- Version: v4.00a +-- Description: Parameterizeable top level processor reset module. +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: This section should show the hierarchical structure of the +-- designs.Separate lines with blank lines if necessary to improve +-- readability. +-- +-- proc_sys_reset.vhd +-- upcnt_n.vhd +-- lpf.vhd +-- sequence.vhd +------------------------------------------------------------------------------- +-- Author: Kurt Conover +-- History: +-- Kurt Conover 11/08/01 -- First Release +-- +-- KC 02/25/2002 -- Added Dcm_locked as an input +-- -- Added Power on reset srl_time_out +-- +-- KC 08/26/2003 -- Added attribute statements for power on +-- reset SRL +-- +-- ~~~~~~~ +-- SK 03/11/10 +-- ^^^^^^^ +-- 1. Updated the core so support the active low "Interconnect_aresetn" and +-- "Peripheral_aresetn" signals. +-- ^^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; +library lib_cdc_v1_0_2; +--use lib_cdc_v1_0_2.all; +library Unisim; + use Unisim.all; +------------------------------------------------------------------------------- +-- Port Declaration +------------------------------------------------------------------------------- +-- Definition of Generics: +-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting +-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting +-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low +-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low +-- +-- Definition of Ports: +-- Slowest_sync_clk -- Clock +-- External_System_Reset -- External Reset Input +-- Auxiliary_System_Reset -- Auxiliary Reset Input +-- Dcm_locked -- DCM Locked, hold system in reset until 1 +-- Lpf_reset -- Low Pass Filtered Output +-- +------------------------------------------------------------------------------- +entity lpf is + generic( + C_EXT_RST_WIDTH : Integer; + C_AUX_RST_WIDTH : Integer; + C_EXT_RESET_HIGH : std_logic; + C_AUX_RESET_HIGH : std_logic + ); + + port( + MB_Debug_Sys_Rst : in std_logic; + Dcm_locked : in std_logic; + External_System_Reset : in std_logic; + Auxiliary_System_Reset : in std_logic; + Slowest_Sync_Clk : in std_logic; + Lpf_reset : out std_logic + ); + +end lpf; + +architecture imp of lpf is + +component SRL16 is +-- synthesis translate_off + generic ( + INIT : bit_vector ); +-- synthesis translate_on + port (D : in std_logic; + CLK : in std_logic; + A0 : in std_logic; + A1 : in std_logic; + A2 : in std_logic; + A3 : in std_logic; + Q : out std_logic); +end component SRL16; + + +constant CLEAR : std_logic := '0'; + +signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset +signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1) + := (others => '0'); -- LPF DFF + +signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset +signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1) + := (others => '0'); -- LPF DFF + +signal exr_and : std_logic := '0'; -- varible input width "and" gate +signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate + +signal asr_and : std_logic := '0'; -- varible input width "and" gate +signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate + +signal lpf_int : std_logic := '0'; -- internal Lpf_reset +signal lpf_exr : std_logic := '0'; +signal lpf_asr : std_logic := '0'; + +signal srl_time_out : std_logic; + +attribute INIT : string; +attribute INIT of POR_SRL_I: label is "FFFF"; + + +begin + + Lpf_reset <= lpf_int; + +------------------------------------------------------------------------------- +-- Power On Reset Generation +------------------------------------------------------------------------------- +-- This generates a reset for the first 16 clocks after a power up +------------------------------------------------------------------------------- + POR_SRL_I: SRL16 +-- synthesis translate_off + generic map ( + INIT => X"FFFF") +-- synthesis translate_on + port map ( + D => '0', + CLK => Slowest_sync_clk, + A0 => '1', + A1 => '1', + A2 => '1', + A3 => '1', + Q => srl_time_out); + +------------------------------------------------------------------------------- +-- LPF_OUTPUT_PROCESS +------------------------------------------------------------------------------- +-- This generates the reset pulse and the count enable to core reset counter +-- +--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate +--begin +LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) +begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked; + end if; +end process LPF_OUTPUT_PROCESS; +--end generate ACTIVE_HIGH_LPF_EXT; + +--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate +--begin +--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- lpf_int <= not (lpf_exr or +-- lpf_asr or +-- srl_time_out)or +-- not Dcm_locked; +-- end if; +-- end process; +--end generate ACTIVE_LOW_LPF_EXT; + +EXR_OUTPUT_PROCESS: process (Slowest_sync_clk) +begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if exr_and = '1' then + lpf_exr <= '1'; + elsif (exr_and = '0' and exr_nand = '1') then + lpf_exr <= '0'; + end if; + end if; +end process EXR_OUTPUT_PROCESS; + +ASR_OUTPUT_PROCESS: process (Slowest_sync_clk) +begin + if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + if asr_and = '1' then + lpf_asr <= '1'; + elsif (asr_and = '0' and asr_nand = '1') then + lpf_asr <= '0'; + end if; + end if; +end process ASR_OUTPUT_PROCESS; +------------------------------------------------------------------------------- +-- This If-generate selects an active high input for External System Reset +------------------------------------------------------------------------------- +ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate +begin + ----------------------------------- +exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst; + +ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 1, + C_FLOP_INPUT => 0, + C_VECTOR_WIDTH => 2, + C_MTBF_STAGES => 4 + ) + port map( + prmry_aclk => '1', + prmry_resetn => '1',--S_AXI_ARESETN, + prmry_in => exr_d1, + prmry_ack => open, + scndry_out => exr_lpf(0), + scndry_aclk => Slowest_Sync_Clk, + scndry_resetn => '1', --S_AXIS_ARESETN, + prmry_vect_in => "00", + scndry_vect_out => open + ); + +----------------------------------- +end generate ACTIVE_HIGH_EXT; +------------------------------------------------------------------------------- +-- This If-generate selects an active low input for External System Reset +------------------------------------------------------------------------------- +ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate +begin +exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst; + ------------------------------------- + +ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 1, + C_FLOP_INPUT => 0, + C_VECTOR_WIDTH => 2, + C_MTBF_STAGES => 4 + ) + port map( + prmry_aclk => '1', + prmry_resetn => '1',--S_AXI_ARESETN, + prmry_in => exr_d1, + prmry_ack => open, + scndry_out => exr_lpf(0), + scndry_aclk => Slowest_Sync_Clk, + scndry_resetn => '1', --S_AXIS_ARESETN, + prmry_vect_in => "00", + scndry_vect_out => open + ); +------------------------------------- +end generate ACTIVE_LOW_EXT; + +------------------------------------------------------------------------------- +-- This If-generate selects an active high input for Auxiliary System Reset +------------------------------------------------------------------------------- +ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate +begin +asr_d1 <= Auxiliary_System_Reset; +------------------------------------- + +ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 1, + C_FLOP_INPUT => 0, + C_VECTOR_WIDTH => 2, + C_MTBF_STAGES => 4 + ) + port map( + prmry_aclk => '1', + prmry_resetn => '1',--S_AXI_ARESETN, + prmry_in => asr_d1, + prmry_ack => open, + scndry_out => asr_lpf(0), + scndry_aclk => Slowest_Sync_Clk, + scndry_resetn => '1', --S_AXIS_ARESETN, + prmry_vect_in => "00", + scndry_vect_out => open + ); + ------------------------------------- +end generate ACTIVE_HIGH_AUX; +------------------------------------------------------------------------------- +-- This If-generate selects an active low input for Auxiliary System Reset +------------------------------------------------------------------------------- +ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate +begin + ------------------------------------- +asr_d1 <= not Auxiliary_System_Reset; + +ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 1, + C_FLOP_INPUT => 0, + C_VECTOR_WIDTH => 2, + C_MTBF_STAGES => 4 + ) + port map( + prmry_aclk => '1', + prmry_resetn => '1',--S_AXI_ARESETN, + prmry_in => asr_d1, + prmry_ack => open, + scndry_out => asr_lpf(0), + scndry_aclk => Slowest_Sync_Clk, + scndry_resetn => '1', --S_AXIS_ARESETN, + prmry_vect_in => "00", + scndry_vect_out => open + ); + ------------------------------------- +end generate ACTIVE_LOW_AUX; + +------------------------------------------------------------------------------- +-- This For-generate creates the low pass filter D-Flip Flops +------------------------------------------------------------------------------- +EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate +begin + ---------------------------------------- + EXT_LPF_DFF : process (Slowest_Sync_Clk) + begin + if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then + exr_lpf(i) <= exr_lpf(i-1); + end if; + end process; + ---------------------------------------- +end generate EXT_LPF; +------------------------------------------------------------------------------------------ +-- Implement the 'AND' function on the for the LPF +------------------------------------------------------------------------------------------ +EXT_LPF_AND : process (exr_lpf) +Variable loop_and : std_logic; +Variable loop_nand : std_logic; +Begin + loop_and := '1'; + loop_nand := '1'; + for j in 0 to C_EXT_RST_WIDTH - 1 loop + loop_and := loop_and and exr_lpf(j); + loop_nand := loop_nand and not exr_lpf(j); + End loop; + + exr_and <= loop_and; + exr_nand <= loop_nand; + +end process; + +------------------------------------------------------------------------------- +-- This For-generate creates the low pass filter D-Flip Flops +------------------------------------------------------------------------------- +AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate +begin + ---------------------------------------- + AUX_LPF_DFF : process (Slowest_Sync_Clk) + begin + if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then + asr_lpf(k) <= asr_lpf(k-1); + end if; + end process; + ---------------------------------------- +end generate AUX_LPF; +------------------------------------------------------------------------------------------ +-- Implement the 'AND' function on the for the LPF +------------------------------------------------------------------------------------------ +AUX_LPF_AND : process (asr_lpf) +Variable aux_loop_and : std_logic; +Variable aux_loop_nand : std_logic; +Begin + aux_loop_and := '1'; + aux_loop_nand := '1'; + for m in 0 to C_AUX_RST_WIDTH - 1 loop + aux_loop_and := aux_loop_and and asr_lpf(m); + aux_loop_nand := aux_loop_nand and not asr_lpf(m); + End loop; + + asr_and <= aux_loop_and; + asr_nand <= aux_loop_nand; + +end process; + +end imp; + + + + +------------------------------------------------------------------------------- +-- proc_sys_reset - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- ************************************************************************ +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This file contains proprietary and confidential information of ** +-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +-- ** from Xilinx, and may be used, copied and/or disclosed only ** +-- ** pursuant to the terms of a valid license agreement with Xilinx. ** +-- ** ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +-- ** does not warrant that functions included in the Materials will ** +-- ** meet the requirements of Licensee, or that the operation of the ** +-- ** Materials will be uninterrupted or error-free, or that defects ** +-- ** in the Materials will be corrected. Furthermore, Xilinx does ** +-- ** not warrant or make any representations regarding use, or the ** +-- ** results of the use, of the Materials in terms of correctness, ** +-- ** accuracy, reliability or otherwise. ** +-- ** ** +-- ** Xilinx products are not designed or intended to be fail-safe, ** +-- ** or for use in any application requiring fail-safe performance, ** +-- ** such as life-support or safety devices or systems, Class III ** +-- ** medical devices, nuclear facilities, applications related to ** +-- ** the deployment of airbags, or any other applications that could ** +-- ** lead to death, personal injury or severe property or ** +-- ** environmental damage (individually and collectively, "critical ** +-- ** applications"). Customer assumes the sole risk and liability ** +-- ** of any use of Xilinx products in critical applications, ** +-- ** subject only to applicable laws and regulations governing ** +-- ** limitations on product liability. ** +-- ** ** +-- ** Copyright 2012 Xilinx, Inc. ** +-- ** All rights reserved. ** +-- ** ** +-- ** This disclaimer and copyright notice must be retained as part ** +-- ** of this file at all times. ** +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: proc_sys_reset.vhd +-- Version: v4.00a +-- Description: Parameterizeable top level processor reset module. +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: This section should show the hierarchical structure of the +-- designs.Separate lines with blank lines if necessary to improve +-- readability. +-- +-- proc_sys_reset.vhd +-- upcnt_n.vhd +-- lpf.vhd +-- sequence.vhd +------------------------------------------------------------------------------- +-- Author: rolandp +-- History: +-- kc 11/07/01 -- First version +-- +-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to +-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to +-- C_AUX_RESET_HIGH to match generics used in +-- MicroBlaze. Added the DCM Lock as an input +-- to keep reset active until after the Lock +-- is valid. +-- lcw 10/11/2004 -- Updated for NCSim +-- Ravi 09/14/2006 -- Added Attributes for synthesis +-- rolandp 04/16/2007 -- version 2.00a +-- ~~~~~~~ +-- SK 03/11/10 +-- ^^^^^^^ +-- 1. Updated the core so support the active low "Interconnect_aresetn" and +-- "Peripheral_aresetn" signals. +-- ^^^^^^^ +-- ~~~~~~~ +-- SK 05/12/11 +-- ^^^^^^^ +-- 1. Updated the core so remove the support for PPC related functionality. +-- ^^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_cmb" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; +library unisim; + use unisim.vcomponents.all; +library proc_sys_reset_v5_0_13; + use proc_sys_reset_v5_0_13.all; + +------------------------------------------------------------------------------- +-- Port Declaration +------------------------------------------------------------------------------- +-- Definition of Generics: +-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting +-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting + +-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low +-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low + +-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate +-- C_NUM_PERP_RST -- Number of Peripheral resets to generate +-- +-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect +-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral + +-- Definition of Ports: +-- slowest_sync_clk -- Clock +-- ext_reset_in -- External Reset Input +-- aux_reset_in -- Auxiliary Reset Input +-- mb_debug_sys_rst -- MDM Reset Input +-- dcm_locked -- DCM Locked, hold system in reset until 1 +-- mb_reset -- MB core reset out +-- bus_struct_reset -- Bus structure reset out +-- peripheral_reset -- Peripheral reset out + +-- interconnect_aresetn -- Interconnect Bus structure registered rst out +-- peripheral_aresetn -- Active Low Peripheral registered reset out +------------------------------------------------------------------------------- + +entity proc_sys_reset is + generic ( + C_FAMILY : string := "virtex7"; + C_EXT_RST_WIDTH : integer := 4; + C_AUX_RST_WIDTH : integer := 4; + C_EXT_RESET_HIGH : std_logic := '0'; -- High active input + C_AUX_RESET_HIGH : std_logic := '1'; -- High active input + C_NUM_BUS_RST : integer := 1; + C_NUM_PERP_RST : integer := 1; + + C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010 + C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010 + ); + port ( + slowest_sync_clk : in std_logic; + + ext_reset_in : in std_logic; + aux_reset_in : in std_logic; + + -- from MDM + mb_debug_sys_rst : in std_logic; + -- DCM locked information + dcm_locked : in std_logic := '1'; + + -- -- from PPC + -- Core_Reset_Req_0 : in std_logic; + -- Chip_Reset_Req_0 : in std_logic; + -- System_Reset_Req_0 : in std_logic; + -- Core_Reset_Req_1 : in std_logic; + -- Chip_Reset_Req_1 : in std_logic; + -- System_Reset_Req_1 : in std_logic; + + -- RstcPPCresetcore_0 : out std_logic := '0'; + -- RstcPPCresetchip_0 : out std_logic := '0'; + -- RstcPPCresetsys_0 : out std_logic := '0'; + -- RstcPPCresetcore_1 : out std_logic := '0'; + -- RstcPPCresetchip_1 : out std_logic := '0'; + -- RstcPPCresetsys_1 : out std_logic := '0'; + + -- to Microblaze active high reset + mb_reset : out std_logic; + -- active high resets + bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1) + := (others => '0'); + peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1) + := (others => '0'); + -- active low resets + interconnect_aresetn : out + std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1)) + := (others => '1'); + peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1)) + := (others => '1') + ); + +end entity proc_sys_reset; + +------------------------------------------------------------------------------- +-- Architecture +------------------------------------------------------------------------------- +architecture imp of proc_sys_reset is + +------------------------------------------------------------------------------- +-- Constant Declarations +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- Signal and Type Declarations +-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req +-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req +constant T : std_logic := C_EXT_RESET_HIGH; + +signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable +signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable + +signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0 +signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1 + +signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output +signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output + +signal lpf_reset : std_logic; -- Low pass filtered ext or aux + +--signal Chip_Reset_Req : std_logic := '0'; +--signal System_Reset_Req : std_logic := '0'; + +signal Bsr_out : std_logic; +signal Pr_out : std_logic; + +-- signal Core_out : std_logic; +-- signal Chip_out : std_logic; +-- signal Sys_out : std_logic; +signal MB_out : std_logic := C_EXT_RESET_HIGH; +signal MB_out1 : std_logic := C_EXT_RESET_HIGH; +signal pr_outn : std_logic; +signal bsr_outn : std_logic; + +------------------------------------------------------------------------------- +-- Attributes to synthesis +------------------------------------------------------------------------------- + +--attribute equivalent_register_removal: string; +--attribute equivalent_register_removal of bus_struct_reset : signal is "no"; +--attribute equivalent_register_removal of peripheral_reset : signal is "no"; + +--attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; +--attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; + +begin +------------------------------------------------------------------------------- + +-- --------------------- +-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze +-- --------------------- +-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate +-- begin +-- mb_reset <= MB_out1; + +-- MB_Reset_PROCESS1: process (slowest_sync_clk) +-- begin +-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then +-- MB_out1 <= MB_out; +-- end if; +-- end process; + + FDRE_inst : FDRE + generic map ( + INIT => '1') -- Initial value of register ('0' or '1') + port map ( + Q => mb_reset, -- Data output + C => slowest_sync_clk, -- Clock input + CE => '1', -- Clock enable input + R => '0', -- Synchronous reset input + D => MB_out -- Data input + ); + +-- ---------------------------------------------------------------------------- +-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s) +-- ---------------------------------------------------------------------------- + BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate + + FDRE_BSR : FDRE + generic map ( + INIT => '1') -- Initial value of register ('0' or '1') + port map ( + Q => bus_struct_reset(i), -- Data output + C => slowest_sync_clk, -- Clock input + CE => '1', -- Clock enable input + R => '0', -- Synchronous reset input + D => Bsr_out -- Data input + ); + + +-- BSR_DFF : process (slowest_sync_clk) +-- begin +-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then +-- bus_struct_reset(i) <= Bsr_out; +-- end if; +-- end process; + end generate BSR_OUT_DFF; + +-- --------------------------------------------------------------------------- +-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s) +-- --------------------------------------------------------------------------- + bsr_outn <= not(Bsr_out); + + ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate + FDRE_BSR_N : FDRE + generic map ( + INIT => '0') -- Initial value of register ('0' or '1') + port map ( + Q => interconnect_aresetn(i), -- Data output + C => slowest_sync_clk, -- Clock input + CE => '1', -- Clock enable input + R => '0', -- Synchronous reset input + D => bsr_outn -- Data input + ); +-- BSR_DFF : process (slowest_sync_clk) +-- begin +-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then +-- interconnect_aresetn(i) <= not (Bsr_out); +-- end if; +-- end process; + end generate ACTIVE_LOW_BSR_OUT_DFF; +------------------------------------------------------------------------------- + +-- ---------------------------------------------------------------------------- +-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s) +-- ---------------------------------------------------------------------------- + PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate + FDRE_PER : FDRE + generic map ( + INIT => '1') -- Initial value of register ('0' or '1') + port map ( + Q => peripheral_reset(i), -- Data output + C => slowest_sync_clk, -- Clock input + CE => '1', -- Clock enable input + R => '0', -- Synchronous reset input + D => Pr_out -- Data input + ); +-- PR_DFF : process (slowest_sync_clk) +-- begin +-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then +-- peripheral_reset(i) <= Pr_out; +-- end if; +-- end process; + end generate PR_OUT_DFF; + +-- ---------------------------------------------------------------------------- +-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s) +-- ---A------------------------------------------------------------------------- + pr_outn <= not(Pr_out); + + ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate + FDRE_PER_N : FDRE + generic map ( + INIT => '0') -- Initial value of register ('0' or '1') + port map ( + Q => peripheral_aresetn(i), -- Data output + C => slowest_sync_clk, -- Clock input + CE => '1', -- Clock enable input + R => '0', -- Synchronous reset input + D => Pr_outn -- Data input + ); +-- ACTIVE_LOW_PR_DFF : process (slowest_sync_clk) +-- begin +-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then +-- peripheral_aresetn(i) <= not(Pr_out); +-- end if; +-- end process; + end generate ACTIVE_LOW_PR_OUT_DFF; +------------------------------------------------------------------------------- +-- This process defines the RstcPPCreset and MB_Reset outputs +------------------------------------------------------------------------------- + -- Rstc_output_PROCESS_0: process (Slowest_sync_clk) + -- begin + -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + -- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and + -- core_cnt_0(1) and core_cnt_0(0)) + -- or Core_out; + -- RstcPPCresetchip_0 <= Chip_out; + -- RstcPPCresetsys_0 <= Sys_out; + -- end if; + -- end process; + + -- Rstc_output_PROCESS_1: process (Slowest_sync_clk) + -- begin + -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then + -- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and + -- core_cnt_1(1) and core_cnt_1(0)) + -- or Core_out; + -- RstcPPCresetchip_1 <= Chip_out; + -- RstcPPCresetsys_1 <= Sys_out; + -- end if; + -- end process; + +------------------------------------------------------------------------------- + +--------------------------------------------------------------------------------- +---- This process delays signals so the the edge can be detected and used +---- Double register to sync up with slowest_sync_clk +--------------------------------------------------------------------------------- +-- DELAY_PROCESS_0: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- core_reset_req_0_d1 <= Core_Reset_Req_0; +-- core_reset_req_0_d2 <= core_reset_req_0_d1; +-- core_reset_req_0_d3 <= core_reset_req_0_d2; +-- end if; +-- end process; +-- +-- DELAY_PROCESS_1: process (Slowest_sync_clk) +-- begin +-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- core_reset_req_1_d1 <= Core_Reset_Req_1; +-- core_reset_req_1_d2 <= core_reset_req_1_d1; +-- core_reset_req_1_d3 <= core_reset_req_1_d2; +-- end if; +-- end process; + + +-- ** -- ------------------------------------------------------------------------------- +-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a +-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks +-- ** -- ------------------------------------------------------------------------------- +-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_13.UPCNT_N +-- ** -- generic map (C_SIZE => 4) +-- ** -- port map( +-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); +-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC; +-- ** -- Load => '0', -- in STD_LOGIC; +-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC; +-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC; +-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) +-- ** -- ); +-- ** -- +-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_13.UPCNT_N +-- ** -- generic map (C_SIZE => 4) +-- ** -- port map( +-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0); +-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC; +-- ** -- Load => '0', -- in STD_LOGIC; +-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC; +-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC; +-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0) +-- ** -- ); +-- ** -- +-- ** -- ------------------------------------------------------------------------------- +-- ** -- -- CORE_RESET_PROCESS +-- ** -- ------------------------------------------------------------------------------- +-- ** -- -- This generates the reset pulse and the count enable to core reset counter +-- ** -- -- +-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk) +-- ** -- begin +-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1)); +-- ** -- --or not core_req_edge_0; +-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3); +-- ** -- end if; +-- ** -- end process; +-- ** -- +-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk) +-- ** -- begin +-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then +-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1)); +-- ** -- --or not core_req_edge_1; +-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3); +-- ** -- end if; +-- ** -- end process; + +------------------------------------------------------------------------------- +-- This instantiates a low pass filter to filter both External and Auxiliary +-- Reset Inputs. +------------------------------------------------------------------------------- + EXT_LPF : entity proc_sys_reset_v5_0_13.LPF + generic map ( + C_EXT_RST_WIDTH => C_EXT_RST_WIDTH, + C_AUX_RST_WIDTH => C_AUX_RST_WIDTH, + C_EXT_RESET_HIGH => C_EXT_RESET_HIGH, + C_AUX_RESET_HIGH => C_AUX_RESET_HIGH + ) + port map( + MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic + Dcm_locked => dcm_locked, -- in std_logic + External_System_Reset => ext_reset_in, -- in std_logic + Auxiliary_System_Reset => aux_reset_in, -- in std_logic + Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic + Lpf_reset => lpf_reset -- out std_logic + ); + +------------------------------------------------------------------------------- +-- This instantiates the sequencer +-- This controls the time between resets becoming inactive +------------------------------------------------------------------------------- + + -- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1; + + -- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1; + + SEQ : entity proc_sys_reset_v5_0_13.SEQUENCE_PSR + --generic map ( + -- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH + --) + port map( + Lpf_reset => lpf_reset, -- in std_logic + --System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic + --Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic + Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic + Bsr_out => Bsr_out, -- out std_logic + Pr_out => Pr_out, -- out std_logic + --Core_out => open, -- Core_out, -- out std_logic + --Chip_out => open, -- Chip_out, -- out std_logic + --Sys_out => open, -- Sys_out, -- out std_logic + MB_out => MB_out); -- out std_logic + +end imp; + +--END_SINGLE_FILE_TAG + + diff --git a/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_7s_mmcm.vh b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_7s_mmcm.vh new file mode 100644 index 0000000..652d7d1 --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_7s_mmcm.vh @@ -0,0 +1,671 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: 7 Series || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_7s_pll.vh b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_7s_pll.vh new file mode 100644 index 0000000..6a3e7c0 --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_7s_pll.vh @@ -0,0 +1,531 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: PLLE2 DRP +// Module Name: plle2_drp_func.h +// Version: 2.00 +// Target Devices: 7 Series || PLL +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// Updated for CR663854. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_mmcm.vh b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_mmcm.vh new file mode 100644 index 0000000..2cffa9a --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_mmcm.vh @@ -0,0 +1,671 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: UltraScale Architecture || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_pll.vh b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_pll.vh new file mode 100644 index 0000000..9439f23 --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_pll.vh @@ -0,0 +1,530 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 6/15/2015 +// Design Name: PLLE3 DRP +// Module Name: plle3_drp_func.h +// Version: 1.10 +// Target Devices: UltraScale Architecture +// Tool versions: 2015.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// PM_Rise bits have been removed for PLLE3 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [759:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001 //19 + + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 19 + ); + + reg [639:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0010_1111_01, //1 + 10'b0010_0011_11, //2 + 10'b0011_0011_11, //3 + 10'b0010_0001_11, //4 + 10'b0010_0110_11, //5 + 10'b0010_1010_11, //6 + 10'b0010_1010_11, //7 + 10'b0011_0110_11, //8 + 10'b0010_1100_11, //9 + 10'b0010_1100_11, //10 + 10'b0010_1100_11, //11 + 10'b0010_0010_11, //12 + 10'b0011_1100_11, //13 + 10'b0011_1100_11, //14 + 10'b0011_1100_11, //15 + 10'b0011_1100_11, //16 + 10'b0011_0010_11, //17 + 10'b0011_0010_11, //18 + 10'b0011_0010_11 //19 + }; + + mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits +// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + + diff --git a/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_plus_mmcm.vh b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_plus_mmcm.vh new file mode 100644 index 0000000..61edf85 --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -0,0 +1,861 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_plus_pll.vh b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_plus_pll.vh new file mode 100644 index 0000000..1d2dc69 --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/d0f7/mmcm_pll_drp_func_us_plus_pll.vh @@ -0,0 +1,536 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ +// Date: 6/15/2015 +// Design Name: PLLE4 DRP +// Module Name: plle4_drp_func.h +// Version: 2.0 +// Target Devices: UltraScale+ Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// M_Rise bits have been removed for PLLE3 +// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for +// Ultrascale+ and for max M of 21 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); +`endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [839:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001, //19 + 40'b11111_11111_0111110100_1111101001_0000000001, //20 + 40'b11111_11111_0111011011_1111101001_0000000001 //21 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [209:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0011_0111_11, //1 not legal in Ultrascale+ + 10'b0011_0111_11, //2 + 10'b0011_0011_11, //3 + 10'b0011_1001_11, //4 + 10'b0011_0001_11, //5 + 10'b0100_1110_11, //6 + 10'b0011_0110_11, //7 + 10'b0011_1010_11, //8 + 10'b0111_1001_11, //9 + 10'b0111_1001_11, //10 + 10'b0101_0110_11, //11 + 10'b1100_0101_11, //12 + 10'b0101_1010_11, //13 + 10'b0110_0110_11, //14 + 10'b0110_1010_11, //15 + 10'b0111_0110_11, //16 + 10'b1111_0101_11, //17 + 10'b1100_0110_11, //18 + 10'b1110_0001_11, //19 + 10'b1101_0110_11, //20 + 10'b1111_0001_11 //21 + }; + + mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" +// will need to divide the doubled clock VCO clock frequency by +// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will +// need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/LAB2/src/pak_depak/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd b/LAB2/src/pak_depak/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd new file mode 100644 index 0000000..f7bb80c --- /dev/null +++ b/LAB2/src/pak_depak/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd @@ -0,0 +1,1263 @@ + +--Generic Help +--C_CDC_TYPE : Defines the type of CDC needed +-- 0 means pulse synchronizer. Used to transfer one clock pulse +-- from prmry domain to scndry domain. +-- 1 means level synchronizer. Used to transfer level signal. +-- 2 means level synchronizer with ack. Used to transfer level +-- signal. Input signal should change only when prmry_ack is detected +-- +--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal +-- Set to 0 when incoming signal is purely floped signal. +-- +--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases +-- it might be needed. +-- 0 means reset not needed for sync flops +-- 1 means reset needed for sync flops. i +-- In this case prmry_resetn should be in prmry clock, +-- while scndry_reset should be in scndry clock. +-- +--C_SINGLE_BIT : CDC should normally be done for single bit signals only. +-- However, based on design buses can also be CDC'ed. +-- 0 means it is a bus. In this case input be connected to prmry_vect_in. +-- Output is on scndry_vect_out. +-- 1 means it is a single bit. In this case input be connected to prmry_in. +-- Output is on scndry_out. +-- +--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 +-- +--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. +-- Value of 0, 1 is allowed only for level CDC. +-- Min value for Pulse CDC is 2 +-- +--Whenever this file is used following XDC constraint has to be added + +-- set_false_path -to [get_pins -hier *cdc_to*/D] + + +--IO Ports +-- +-- prmry_aclk : clock of originating domain (source domain) +-- prmry_resetn : sync reset of originating clock domain (source domain) +-- prmry_in : input signal bit. This should be a pure flop output without +-- any combi logic. This is source. +-- prmry_vect_in : bus signal. From Source domain. +-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. +-- Used only when C_CDC_TYPE = 2 +-- scndry_aclk : destination clock. +-- scndry_resetn : sync reset of destination domain +-- scndry_out : sync'ed output in destination domain. Single bit. +-- scndry_vect_out : sync'ed output in destination domain. bus. + + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_misc.all; +library unisim; +use unisim.vcomponents.FDR; + + + +entity cdc_sync is + generic ( + C_CDC_TYPE : integer range 0 to 2 := 1 ; + -- 0 is pulse synch + -- 1 is level synch + -- 2 is ack based level sync + C_RESET_STATE : integer range 0 to 1 := 0 ; + -- 0 is reset not needed + -- 1 is reset needed + C_SINGLE_BIT : integer range 0 to 1 := 1 ; + -- 0 is bus input + -- 1 is single bit input + C_FLOP_INPUT : integer range 0 to 1 := 0 ; + C_VECTOR_WIDTH : integer range 0 to 64 := 32 ; + C_MTBF_STAGES : integer range 0 to 6 := 2 + -- Vector Data witdth + ); + + port ( + prmry_aclk : in std_logic ; -- + prmry_resetn : in std_logic ; -- + prmry_in : in std_logic ; -- + prmry_vect_in : in std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) ; -- + prmry_ack : out std_logic ; + -- + scndry_aclk : in std_logic ; -- + scndry_resetn : in std_logic ; -- + -- + -- Primary to Secondary Clock Crossing -- + scndry_out : out std_logic ; -- + -- + scndry_vect_out : out std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) -- + + ); + +end cdc_sync; + +------------------------------------------------------------------------------- +-- Architecture +------------------------------------------------------------------------------- +architecture implementation of cdc_sync is + +attribute DowngradeIPIdentifiedWarnings : string; +attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; + +--attribute DONT_TOUCH : STRING; +--attribute KEEP : STRING; +--attribute DONT_TOUCH of implementation : architecture is "yes"; +signal prmry_resetn1 : std_logic := '0'; +signal scndry_resetn1 : std_logic := '0'; +signal prmry_reset2 : std_logic := '0'; +signal scndry_reset2 : std_logic := '0'; +--attribute KEEP of prmry_resetn1 : signal is "true"; +--attribute KEEP of scndry_resetn1 : signal is "true"; + +------------------------------------------------------------------------------- +-- Functions +------------------------------------------------------------------------------- + +-- No Functions Declared + +------------------------------------------------------------------------------- +-- Constants Declarations +------------------------------------------------------------------------------- + +-- No Constants Declared + +------------------------------------------------------------------------------- +-- Begin architecture logic +------------------------------------------------------------------------------- +begin + +HAS_RESET : if C_RESET_STATE = 1 generate +begin +prmry_resetn1 <= prmry_resetn; +scndry_resetn1 <= scndry_resetn; + +end generate HAS_RESET; + +HAS_NO_RESET : if C_RESET_STATE = 0 generate +begin + +prmry_resetn1 <= '1'; +scndry_resetn1 <= '1'; + +end generate HAS_NO_RESET; + +prmry_reset2 <= not prmry_resetn1; +scndry_reset2 <= not scndry_resetn1; + + +-- Generate PULSE clock domain crossing +GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate + +-- Primary to Secondary +signal s_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; +signal s_out_d2 : std_logic := '0'; +signal s_out_d3 : std_logic := '0'; +signal s_out_d4 : std_logic := '0'; +signal s_out_d5 : std_logic := '0'; +signal s_out_d6 : std_logic := '0'; +signal s_out_d7 : std_logic := '0'; +signal s_out_re : std_logic := '0'; +signal prmry_in_xored : std_logic := '0'; +signal p_in_d1_cdc_from : std_logic := '0'; + +signal srst_d1 : std_logic := '0'; +signal srst_d2 : std_logic := '0'; +signal srst_d3 : std_logic := '0'; +signal srst_d4 : std_logic := '0'; +signal srst_d5 : std_logic := '0'; +signal srst_d6 : std_logic := '0'; +signal srst_d7 : std_logic := '0'; + + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Pulse Clock Crossing ** + --** PRIMARY TO SECONDARY OPEN-ENDED ** + --***************************************************************************** + +scndry_vect_out <= (others => '0'); +prmry_ack <= '0'; + +prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; + +--------------------------------------REG_P_IN : process(prmry_aclk) +-------------------------------------- begin +-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +-------------------------------------- p_in_d1_cdc_from <= '0'; +-------------------------------------- else +-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; +-------------------------------------- end if; +-------------------------------------- end if; +-------------------------------------- end process REG_P_IN; + + + +REG_P_IN_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_in_d1_cdc_from, + C => prmry_aclk, + D => prmry_in_xored, + R => prmry_reset2 + ); + + + + + +REG_P_IN2_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d1_cdc_to, + C => scndry_aclk, + D => p_in_d1_cdc_from, + R => scndry_reset2 + ); + + + +------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) +------------------------------------ begin +------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then +------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------------ s_out_d2 <= '0'; +------------------------------------ s_out_d3 <= '0'; +------------------------------------ s_out_d4 <= '0'; +------------------------------------ s_out_d5 <= '0'; +------------------------------------ s_out_d6 <= '0'; +------------------------------------ s_out_d7 <= '0'; +------------------------------------ scndry_out <= '0'; +------------------------------------ else +------------------------------------ s_out_d2 <= s_out_d1_cdc_to; +------------------------------------ s_out_d3 <= s_out_d2; +------------------------------------ s_out_d4 <= s_out_d3; +------------------------------------ s_out_d5 <= s_out_d4; +------------------------------------ s_out_d6 <= s_out_d5; +------------------------------------ s_out_d7 <= s_out_d6; +------------------------------------ scndry_out <= s_out_re; +------------------------------------ end if; +------------------------------------ end if; +------------------------------------ end process P_IN_CROSS2SCNDRY; + + + + +P_IN_CROSS2SCNDRY_s_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d2, + C => scndry_aclk, + D => s_out_d1_cdc_to, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d3, + C => scndry_aclk, + D => s_out_d2, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d4, + C => scndry_aclk, + D => s_out_d3, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d5, + C => scndry_aclk, + D => s_out_d4, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d6, + C => scndry_aclk, + D => s_out_d5, + R => scndry_reset2 + ); + + + +P_IN_CROSS2SCNDRY_s_out_d7 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d7, + C => scndry_aclk, + D => s_out_d6, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_scndry_out : component FDR + generic map(INIT => '0' + )port map ( + Q => scndry_out, + C => scndry_aclk, + D => s_out_re, + R => scndry_reset2 + ); + +s_rst_d1 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d1, + C => scndry_aclk, + D => '1', + R => scndry_reset2 + ); +s_rst_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d2, + C => scndry_aclk, + D => srst_d1, + R => scndry_reset2 + ); +s_rst_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d3, + C => scndry_aclk, + D => srst_d2, + R => scndry_reset2 + ); + +s_rst_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d4, + C => scndry_aclk, + D => srst_d3, + R => scndry_reset2 + ); + + +s_rst_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d5, + C => scndry_aclk, + D => srst_d4, + R => scndry_reset2 + ); + +s_rst_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d6, + C => scndry_aclk, + D => srst_d5, + R => scndry_reset2 + ); + +s_rst_d7 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d7, + C => scndry_aclk, + D => srst_d6, + R => scndry_reset2 + ); + +MTBF_2 : if C_MTBF_STAGES = 2 generate +begin + s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3); + +end generate MTBF_2; + +MTBF_3 : if C_MTBF_STAGES = 3 generate +begin + s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4); + +end generate MTBF_3; + +MTBF_4 : if C_MTBF_STAGES = 4 generate +begin + s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5); + +end generate MTBF_4; + +MTBF_5 : if C_MTBF_STAGES = 5 generate +begin + s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6); + +end generate MTBF_5; + +MTBF_6 : if C_MTBF_STAGES = 6 generate +begin + s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7); + +end generate MTBF_6; + + -- Feed secondary pulse out + +end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; + + +-- Generate LEVEL clock domain crossing with reset state = 0 +GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate +begin +-- Primary to Secondary + +SINGLE_BIT : if C_SINGLE_BIT = 1 generate + +signal p_level_in_d1_cdc_from : std_logic := '0'; +signal p_level_in_int : std_logic := '0'; +signal s_level_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; +signal s_level_out_d2 : std_logic := '0'; +signal s_level_out_d3 : std_logic := '0'; +signal s_level_out_d4 : std_logic := '0'; +signal s_level_out_d5 : std_logic := '0'; +signal s_level_out_d6 : std_logic := '0'; + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic + +scndry_vect_out <= (others => '0'); +prmry_ack <= '0'; + + +INPUT_FLOP : if C_FLOP_INPUT = 1 generate +begin + +---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) +---------------------------------- begin +---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +---------------------------------- p_level_in_d1_cdc_from <= '0'; +---------------------------------- else +---------------------------------- p_level_in_d1_cdc_from <= prmry_in; +---------------------------------- end if; +---------------------------------- end if; +---------------------------------- end process REG_PLEVEL_IN; + + +REG_PLEVEL_IN_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_in_d1_cdc_from, + C => prmry_aclk, + D => prmry_in, + R => prmry_reset2 + ); + + + p_level_in_int <= p_level_in_d1_cdc_from; + +end generate INPUT_FLOP; + + +NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate +begin + + p_level_in_int <= prmry_in; + +end generate NO_INPUT_FLOP; + + +CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d1_cdc_to, + C => scndry_aclk, + D => p_level_in_int, + R => scndry_reset2 + ); + + +------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) +------------------------------ begin +------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then +------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------ s_level_out_d2 <= '0'; +------------------------------ s_level_out_d3 <= '0'; +------------------------------ s_level_out_d4 <= '0'; +------------------------------ s_level_out_d5 <= '0'; +------------------------------ s_level_out_d6 <= '0'; +------------------------------ else +------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; +------------------------------ s_level_out_d3 <= s_level_out_d2; +------------------------------ s_level_out_d4 <= s_level_out_d3; +------------------------------ s_level_out_d5 <= s_level_out_d4; +------------------------------ s_level_out_d6 <= s_level_out_d5; +------------------------------ end if; +------------------------------ end if; +------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; + + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d2, + C => scndry_aclk, + D => s_level_out_d1_cdc_to, + R => scndry_reset2 + ); + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d3, + C => scndry_aclk, + D => s_level_out_d2, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d4, + C => scndry_aclk, + D => s_level_out_d3, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d5, + C => scndry_aclk, + D => s_level_out_d4, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d6, + C => scndry_aclk, + D => s_level_out_d5, + R => scndry_reset2 + ); + + + + + + + +MTBF_L1 : if C_MTBF_STAGES = 1 generate +begin + scndry_out <= s_level_out_d1_cdc_to; + + +end generate MTBF_L1; + +MTBF_L2 : if C_MTBF_STAGES = 2 generate +begin + + scndry_out <= s_level_out_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_out <= s_level_out_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_out <= s_level_out_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_out <= s_level_out_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_out <= s_level_out_d6; + + +end generate MTBF_L6; + +end generate SINGLE_BIT; + + + +MULTI_BIT : if C_SINGLE_BIT = 0 generate + +signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); +signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; +signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic + +scndry_out <= '0'; +prmry_ack <= '0'; + + +INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate +begin + + + +----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) +----------------------------------- begin +----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); +----------------------------------- else +----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; +----------------------------------- end if; +----------------------------------- end if; +----------------------------------- end process REG_PLEVEL_IN; + +FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate +begin + +REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_in_bus_d1_cdc_from (i), + C => prmry_aclk, + D => prmry_vect_in (i), + R => prmry_reset2 + ); +end generate FOR_REG_PLEVEL_IN; + + + + + + p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; + +end generate INPUT_FLOP_BUS; + + +NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate +begin + +p_level_in_bus_int <= prmry_vect_in; + +end generate NO_INPUT_FLOP_BUS; + +FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d1_cdc_to (i), + C => scndry_aclk, + D => p_level_in_bus_int (i), + R => scndry_reset2 + ); +end generate FOR_IN_cdc_to; + +----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) +----------------------------------------- begin +----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then +----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +----------------------------------------- s_level_out_bus_d2 <= (others => '0'); +----------------------------------------- s_level_out_bus_d3 <= (others => '0'); +----------------------------------------- s_level_out_bus_d4 <= (others => '0'); +----------------------------------------- s_level_out_bus_d5 <= (others => '0'); +----------------------------------------- s_level_out_bus_d6 <= (others => '0'); +----------------------------------------- else +----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; +----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; +----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; +----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; +----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; +----------------------------------------- end if; +----------------------------------------- end if; +----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; + + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d2 (i), + C => scndry_aclk, + D => s_level_out_bus_d1_cdc_to (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d3 (i), + C => scndry_aclk, + D => s_level_out_bus_d2 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d4 (i), + C => scndry_aclk, + D => s_level_out_bus_d3 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; + + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d5 (i), + C => scndry_aclk, + D => s_level_out_bus_d4 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d6 (i), + C => scndry_aclk, + D => s_level_out_bus_d5 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; + + + +MTBF_L1 : if C_MTBF_STAGES = 1 generate +begin + + scndry_vect_out <= s_level_out_bus_d1_cdc_to; + + +end generate MTBF_L1; + +MTBF_L2 : if C_MTBF_STAGES = 2 generate +begin + + scndry_vect_out <= s_level_out_bus_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_vect_out <= s_level_out_bus_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_vect_out <= s_level_out_bus_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_vect_out <= s_level_out_bus_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_vect_out <= s_level_out_bus_d6; + + +end generate MTBF_L6; + +end generate MULTI_BIT; + + +end generate GENERATE_LEVEL_P_S_CDC; + + +GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate +-- Primary to Secondary + + +signal p_level_in_d1_cdc_from : std_logic := '0'; +signal p_level_in_int : std_logic := '0'; +signal s_level_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; +signal s_level_out_d2 : std_logic := '0'; +signal s_level_out_d3 : std_logic := '0'; +signal s_level_out_d4 : std_logic := '0'; +signal s_level_out_d5 : std_logic := '0'; +signal s_level_out_d6 : std_logic := '0'; +signal p_level_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; +signal p_level_out_d2 : std_logic := '0'; +signal p_level_out_d3 : std_logic := '0'; +signal p_level_out_d4 : std_logic := '0'; +signal p_level_out_d5 : std_logic := '0'; +signal p_level_out_d6 : std_logic := '0'; +signal p_level_out_d7 : std_logic := '0'; +signal scndry_out_int : std_logic := '0'; +signal prmry_pulse_ack : std_logic := '0'; + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; + + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic +scndry_vect_out <= (others => '0'); + + +INPUT_FLOP : if C_FLOP_INPUT = 1 generate +begin + +------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) +------------------------------------------ begin +------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then +------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------------------ p_level_in_d1_cdc_from <= '0'; +------------------------------------------ else +------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; +------------------------------------------ end if; +------------------------------------------ end if; +------------------------------------------ end process REG_PLEVEL_IN; + + + +REG_PLEVEL_IN_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_in_d1_cdc_from, + C => prmry_aclk, + D => prmry_in, + R => prmry_reset2 + ); + + + p_level_in_int <= p_level_in_d1_cdc_from; + +end generate INPUT_FLOP; + + +NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate +begin + + p_level_in_int <= prmry_in; + +end generate NO_INPUT_FLOP; + + +CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d1_cdc_to, + C => scndry_aclk, + D => p_level_in_int, + R => scndry_reset2 + ); + + +------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) +------------------------------------------------ begin +------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then +------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------------------------ s_level_out_d2 <= '0'; +------------------------------------------------ s_level_out_d3 <= '0'; +------------------------------------------------ s_level_out_d4 <= '0'; +------------------------------------------------ s_level_out_d5 <= '0'; +------------------------------------------------ s_level_out_d6 <= '0'; +------------------------------------------------ else +------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; +------------------------------------------------ s_level_out_d3 <= s_level_out_d2; +------------------------------------------------ s_level_out_d4 <= s_level_out_d3; +------------------------------------------------ s_level_out_d5 <= s_level_out_d4; +------------------------------------------------ s_level_out_d6 <= s_level_out_d5; +------------------------------------------------ end if; +------------------------------------------------ end if; +------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; + + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d2, + C => scndry_aclk, + D => s_level_out_d1_cdc_to, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d3, + C => scndry_aclk, + D => s_level_out_d2, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d4, + C => scndry_aclk, + D => s_level_out_d3, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d5, + C => scndry_aclk, + D => s_level_out_d4, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d6, + C => scndry_aclk, + D => s_level_out_d5, + R => scndry_reset2 + ); + + + + + + + + +--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) +--------------------------------------------------- begin +--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +--------------------------------------------------- p_level_out_d1_cdc_to <= '0'; +--------------------------------------------------- p_level_out_d2 <= '0'; +--------------------------------------------------- p_level_out_d3 <= '0'; +--------------------------------------------------- p_level_out_d4 <= '0'; +--------------------------------------------------- p_level_out_d5 <= '0'; +--------------------------------------------------- p_level_out_d6 <= '0'; +--------------------------------------------------- p_level_out_d7 <= '0'; +--------------------------------------------------- prmry_ack <= '0'; +--------------------------------------------------- else +--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; +--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; +--------------------------------------------------- p_level_out_d3 <= p_level_out_d2; +--------------------------------------------------- p_level_out_d4 <= p_level_out_d3; +--------------------------------------------------- p_level_out_d5 <= p_level_out_d4; +--------------------------------------------------- p_level_out_d6 <= p_level_out_d5; +--------------------------------------------------- p_level_out_d7 <= p_level_out_d6; +--------------------------------------------------- prmry_ack <= prmry_pulse_ack; +--------------------------------------------------- end if; +--------------------------------------------------- end if; +--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; + + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d1_cdc_to, + C => prmry_aclk, + D => scndry_out_int, + R => prmry_reset2 + ); + + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d2, + C => prmry_aclk, + D => p_level_out_d1_cdc_to, + R => prmry_reset2 + ); + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d3, + C => prmry_aclk, + D => p_level_out_d2, + R => prmry_reset2 + ); + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d4, + C => prmry_aclk, + D => p_level_out_d3, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d5, + C => prmry_aclk, + D => p_level_out_d4, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d6, + C => prmry_aclk, + D => p_level_out_d5, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d7, + C => prmry_aclk, + D => p_level_out_d6, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR + generic map(INIT => '0' + )port map ( + Q => prmry_ack, + C => prmry_aclk, + D => prmry_pulse_ack, + R => prmry_reset2 + ); + + + + + + + + + + + + + + + +MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate +begin + + scndry_out_int <= s_level_out_d2; + --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; + prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_out_int <= s_level_out_d3; + --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; + prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_out_int <= s_level_out_d4; + --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; + prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_out_int <= s_level_out_d5; + --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; + prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_out_int <= s_level_out_d6; + --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; + prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; + + +end generate MTBF_L6; + + scndry_out <= scndry_out_int; + + +end generate GENERATE_LEVEL_ACK_P_S_CDC; + + +end implementation; + + + + diff --git a/LAB2/src/pak_depak/pak_depak.bd b/LAB2/src/pak_depak/pak_depak.bd new file mode 100644 index 0000000..268f47c --- /dev/null +++ b/LAB2/src/pak_depak/pak_depak.bd @@ -0,0 +1,474 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x9157799052A71E23", + "device": "xc7a35tcpg236-1", + "name": "pak_depak", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "None", + "tool_version": "2020.2" + }, + "design_tree": { + "proc_sys_reset_0": "", + "clk_wiz_0": "", + "AXI4Stream_UART_0": "", + "depacketizer_0": "", + "packetizer_0": "" + }, + "interface_ports": { + "usb_uart": { + "mode": "Master", + "vlnv": "xilinx.com:interface:uart_rtl:1.0" + } + }, + "ports": { + "reset": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_HIGH" + } + } + }, + "sys_clock": { + "type": "clk", + "direction": "I", + "parameters": { + "FREQ_HZ": { + "value": "100000000" + }, + "PHASE": { + "value": "0.000" + } + } + } + }, + "components": { + "proc_sys_reset_0": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "pak_depak_proc_sys_reset_0_0", + "xci_path": "ip\\pak_depak_proc_sys_reset_0_0\\pak_depak_proc_sys_reset_0_0.xci", + "inst_hier_path": "proc_sys_reset_0", + "parameters": { + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "clk_wiz_0": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "xci_name": "pak_depak_clk_wiz_0_1", + "xci_path": "ip\\pak_depak_clk_wiz_0_1\\pak_depak_clk_wiz_0_1.xci", + "inst_hier_path": "clk_wiz_0", + "parameters": { + "CLK_IN1_BOARD_INTERFACE": { + "value": "sys_clock" + }, + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "AXI4Stream_UART_0": { + "vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1", + "xci_name": "pak_depak_AXI4Stream_UART_0_0", + "xci_path": "ip\\pak_depak_AXI4Stream_UART_0_0\\pak_depak_AXI4Stream_UART_0_0.xci", + "inst_hier_path": "AXI4Stream_UART_0", + "parameters": { + "UART_BOARD_INTERFACE": { + "value": "usb_uart" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "depacketizer_0": { + "vlnv": "xilinx.com:module_ref:depacketizer:1.0", + "xci_name": "pak_depak_depacketizer_0_0", + "xci_path": "ip\\pak_depak_depacketizer_0_0\\pak_depak_depacketizer_0_0.xci", + "inst_hier_path": "depacketizer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "depacketizer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + }, + "packetizer_0": { + "vlnv": "xilinx.com:module_ref:packetizer:1.0", + "xci_name": "pak_depak_packetizer_0_0", + "xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci", + "inst_hier_path": "packetizer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "packetizer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + } + }, + "interface_nets": { + "AXI4Stream_UART_0_UART": { + "interface_ports": [ + "usb_uart", + "AXI4Stream_UART_0/UART" + ] + }, + "packetizer_0_m_axis": { + "interface_ports": [ + "packetizer_0/m_axis", + "AXI4Stream_UART_0/S00_AXIS_TX" + ] + }, + "depacketizer_0_m_axis": { + "interface_ports": [ + "depacketizer_0/m_axis", + "packetizer_0/s_axis" + ] + }, + "AXI4Stream_UART_0_M00_AXIS_RX": { + "interface_ports": [ + "AXI4Stream_UART_0/M00_AXIS_RX", + "depacketizer_0/s_axis" + ] + } + }, + "nets": { + "reset_1": { + "ports": [ + "reset", + "proc_sys_reset_0/ext_reset_in", + "clk_wiz_0/reset" + ] + }, + "sys_clock_1": { + "ports": [ + "sys_clock", + "clk_wiz_0/clk_in1" + ] + }, + "clk_wiz_0_clk_out1": { + "ports": [ + "clk_wiz_0/clk_out1", + "AXI4Stream_UART_0/clk_uart", + "proc_sys_reset_0/slowest_sync_clk", + "AXI4Stream_UART_0/m00_axis_rx_aclk", + "AXI4Stream_UART_0/s00_axis_tx_aclk", + "depacketizer_0/clk", + "packetizer_0/clk" + ] + }, + "proc_sys_reset_0_peripheral_reset": { + "ports": [ + "proc_sys_reset_0/peripheral_reset", + "AXI4Stream_UART_0/rst" + ] + }, + "clk_wiz_0_locked": { + "ports": [ + "clk_wiz_0/locked", + "proc_sys_reset_0/dcm_locked" + ] + }, + "proc_sys_reset_0_peripheral_aresetn": { + "ports": [ + "proc_sys_reset_0/peripheral_aresetn", + "AXI4Stream_UART_0/m00_axis_rx_aresetn", + "AXI4Stream_UART_0/s00_axis_tx_aresetn", + "depacketizer_0/aresetn", + "packetizer_0/aresetn" + ] + } + } + } +} \ No newline at end of file diff --git a/LAB2/src/pak_depak/pak_depak.bda b/LAB2/src/pak_depak/pak_depak.bda new file mode 100644 index 0000000..0240c83 --- /dev/null +++ b/LAB2/src/pak_depak/pak_depak.bda @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + active + 2 + PM + + + pak_depak + BC + + + 2 + pak_depak + VR + + + + + + + diff --git a/LAB2/src/pak_depak/ui/bd_c9b29a54.ui b/LAB2/src/pak_depak/ui/bd_c9b29a54.ui new file mode 100644 index 0000000..259ec2e --- /dev/null +++ b/LAB2/src/pak_depak/ui/bd_c9b29a54.ui @@ -0,0 +1,33 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.00128", + "Default View_TopLeft":"-106,-179", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS +# -string -flagsOSRD +preplace port usb_uart -pg 1 -lvl 6 -x 1360 -y 180 -defaultsOSRD +preplace port reset -pg 1 -lvl 0 -x 0 -y 190 -defaultsOSRD +preplace port sys_clock -pg 1 -lvl 0 -x 0 -y 270 -defaultsOSRD +preplace inst proc_sys_reset_0 -pg 1 -lvl 2 -x 380 -y 210 -defaultsOSRD +preplace inst clk_wiz_0 -pg 1 -lvl 1 -x 110 -y 260 -defaultsOSRD +preplace inst AXI4Stream_UART_0 -pg 1 -lvl 5 -x 1190 -y 170 -defaultsOSRD +preplace inst depacketizer_0 -pg 1 -lvl 3 -x 670 -y 90 -defaultsOSRD +preplace inst packetizer_0 -pg 1 -lvl 4 -x 910 -y 110 -defaultsOSRD +preplace netloc reset_1 1 0 2 20 190 NJ +preplace netloc sys_clock_1 1 0 1 NJ 270 +preplace netloc clk_wiz_0_clk_out1 1 1 4 200 310 550 170 780 20 1030 +preplace netloc proc_sys_reset_0_peripheral_reset 1 2 3 NJ 210 790J 30 1020 +preplace netloc clk_wiz_0_locked 1 1 1 210 250n +preplace netloc proc_sys_reset_0_peripheral_aresetn 1 2 3 560 180 800 190 1040 +preplace netloc AXI4Stream_UART_0_UART 1 5 1 N 180 +preplace netloc depacketizer_0_m_axis 1 3 1 N 90 +preplace netloc packetizer_0_m_axis 1 4 1 N 110 +preplace netloc AXI4Stream_UART_0_M00_AXIS_RX 1 2 4 550 10 NJ 10 NJ 10 1340 +levelinfo -pg 1 0 110 380 670 910 1190 1360 +pagesize -pg 1 -db -bbox -sgen -110 0 1470 330 +" +} +{ + "da_board_cnt":"1", + "da_clkrst_cnt":"3" +} diff --git a/LAB2/vivado/lab2/lab2.xpr b/LAB2/vivado/lab2/lab2.xpr index 5e66faf..611d728 100644 --- a/LAB2/vivado/lab2/lab2.xpr +++ b/LAB2/vivado/lab2/lab2.xpr @@ -83,6 +83,18 @@ + + + + + + + + + + + + @@ -107,18 +119,6 @@ - - - - - - - - - - - - diff --git a/LAB2/vivado/pak_depak/pak_depak.xpr b/LAB2/vivado/pak_depak/pak_depak.xpr new file mode 100644 index 0000000..3c87775 --- /dev/null +++ b/LAB2/vivado/pak_depak/pak_depak.xpr @@ -0,0 +1,231 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + +