From 460378cdaad7d99e2c19248b963048b86ebcd4d7 Mon Sep 17 00:00:00 2001 From: Cd16d Date: Fri, 16 May 2025 16:44:46 +0200 Subject: [PATCH] Update digilent_jstk2.vhd to clarify the required packet delay for SPI IP-Core functionality --- LAB3/src/digilent_jstk2.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/LAB3/src/digilent_jstk2.vhd b/LAB3/src/digilent_jstk2.vhd index 1cd9e6f..c2978a0 100644 --- a/LAB3/src/digilent_jstk2.vhd +++ b/LAB3/src/digilent_jstk2.vhd @@ -3,7 +3,7 @@ USE IEEE.STD_LOGIC_1164.ALL; ENTITY digilent_jstk2 IS GENERIC ( - DELAY_US : INTEGER := 100; -- Delay (in us) between two packets + DELAY_US : INTEGER := 100; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz) SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz) );