diff --git a/LAB1/lab1_kit_car b/LAB1/lab1_kit_car deleted file mode 160000 index ec3447b..0000000 --- a/LAB1/lab1_kit_car +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ec3447bd8cd0d2d809c93a686076bfcfaff174af diff --git a/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/gui_handlers.wdf b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..fef8f15 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/gui_handlers.wdf @@ -0,0 +1,67 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637466696c65766965775f72656c6f6164:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6170706c79:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6e6f:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3933:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:3235:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626f61726463686f6f7365725f626f6172645f7461626c65:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3337:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3736:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f73657268656c706572735f6a756d705f746f5f646f776e6c6f6164735f6469726563746f7279:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f73657268656c706572735f726566726573685f666f6c6465725f766965775f746f5f7265666c6563745f65787465726e616c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f736572726563656e746c697374707265766965775f726563656e745f6469726563746f72696573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f68656c70:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:3132:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:3332:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c6f6164:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:37:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e756d6a6f627363686f6f7365725f6e756d6265725f6f665f6a6f6273:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3230:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3132:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:3137:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636b6167657472656570616e656c5f7061636b6167655f747265655f70616e656c:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f70726f6772616d5f646576696365:3139:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f726566726573685f646576696365:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:3330:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f737065636966795f62697473747265616d5f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563747461625f636c6f73655f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563747461625f72656c6f6164:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f637573746f6d5f636f6d6d616e6473:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f7761726e696e675f616e645f6572726f725f6d657373616765735f696e5f6d65737361676573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:736561726368636f6d6d616e64636f6d706f6e656e745f717569636b5f616363657373:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73657474696e67736469616c6f675f70726f6a6563745f74726565:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73657474696e677370726f6a65637467656e6572616c706167655f63686f6f73655f6465766963655f666f725f796f75725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7369676e616c7472656570616e656c5f7369676e616c5f747265655f7461626c65:3132:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f7365727461626c655f7372635f63686f6f7365725f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:746f756368706f696e747375727665796469616c6f675f6e6f:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:746f756368706f696e747375727665796469616c6f675f72656d696e645f6d655f6c61746572:31:00:00 +eof:199942204 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/java_command_handlers.wdf b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/java_command_handlers.wdf new file mode 100644 index 0000000..e160966 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/java_command_handlers.wdf @@ -0,0 +1,29 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65786974617070:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:666c6970746f766965777461736b696d706c656d656e746174696f6e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:666c6970746f766965777461736b73796e746865736973:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3332:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3135:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3135:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72656672657368646576696365:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3332:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e736368656d61746963:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:39:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766564657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3330:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:74696d696e67636f6e73747261696e747377697a617264:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965776c61796f7574636d64:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:37:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b70726f6772616d616e646465627567:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b70726f6a6563746d616e61676572:38:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:31:00:00 +eof:1221856172 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/project.wpc b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/project.wpc new file mode 100644 index 0000000..cd0ff06 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:22 +6d6f64655f636f756e7465727c4755494d6f6465:3 +eof: diff --git a/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/synthesis.wdf b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/synthesis.wdf new file mode 100644 index 0000000..a3f7b29 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/synthesis.wdf @@ -0,0 +1,42 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613335746370673233362d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:4b697474436172:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323173:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313031382e3530344d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:31382e3530304d42:00:00 +eof:359947987 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/synthesis_details.wdf b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/synthesis_details.wdf new file mode 100644 index 0000000..78f8d66 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.cache/wt/synthesis_details.wdf @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.hw/lab1_kit_car.lpr b/LAB1/lab1_kit_car/lab1_kit_car.hw/lab1_kit_car.lpr new file mode 100644 index 0000000..7deddf8 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.hw/lab1_kit_car.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.ip_user_files/README.txt b/LAB1/lab1_kit_car/lab1_kit_car.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.Vivado_Implementation.queue.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.init_design.begin.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..f204e56 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.init_design.end.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.opt_design.begin.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..f204e56 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.opt_design.end.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.phys_opt_design.begin.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.phys_opt_design.begin.rst new file mode 100644 index 0000000..f204e56 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.phys_opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.phys_opt_design.end.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.phys_opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.place_design.begin.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..f204e56 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.place_design.end.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.route_design.begin.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..f204e56 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.route_design.end.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.vivado.begin.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..eb5caeb --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.vivado.end.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.write_bitstream.begin.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..f204e56 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.write_bitstream.end.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/ISEWrap.js b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000..97a2ecb --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/ISEWrap.sh b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000..f679f2e --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_bus_skew_routed.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_bus_skew_routed.rpt new file mode 100644 index 0000000..2531096 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:47 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file KittCar_bus_skew_routed.rpt -pb KittCar_bus_skew_routed.pb -rpx KittCar_bus_skew_routed.rpx +| Design : KittCar +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------ + +Bus Skew Report + +No bus skew constraints + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_clock_utilization_routed.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_clock_utilization_routed.rpt new file mode 100644 index 0000000..fccb418 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_clock_utilization_routed.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:47 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_clock_utilization -file KittCar_clock_utilization_routed.rpt +| Design : KittCar +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 64 | 0 | 10.000 | sys_clk_pin | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 0 | 10.000 | sys_clk_pin | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 64 | 1200 | 53 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 1 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | sys_clk_pin | 10.000 | {0.000 5.000} | 64 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+-----+----+-----------------------+ +| | X0 | X1 | HORIZONTAL PROG DELAY | ++----+-----+----+-----------------------+ +| Y2 | 0 | 0 | 0 | +| Y1 | 0 | 0 | 0 | +| Y0 | 64 | 0 | 0 | ++----+-----+----+-----------------------+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 64 | 0 | 64 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y26 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} +#endgroup diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_control_sets_placed.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_control_sets_placed.rpt new file mode 100644 index 0000000..ea5b8a2 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_control_sets_placed.rpt @@ -0,0 +1,81 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:34 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file KittCar_control_sets_placed.rpt +| Design : KittCar +| Device : xc7a35t +------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 3 | +| Minimum number of control sets | 3 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 7 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 3 | +| >= 0 to < 4 | 1 | +| >= 4 to < 6 | 0 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 2 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 48 | 12 | +| No | Yes | No | 1 | 1 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 16 | 7 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++-----------------+---------------+------------------+------------------+----------------+--------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | ++-----------------+---------------+------------------+------------------+----------------+--------------+ +| up_reg_i_2_n_0 | | reset_IBUF | 1 | 1 | 1.00 | +| clk_IBUF_BUFG | leds_sr0 | reset_IBUF | 7 | 16 | 2.29 | +| clk_IBUF_BUFG | | reset_IBUF | 12 | 48 | 4.00 | ++-----------------+---------------+------------------+------------------+----------------+--------------+ + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_drc_opted.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_drc_opted.rpt new file mode 100644 index 0000000..ff56469 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_drc_opted.rpt @@ -0,0 +1,67 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:32 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_drc -file KittCar_drc_opted.rpt -pb KittCar_drc_opted.pb -rpx KittCar_drc_opted.rpx +| Design : KittCar +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 4 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| DPIP-1 | Warning | Input pipelining | 1 | +| DPOP-1 | Warning | PREG Output pipelining | 1 | +| DPOP-2 | Warning | MREG Output pipelining | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +DPIP-1#1 Warning +Input pipelining +DSP counter2 input counter2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP counter2 output counter2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP counter2 multiplier stage counter2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_drc_routed.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_drc_routed.rpt new file mode 100644 index 0000000..7dbb19a --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_drc_routed.rpt @@ -0,0 +1,73 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:46 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_drc -file KittCar_drc_routed.rpt -pb KittCar_drc_routed.pb -rpx KittCar_drc_routed.rpx +| Design : KittCar +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 5 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| DPIP-1 | Warning | Input pipelining | 1 | +| DPOP-1 | Warning | PREG Output pipelining | 1 | +| DPOP-2 | Warning | MREG Output pipelining | 1 | +| PDRC-153 | Warning | Gated clock check | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +DPIP-1#1 Warning +Input pipelining +DSP counter2 input counter2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP counter2 output counter2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP counter2 multiplier stage counter2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +PDRC-153#1 Warning +Gated clock check +Net up_reg_i_2_n_0 is a gated clock net sourced by a combinational pin up_reg_i_2/O, cell up_reg_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_io_placed.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_io_placed.rpt new file mode 100644 index 0000000..702865b --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_io_placed.rpt @@ -0,0 +1,280 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:34 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_io -file KittCar_io_placed.rpt +| Design : KittCar +| Device : xc7a35t +| Speed File : -1 +| Package : cpg236 +| Package Version : FINAL 2014-02-19 +| Package Pin Delay Version : VERS. 2.0 2014-02-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 34 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A18 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| B14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B15 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| C9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| C12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C13 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C15 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D17 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| D19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| E1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| E3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| E19 | led[1] | High Range | IO_L3N_T0_DQS_EMCCLK_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| F18 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| F19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| G19 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H17 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| H18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H19 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| J17 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| J19 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| K2 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| K8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | led[15] | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| L18 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| L19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| M12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M18 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | led[13] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| P1 | led[14] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P3 | led[12] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P19 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| R2 | sw[15] | High Range | IO_L1P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R3 | sw[11] | High Range | IO_L2P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | sw[14] | High Range | IO_L3P_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| T2 | sw[10] | High Range | IO_L1N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| T3 | sw[9] | High Range | IO_L2N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| T17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| T18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U1 | sw[13] | High Range | IO_L3N_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| U2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | led[11] | High Range | IO_L9P_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U14 | led[6] | High Range | IO_25_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U15 | led[5] | High Range | IO_L23P_T3_A03_D19_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U16 | led[0] | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | reset | High Range | IO_L18N_T2_A11_D27_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| U19 | led[2] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V2 | sw[8] | High Range | IO_L5P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| V3 | led[9] | High Range | IO_L6P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | led[8] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V14 | led[7] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V15 | sw[5] | High Range | IO_L21P_T3_DQS_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V16 | sw[1] | High Range | IO_L19P_T3_A10_D26_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V17 | sw[0] | High Range | IO_L19N_T3_A09_D25_VREF_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V19 | led[3] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W2 | sw[12] | High Range | IO_L5N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| W3 | led[10] | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | clk | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| W6 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| W9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| W10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| W11 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W13 | sw[7] | High Range | IO_L22P_T3_A05_D21_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| W14 | sw[6] | High Range | IO_L22N_T3_A04_D20_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| W15 | sw[4] | High Range | IO_L21N_T3_DQS_A06_D22_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| W16 | sw[2] | High Range | IO_L20P_T3_A08_D24_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| W17 | sw[3] | High Range | IO_L20N_T3_A07_D23_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| W18 | led[4] | High Range | IO_L16P_T2_CSI_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W19 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_methodology_drc_routed.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_methodology_drc_routed.rpt new file mode 100644 index 0000000..c72ea63 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_methodology_drc_routed.rpt @@ -0,0 +1,206 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:46 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_methodology -file KittCar_methodology_drc_routed.rpt -pb KittCar_methodology_drc_routed.pb -rpx KittCar_methodology_drc_routed.rpx +| Design : KittCar +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Fully Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 34 ++-----------+----------+-------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-------------------------------+------------+ +| TIMING-18 | Warning | Missing input or output delay | 33 | +| TIMING-20 | Warning | Non-clocked latch | 1 | ++-----------+----------+-------------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-18#1 Warning +Missing input or output delay +An input delay is missing on reset relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#2 Warning +Missing input or output delay +An input delay is missing on sw[0] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#3 Warning +Missing input or output delay +An input delay is missing on sw[10] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#4 Warning +Missing input or output delay +An input delay is missing on sw[11] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#5 Warning +Missing input or output delay +An input delay is missing on sw[12] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#6 Warning +Missing input or output delay +An input delay is missing on sw[13] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#7 Warning +Missing input or output delay +An input delay is missing on sw[14] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#8 Warning +Missing input or output delay +An input delay is missing on sw[15] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#9 Warning +Missing input or output delay +An input delay is missing on sw[1] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#10 Warning +Missing input or output delay +An input delay is missing on sw[2] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#11 Warning +Missing input or output delay +An input delay is missing on sw[3] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#12 Warning +Missing input or output delay +An input delay is missing on sw[4] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#13 Warning +Missing input or output delay +An input delay is missing on sw[5] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#14 Warning +Missing input or output delay +An input delay is missing on sw[6] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#15 Warning +Missing input or output delay +An input delay is missing on sw[7] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#16 Warning +Missing input or output delay +An input delay is missing on sw[8] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#17 Warning +Missing input or output delay +An input delay is missing on sw[9] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#18 Warning +Missing input or output delay +An output delay is missing on led[0] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#19 Warning +Missing input or output delay +An output delay is missing on led[10] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#20 Warning +Missing input or output delay +An output delay is missing on led[11] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#21 Warning +Missing input or output delay +An output delay is missing on led[12] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#22 Warning +Missing input or output delay +An output delay is missing on led[13] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#23 Warning +Missing input or output delay +An output delay is missing on led[14] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#24 Warning +Missing input or output delay +An output delay is missing on led[15] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#25 Warning +Missing input or output delay +An output delay is missing on led[1] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#26 Warning +Missing input or output delay +An output delay is missing on led[2] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#27 Warning +Missing input or output delay +An output delay is missing on led[3] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#28 Warning +Missing input or output delay +An output delay is missing on led[4] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#29 Warning +Missing input or output delay +An output delay is missing on led[5] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#30 Warning +Missing input or output delay +An output delay is missing on led[6] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#31 Warning +Missing input or output delay +An output delay is missing on led[7] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#32 Warning +Missing input or output delay +An output delay is missing on led[8] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#33 Warning +Missing input or output delay +An output delay is missing on led[9] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-20#1 Warning +Non-clocked latch +The latch up_reg cannot be properly analyzed as its control pin up_reg/G is not reached by a timing clock +Related violations: + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_power_routed.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_power_routed.rpt new file mode 100644 index 0000000..da5bb94 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_power_routed.rpt @@ -0,0 +1,147 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:47 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_power -file KittCar_power_routed.rpt -pb KittCar_power_summary_routed.pb -rpx KittCar_power_routed.rpx +| Design : KittCar +| Device : xc7a35tcpg236-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.075 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.003 | +| Device Static (W) | 0.072 | +| Effective TJA (C/W) | 5.0 | +| Max Ambient (C) | 84.6 | +| Junction Temperature (C) | 25.4 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | <0.001 | 3 | --- | --- | +| Slice Logic | <0.001 | 212 | --- | --- | +| LUT as Logic | <0.001 | 93 | 20800 | 0.45 | +| CARRY4 | <0.001 | 22 | 8150 | 0.27 | +| Register | <0.001 | 65 | 41600 | 0.16 | +| Others | 0.000 | 4 | --- | --- | +| Signals | <0.001 | 158 | --- | --- | +| DSPs | <0.001 | 1 | 90 | 1.11 | +| I/O | <0.001 | 34 | 106 | 32.08 | +| Static Power | 0.072 | | | | +| Total | 0.075 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.012 | 0.003 | 0.010 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.013 | 0.000 | 0.013 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 5.0 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------------+--------+-----------------+ +| sys_clk_pin | clk | 10.0 | ++-------------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++---------+-----------+ +| Name | Power (W) | ++---------+-----------+ +| KittCar | 0.003 | ++---------+-----------+ + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_route_status.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_route_status.rpt new file mode 100644 index 0000000..8ad1f7f --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 357 : + # of nets not needing routing.......... : 195 : + # of internally routed nets........ : 195 : + # of routable nets..................... : 162 : + # of fully routed nets............. : 162 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_timing_summary_routed.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_timing_summary_routed.rpt new file mode 100644 index 0000000..79550bb --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_timing_summary_routed.rpt @@ -0,0 +1,1861 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:47 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file KittCar_timing_summary_routed.rpt -pb KittCar_timing_summary_routed.pb -rpx KittCar_timing_summary_routed.rpx -warn_on_violation +| Design : KittCar +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (2) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (2) +5. checking no_input_delay (17) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (2) +------------------------ + There is 1 register/latch pin with no clock driven by root clock pin: leds_sr_reg[0]/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: leds_sr_reg[15]/Q (HIGH) + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (2) +------------------------------------------------ + There are 2 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (17) +------------------------------- + There are 17 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 2.986 0.000 0 80 0.179 0.000 0 80 4.500 0.000 0 65 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +sys_clk_pin {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +sys_clk_pin 2.986 0.000 0 80 0.179 0.000 0 80 4.500 0.000 0 65 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_clk_pin + To Clock: sys_clk_pin + +Setup : 0 Failing Endpoints, Worst Slack 2.986ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.179ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.986ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[45]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 7.059ns (logic 3.755ns (53.193%) route 3.304ns (46.807%)) + Logic Levels: 20 (CARRY4=18 LUT2=1 LUT4=1) + Clock Path Skew: -0.028ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.785ns = ( 14.785 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.693 r counter_reg[36]_i_1/CO[3] + net (fo=1, routed) 0.000 11.693 counter_reg[36]_i_1_n_0 + SLICE_X10Y32 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.810 r counter_reg[40]_i_1/CO[3] + net (fo=1, routed) 0.000 11.810 counter_reg[40]_i_1_n_0 + SLICE_X10Y33 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 12.133 r counter_reg[44]_i_1/O[1] + net (fo=1, routed) 0.000 12.133 counter_reg[44]_i_1_n_6 + SLICE_X10Y33 FDCE r counter_reg[45]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.444 14.785 clk_IBUF_BUFG + SLICE_X10Y33 FDCE r counter_reg[45]/C + clock pessimism 0.260 15.045 + clock uncertainty -0.035 15.010 + SLICE_X10Y33 FDCE (Setup_fdce_C_D) 0.109 15.119 counter_reg[45] + ------------------------------------------------------------------- + required time 15.119 + arrival time -12.133 + ------------------------------------------------------------------- + slack 2.986 + +Slack (MET) : 2.994ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[47]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 7.051ns (logic 3.747ns (53.140%) route 3.304ns (46.860%)) + Logic Levels: 20 (CARRY4=18 LUT2=1 LUT4=1) + Clock Path Skew: -0.028ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.785ns = ( 14.785 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.693 r counter_reg[36]_i_1/CO[3] + net (fo=1, routed) 0.000 11.693 counter_reg[36]_i_1_n_0 + SLICE_X10Y32 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.810 r counter_reg[40]_i_1/CO[3] + net (fo=1, routed) 0.000 11.810 counter_reg[40]_i_1_n_0 + SLICE_X10Y33 CARRY4 (Prop_carry4_CI_O[3]) + 0.315 12.125 r counter_reg[44]_i_1/O[3] + net (fo=1, routed) 0.000 12.125 counter_reg[44]_i_1_n_4 + SLICE_X10Y33 FDCE r counter_reg[47]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.444 14.785 clk_IBUF_BUFG + SLICE_X10Y33 FDCE r counter_reg[47]/C + clock pessimism 0.260 15.045 + clock uncertainty -0.035 15.010 + SLICE_X10Y33 FDCE (Setup_fdce_C_D) 0.109 15.119 counter_reg[47] + ------------------------------------------------------------------- + required time 15.119 + arrival time -12.125 + ------------------------------------------------------------------- + slack 2.994 + +Slack (MET) : 3.070ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[46]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 6.975ns (logic 3.671ns (52.629%) route 3.304ns (47.371%)) + Logic Levels: 20 (CARRY4=18 LUT2=1 LUT4=1) + Clock Path Skew: -0.028ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.785ns = ( 14.785 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.693 r counter_reg[36]_i_1/CO[3] + net (fo=1, routed) 0.000 11.693 counter_reg[36]_i_1_n_0 + SLICE_X10Y32 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.810 r counter_reg[40]_i_1/CO[3] + net (fo=1, routed) 0.000 11.810 counter_reg[40]_i_1_n_0 + SLICE_X10Y33 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 12.049 r counter_reg[44]_i_1/O[2] + net (fo=1, routed) 0.000 12.049 counter_reg[44]_i_1_n_5 + SLICE_X10Y33 FDCE r counter_reg[46]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.444 14.785 clk_IBUF_BUFG + SLICE_X10Y33 FDCE r counter_reg[46]/C + clock pessimism 0.260 15.045 + clock uncertainty -0.035 15.010 + SLICE_X10Y33 FDCE (Setup_fdce_C_D) 0.109 15.119 counter_reg[46] + ------------------------------------------------------------------- + required time 15.119 + arrival time -12.049 + ------------------------------------------------------------------- + slack 3.070 + +Slack (MET) : 3.090ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[44]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 6.955ns (logic 3.651ns (52.493%) route 3.304ns (47.507%)) + Logic Levels: 20 (CARRY4=18 LUT2=1 LUT4=1) + Clock Path Skew: -0.028ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.785ns = ( 14.785 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.693 r counter_reg[36]_i_1/CO[3] + net (fo=1, routed) 0.000 11.693 counter_reg[36]_i_1_n_0 + SLICE_X10Y32 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.810 r counter_reg[40]_i_1/CO[3] + net (fo=1, routed) 0.000 11.810 counter_reg[40]_i_1_n_0 + SLICE_X10Y33 CARRY4 (Prop_carry4_CI_O[0]) + 0.219 12.029 r counter_reg[44]_i_1/O[0] + net (fo=1, routed) 0.000 12.029 counter_reg[44]_i_1_n_7 + SLICE_X10Y33 FDCE r counter_reg[44]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.444 14.785 clk_IBUF_BUFG + SLICE_X10Y33 FDCE r counter_reg[44]/C + clock pessimism 0.260 15.045 + clock uncertainty -0.035 15.010 + SLICE_X10Y33 FDCE (Setup_fdce_C_D) 0.109 15.119 counter_reg[44] + ------------------------------------------------------------------- + required time 15.119 + arrival time -12.029 + ------------------------------------------------------------------- + slack 3.090 + +Slack (MET) : 3.102ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[41]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 6.942ns (logic 3.638ns (52.404%) route 3.304ns (47.596%)) + Logic Levels: 19 (CARRY4=17 LUT2=1 LUT4=1) + Clock Path Skew: -0.029ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.784ns = ( 14.784 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.693 r counter_reg[36]_i_1/CO[3] + net (fo=1, routed) 0.000 11.693 counter_reg[36]_i_1_n_0 + SLICE_X10Y32 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 12.016 r counter_reg[40]_i_1/O[1] + net (fo=1, routed) 0.000 12.016 counter_reg[40]_i_1_n_6 + SLICE_X10Y32 FDCE r counter_reg[41]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.443 14.784 clk_IBUF_BUFG + SLICE_X10Y32 FDCE r counter_reg[41]/C + clock pessimism 0.260 15.044 + clock uncertainty -0.035 15.009 + SLICE_X10Y32 FDCE (Setup_fdce_C_D) 0.109 15.118 counter_reg[41] + ------------------------------------------------------------------- + required time 15.118 + arrival time -12.016 + ------------------------------------------------------------------- + slack 3.102 + +Slack (MET) : 3.110ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[43]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 6.934ns (logic 3.630ns (52.349%) route 3.304ns (47.651%)) + Logic Levels: 19 (CARRY4=17 LUT2=1 LUT4=1) + Clock Path Skew: -0.029ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.784ns = ( 14.784 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.693 r counter_reg[36]_i_1/CO[3] + net (fo=1, routed) 0.000 11.693 counter_reg[36]_i_1_n_0 + SLICE_X10Y32 CARRY4 (Prop_carry4_CI_O[3]) + 0.315 12.008 r counter_reg[40]_i_1/O[3] + net (fo=1, routed) 0.000 12.008 counter_reg[40]_i_1_n_4 + SLICE_X10Y32 FDCE r counter_reg[43]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.443 14.784 clk_IBUF_BUFG + SLICE_X10Y32 FDCE r counter_reg[43]/C + clock pessimism 0.260 15.044 + clock uncertainty -0.035 15.009 + SLICE_X10Y32 FDCE (Setup_fdce_C_D) 0.109 15.118 counter_reg[43] + ------------------------------------------------------------------- + required time 15.118 + arrival time -12.008 + ------------------------------------------------------------------- + slack 3.110 + +Slack (MET) : 3.186ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[42]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 6.858ns (logic 3.554ns (51.821%) route 3.304ns (48.179%)) + Logic Levels: 19 (CARRY4=17 LUT2=1 LUT4=1) + Clock Path Skew: -0.029ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.784ns = ( 14.784 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.693 r counter_reg[36]_i_1/CO[3] + net (fo=1, routed) 0.000 11.693 counter_reg[36]_i_1_n_0 + SLICE_X10Y32 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 11.932 r counter_reg[40]_i_1/O[2] + net (fo=1, routed) 0.000 11.932 counter_reg[40]_i_1_n_5 + SLICE_X10Y32 FDCE r counter_reg[42]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.443 14.784 clk_IBUF_BUFG + SLICE_X10Y32 FDCE r counter_reg[42]/C + clock pessimism 0.260 15.044 + clock uncertainty -0.035 15.009 + SLICE_X10Y32 FDCE (Setup_fdce_C_D) 0.109 15.118 counter_reg[42] + ------------------------------------------------------------------- + required time 15.118 + arrival time -11.932 + ------------------------------------------------------------------- + slack 3.186 + +Slack (MET) : 3.206ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[40]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 6.838ns (logic 3.534ns (51.680%) route 3.304ns (48.320%)) + Logic Levels: 19 (CARRY4=17 LUT2=1 LUT4=1) + Clock Path Skew: -0.029ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.784ns = ( 14.784 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.693 r counter_reg[36]_i_1/CO[3] + net (fo=1, routed) 0.000 11.693 counter_reg[36]_i_1_n_0 + SLICE_X10Y32 CARRY4 (Prop_carry4_CI_O[0]) + 0.219 11.912 r counter_reg[40]_i_1/O[0] + net (fo=1, routed) 0.000 11.912 counter_reg[40]_i_1_n_7 + SLICE_X10Y32 FDCE r counter_reg[40]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.443 14.784 clk_IBUF_BUFG + SLICE_X10Y32 FDCE r counter_reg[40]/C + clock pessimism 0.260 15.044 + clock uncertainty -0.035 15.009 + SLICE_X10Y32 FDCE (Setup_fdce_C_D) 0.109 15.118 counter_reg[40] + ------------------------------------------------------------------- + required time 15.118 + arrival time -11.912 + ------------------------------------------------------------------- + slack 3.206 + +Slack (MET) : 3.217ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[37]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 6.825ns (logic 3.521ns (51.588%) route 3.304ns (48.412%)) + Logic Levels: 18 (CARRY4=16 LUT2=1 LUT4=1) + Clock Path Skew: -0.031ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.782ns = ( 14.782 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 11.899 r counter_reg[36]_i_1/O[1] + net (fo=1, routed) 0.000 11.899 counter_reg[36]_i_1_n_6 + SLICE_X10Y31 FDCE r counter_reg[37]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.441 14.782 clk_IBUF_BUFG + SLICE_X10Y31 FDCE r counter_reg[37]/C + clock pessimism 0.260 15.042 + clock uncertainty -0.035 15.007 + SLICE_X10Y31 FDCE (Setup_fdce_C_D) 0.109 15.116 counter_reg[37] + ------------------------------------------------------------------- + required time 15.116 + arrival time -11.899 + ------------------------------------------------------------------- + slack 3.217 + +Slack (MET) : 3.225ns (required time - arrival time) + Source: counter_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: counter_reg[39]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 6.817ns (logic 3.513ns (51.531%) route 3.304ns (48.469%)) + Logic Levels: 18 (CARRY4=16 LUT2=1 LUT4=1) + Clock Path Skew: -0.031ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.782ns = ( 14.782 - 10.000 ) + Source Clock Delay (SCD): 5.073ns + Clock Pessimism Removal (CPR): 0.260ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=1, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.552 5.073 clk_IBUF_BUFG + SLICE_X10Y22 FDCE r counter_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y22 FDCE (Prop_fdce_C_Q) 0.518 5.591 r counter_reg[3]/Q + net (fo=3, routed) 0.990 6.581 counter_reg[3] + SLICE_X11Y25 LUT4 (Prop_lut4_I1_O) 0.124 6.705 r leds_sr[15]_i_58/O + net (fo=1, routed) 0.000 6.705 leds_sr[15]_i_58_n_0 + SLICE_X11Y25 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 7.255 r leds_sr_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 7.255 leds_sr_reg[15]_i_43_n_0 + SLICE_X11Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.369 r leds_sr_reg[15]_i_34/CO[3] + net (fo=1, routed) 0.000 7.369 leds_sr_reg[15]_i_34_n_0 + SLICE_X11Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.483 r leds_sr_reg[15]_i_25/CO[3] + net (fo=1, routed) 0.000 7.483 leds_sr_reg[15]_i_25_n_0 + SLICE_X11Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.597 r leds_sr_reg[15]_i_16/CO[3] + net (fo=1, routed) 0.000 7.597 leds_sr_reg[15]_i_16_n_0 + SLICE_X11Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.711 r leds_sr_reg[15]_i_7/CO[3] + net (fo=1, routed) 0.000 7.711 leds_sr_reg[15]_i_7_n_0 + SLICE_X11Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.825 f leds_sr_reg[15]_i_4/CO[3] + net (fo=67, routed) 2.305 10.131 load + SLICE_X10Y22 LUT2 (Prop_lut2_I1_O) 0.124 10.255 r counter[0]_i_4/O + net (fo=1, routed) 0.000 10.255 counter[0]_i_4_n_0 + SLICE_X10Y22 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 10.631 r counter_reg[0]_i_1/CO[3] + net (fo=1, routed) 0.000 10.631 counter_reg[0]_i_1_n_0 + SLICE_X10Y23 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.748 r counter_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 10.748 counter_reg[4]_i_1_n_0 + SLICE_X10Y24 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.865 r counter_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.009 10.874 counter_reg[8]_i_1_n_0 + SLICE_X10Y25 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 10.991 r counter_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 10.991 counter_reg[12]_i_1_n_0 + SLICE_X10Y26 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.108 r counter_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 11.108 counter_reg[16]_i_1_n_0 + SLICE_X10Y27 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.225 r counter_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 11.225 counter_reg[20]_i_1_n_0 + SLICE_X10Y28 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.342 r counter_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.000 11.342 counter_reg[24]_i_1_n_0 + SLICE_X10Y29 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.459 r counter_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 11.459 counter_reg[28]_i_1_n_0 + SLICE_X10Y30 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.576 r counter_reg[32]_i_1/CO[3] + net (fo=1, routed) 0.000 11.576 counter_reg[32]_i_1_n_0 + SLICE_X10Y31 CARRY4 (Prop_carry4_CI_O[3]) + 0.315 11.891 r counter_reg[36]_i_1/O[3] + net (fo=1, routed) 0.000 11.891 counter_reg[36]_i_1_n_4 + SLICE_X10Y31 FDCE r counter_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 10.000 10.000 r + W5 0.000 10.000 r clk (IN) + net (fo=0) 0.000 10.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 11.388 r clk_IBUF_inst/O + net (fo=1, routed) 1.862 13.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 13.341 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 1.441 14.782 clk_IBUF_BUFG + SLICE_X10Y31 FDCE r counter_reg[39]/C + clock pessimism 0.260 15.042 + clock uncertainty -0.035 15.007 + SLICE_X10Y31 FDCE (Setup_fdce_C_D) 0.109 15.116 counter_reg[39] + ------------------------------------------------------------------- + required time 15.116 + arrival time -11.891 + ------------------------------------------------------------------- + slack 3.225 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.179ns (arrival time - required time) + Source: leds_sr_reg[11]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[10]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.313ns (logic 0.186ns (59.453%) route 0.127ns (40.547%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.983ns + Source Clock Delay (SCD): 1.470ns + Clock Pessimism Removal (CPR): 0.500ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.587 1.470 clk_IBUF_BUFG + SLICE_X3Y30 FDCE r leds_sr_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y30 FDCE (Prop_fdce_C_Q) 0.141 1.611 r leds_sr_reg[11]/Q + net (fo=4, routed) 0.127 1.738 led_OBUF[11] + SLICE_X2Y30 LUT6 (Prop_lut6_I0_O) 0.045 1.783 r leds_sr[10]_i_1/O + net (fo=1, routed) 0.000 1.783 p_1_in[10] + SLICE_X2Y30 FDCE r leds_sr_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.856 1.983 clk_IBUF_BUFG + SLICE_X2Y30 FDCE r leds_sr_reg[10]/C + clock pessimism -0.500 1.483 + SLICE_X2Y30 FDCE (Hold_fdce_C_D) 0.121 1.604 leds_sr_reg[10] + ------------------------------------------------------------------- + required time -1.604 + arrival time 1.783 + ------------------------------------------------------------------- + slack 0.179 + +Slack (MET) : 0.202ns (arrival time - required time) + Source: leds_sr_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.306ns (logic 0.186ns (60.821%) route 0.120ns (39.179%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.981ns + Source Clock Delay (SCD): 1.468ns + Clock Pessimism Removal (CPR): 0.500ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.585 1.468 clk_IBUF_BUFG + SLICE_X0Y21 FDCE r leds_sr_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y21 FDCE (Prop_fdce_C_Q) 0.141 1.609 r leds_sr_reg[2]/Q + net (fo=4, routed) 0.120 1.729 led_OBUF[2] + SLICE_X1Y21 LUT5 (Prop_lut5_I1_O) 0.045 1.774 r leds_sr[1]_i_1/O + net (fo=1, routed) 0.000 1.774 p_1_in[1] + SLICE_X1Y21 FDCE r leds_sr_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.854 1.981 clk_IBUF_BUFG + SLICE_X1Y21 FDCE r leds_sr_reg[1]/C + clock pessimism -0.500 1.481 + SLICE_X1Y21 FDCE (Hold_fdce_C_D) 0.091 1.572 leds_sr_reg[1] + ------------------------------------------------------------------- + required time -1.572 + arrival time 1.774 + ------------------------------------------------------------------- + slack 0.202 + +Slack (MET) : 0.204ns (arrival time - required time) + Source: leds_sr_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.308ns (logic 0.186ns (60.324%) route 0.122ns (39.676%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.981ns + Source Clock Delay (SCD): 1.468ns + Clock Pessimism Removal (CPR): 0.500ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.585 1.468 clk_IBUF_BUFG + SLICE_X1Y21 FDCE r leds_sr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y21 FDCE (Prop_fdce_C_Q) 0.141 1.609 r leds_sr_reg[1]/Q + net (fo=4, routed) 0.122 1.731 led_OBUF[1] + SLICE_X0Y21 LUT6 (Prop_lut6_I1_O) 0.045 1.776 r leds_sr[2]_i_1/O + net (fo=1, routed) 0.000 1.776 p_1_in[2] + SLICE_X0Y21 FDCE r leds_sr_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.854 1.981 clk_IBUF_BUFG + SLICE_X0Y21 FDCE r leds_sr_reg[2]/C + clock pessimism -0.500 1.481 + SLICE_X0Y21 FDCE (Hold_fdce_C_D) 0.091 1.572 leds_sr_reg[2] + ------------------------------------------------------------------- + required time -1.572 + arrival time 1.776 + ------------------------------------------------------------------- + slack 0.204 + +Slack (MET) : 0.226ns (arrival time - required time) + Source: leds_sr_reg[13]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[12]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.331ns (logic 0.209ns (63.180%) route 0.122ns (36.820%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.983ns + Source Clock Delay (SCD): 1.470ns + Clock Pessimism Removal (CPR): 0.500ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.587 1.470 clk_IBUF_BUFG + SLICE_X2Y30 FDCE r leds_sr_reg[13]/C + ------------------------------------------------------------------- ------------------- + SLICE_X2Y30 FDCE (Prop_fdce_C_Q) 0.164 1.634 r leds_sr_reg[13]/Q + net (fo=4, routed) 0.122 1.756 led_OBUF[13] + SLICE_X3Y30 LUT6 (Prop_lut6_I0_O) 0.045 1.801 r leds_sr[12]_i_1/O + net (fo=1, routed) 0.000 1.801 p_1_in[12] + SLICE_X3Y30 FDCE r leds_sr_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.856 1.983 clk_IBUF_BUFG + SLICE_X3Y30 FDCE r leds_sr_reg[12]/C + clock pessimism -0.500 1.483 + SLICE_X3Y30 FDCE (Hold_fdce_C_D) 0.092 1.575 leds_sr_reg[12] + ------------------------------------------------------------------- + required time -1.575 + arrival time 1.801 + ------------------------------------------------------------------- + slack 0.226 + +Slack (MET) : 0.230ns (arrival time - required time) + Source: leds_sr_reg[12]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[13]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.363ns (logic 0.186ns (51.285%) route 0.177ns (48.715%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.983ns + Source Clock Delay (SCD): 1.470ns + Clock Pessimism Removal (CPR): 0.500ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.587 1.470 clk_IBUF_BUFG + SLICE_X3Y30 FDCE r leds_sr_reg[12]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y30 FDCE (Prop_fdce_C_Q) 0.141 1.611 r leds_sr_reg[12]/Q + net (fo=4, routed) 0.177 1.788 led_OBUF[12] + SLICE_X2Y30 LUT6 (Prop_lut6_I1_O) 0.045 1.833 r leds_sr[13]_i_1/O + net (fo=1, routed) 0.000 1.833 p_1_in[13] + SLICE_X2Y30 FDCE r leds_sr_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.856 1.983 clk_IBUF_BUFG + SLICE_X2Y30 FDCE r leds_sr_reg[13]/C + clock pessimism -0.500 1.483 + SLICE_X2Y30 FDCE (Hold_fdce_C_D) 0.120 1.603 leds_sr_reg[13] + ------------------------------------------------------------------- + required time -1.603 + arrival time 1.833 + ------------------------------------------------------------------- + slack 0.230 + +Slack (MET) : 0.271ns (arrival time - required time) + Source: leds_sr_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.186ns (49.488%) route 0.190ns (50.512%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.981ns + Source Clock Delay (SCD): 1.469ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.586 1.469 clk_IBUF_BUFG + SLICE_X0Y20 FDCE r leds_sr_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y20 FDCE (Prop_fdce_C_Q) 0.141 1.610 r leds_sr_reg[4]/Q + net (fo=4, routed) 0.190 1.800 led_OBUF[4] + SLICE_X0Y21 LUT6 (Prop_lut6_I0_O) 0.045 1.845 r leds_sr[3]_i_1/O + net (fo=1, routed) 0.000 1.845 p_1_in[3] + SLICE_X0Y21 FDCE r leds_sr_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.854 1.981 clk_IBUF_BUFG + SLICE_X0Y21 FDCE r leds_sr_reg[3]/C + clock pessimism -0.499 1.482 + SLICE_X0Y21 FDCE (Hold_fdce_C_D) 0.092 1.574 leds_sr_reg[3] + ------------------------------------------------------------------- + required time -1.574 + arrival time 1.845 + ------------------------------------------------------------------- + slack 0.271 + +Slack (MET) : 0.273ns (arrival time - required time) + Source: leds_sr_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[8]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.378ns (logic 0.186ns (49.191%) route 0.192ns (50.809%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.981ns + Source Clock Delay (SCD): 1.469ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.586 1.469 clk_IBUF_BUFG + SLICE_X0Y20 FDCE r leds_sr_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y20 FDCE (Prop_fdce_C_Q) 0.141 1.610 r leds_sr_reg[7]/Q + net (fo=4, routed) 0.192 1.802 led_OBUF[7] + SLICE_X0Y21 LUT6 (Prop_lut6_I1_O) 0.045 1.847 r leds_sr[8]_i_1/O + net (fo=1, routed) 0.000 1.847 p_1_in[8] + SLICE_X0Y21 FDCE r leds_sr_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.854 1.981 clk_IBUF_BUFG + SLICE_X0Y21 FDCE r leds_sr_reg[8]/C + clock pessimism -0.499 1.482 + SLICE_X0Y21 FDCE (Hold_fdce_C_D) 0.092 1.574 leds_sr_reg[8] + ------------------------------------------------------------------- + required time -1.574 + arrival time 1.847 + ------------------------------------------------------------------- + slack 0.273 + +Slack (MET) : 0.277ns (arrival time - required time) + Source: leds_sr_reg[10]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.381ns (logic 0.209ns (54.902%) route 0.172ns (45.098%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.983ns + Source Clock Delay (SCD): 1.470ns + Clock Pessimism Removal (CPR): 0.500ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.587 1.470 clk_IBUF_BUFG + SLICE_X2Y30 FDCE r leds_sr_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X2Y30 FDCE (Prop_fdce_C_Q) 0.164 1.634 r leds_sr_reg[10]/Q + net (fo=4, routed) 0.172 1.806 led_OBUF[10] + SLICE_X3Y30 LUT6 (Prop_lut6_I1_O) 0.045 1.851 r leds_sr[11]_i_1/O + net (fo=1, routed) 0.000 1.851 p_1_in[11] + SLICE_X3Y30 FDCE r leds_sr_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.856 1.983 clk_IBUF_BUFG + SLICE_X3Y30 FDCE r leds_sr_reg[11]/C + clock pessimism -0.500 1.483 + SLICE_X3Y30 FDCE (Hold_fdce_C_D) 0.091 1.574 leds_sr_reg[11] + ------------------------------------------------------------------- + required time -1.574 + arrival time 1.851 + ------------------------------------------------------------------- + slack 0.277 + +Slack (MET) : 0.280ns (arrival time - required time) + Source: leds_sr_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[5]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.372ns (logic 0.186ns (49.998%) route 0.186ns (50.002%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.982ns + Source Clock Delay (SCD): 1.469ns + Clock Pessimism Removal (CPR): 0.513ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.586 1.469 clk_IBUF_BUFG + SLICE_X0Y20 FDCE r leds_sr_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y20 FDCE (Prop_fdce_C_Q) 0.141 1.610 r leds_sr_reg[4]/Q + net (fo=4, routed) 0.186 1.796 led_OBUF[4] + SLICE_X0Y20 LUT6 (Prop_lut6_I1_O) 0.045 1.841 r leds_sr[5]_i_1/O + net (fo=1, routed) 0.000 1.841 p_1_in[5] + SLICE_X0Y20 FDCE r leds_sr_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.855 1.982 clk_IBUF_BUFG + SLICE_X0Y20 FDCE r leds_sr_reg[5]/C + clock pessimism -0.513 1.469 + SLICE_X0Y20 FDCE (Hold_fdce_C_D) 0.092 1.561 leds_sr_reg[5] + ------------------------------------------------------------------- + required time -1.561 + arrival time 1.841 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.284ns (arrival time - required time) + Source: leds_sr_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: leds_sr_reg[6]/D + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.186ns (49.432%) route 0.190ns (50.568%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.982ns + Source Clock Delay (SCD): 1.469ns + Clock Pessimism Removal (CPR): 0.513ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.226 0.226 r clk_IBUF_inst/O + net (fo=1, routed) 0.631 0.858 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.884 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.586 1.469 clk_IBUF_BUFG + SLICE_X0Y20 FDCE r leds_sr_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y20 FDCE (Prop_fdce_C_Q) 0.141 1.610 r leds_sr_reg[7]/Q + net (fo=4, routed) 0.190 1.800 led_OBUF[7] + SLICE_X0Y20 LUT6 (Prop_lut6_I0_O) 0.045 1.845 r leds_sr[6]_i_1/O + net (fo=1, routed) 0.000 1.845 p_1_in[6] + SLICE_X0Y20 FDCE r leds_sr_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 0.414 0.414 r clk_IBUF_inst/O + net (fo=1, routed) 0.685 1.099 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.128 r clk_IBUF_BUFG_inst/O + net (fo=64, routed) 0.855 1.982 clk_IBUF_BUFG + SLICE_X0Y20 FDCE r leds_sr_reg[6]/C + clock pessimism -0.513 1.469 + SLICE_X0Y20 FDCE (Hold_fdce_C_D) 0.092 1.561 leds_sr_reg[6] + ------------------------------------------------------------------- + required time -1.561 + arrival time 1.845 + ------------------------------------------------------------------- + slack 0.284 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_clk_pin +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 clk_IBUF_BUFG_inst/I +Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X10Y22 counter_reg[0]/C +Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X10Y24 counter_reg[10]/C +Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X10Y24 counter_reg[11]/C +Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X10Y25 counter_reg[12]/C +Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X10Y25 counter_reg[13]/C +Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X10Y25 counter_reg[14]/C +Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X10Y25 counter_reg[15]/C +Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X10Y26 counter_reg[16]/C +Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X10Y26 counter_reg[17]/C +Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y24 counter_reg[10]/C +Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y24 counter_reg[11]/C +Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y25 counter_reg[12]/C +Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y25 counter_reg[13]/C +Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y25 counter_reg[14]/C +Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y25 counter_reg[15]/C +Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y28 counter_reg[24]/C +Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y28 counter_reg[25]/C +Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y28 counter_reg[26]/C +Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y28 counter_reg[27]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y24 counter_reg[10]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y24 counter_reg[11]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y25 counter_reg[12]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y25 counter_reg[13]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y25 counter_reg[14]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y25 counter_reg[15]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y29 counter_reg[28]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y29 counter_reg[29]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y29 counter_reg[30]/C +High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X10Y29 counter_reg[31]/C + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_utilization_placed.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_utilization_placed.rpt new file mode 100644 index 0000000..5ecfab9 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_utilization_placed.rpt @@ -0,0 +1,212 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:34 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_utilization -file KittCar_utilization_placed.rpt -pb KittCar_utilization_placed.pb +| Design : KittCar +| Device : 7a35tcpg236-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 93 | 0 | 20800 | 0.45 | +| LUT as Logic | 93 | 0 | 20800 | 0.45 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 65 | 0 | 41600 | 0.16 | +| Register as Flip Flop | 64 | 0 | 41600 | 0.15 | +| Register as Latch | 1 | 0 | 41600 | <0.01 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 1 | Yes | - | Set | +| 64 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------------------------+------+-------+-----------+-------+ +| Slice | 31 | 0 | 8150 | 0.38 | +| SLICEL | 12 | 0 | | | +| SLICEM | 19 | 0 | | | +| LUT as Logic | 93 | 0 | 20800 | 0.45 | +| using O5 output only | 0 | | | | +| using O6 output only | 65 | | | | +| using O5 and O6 | 28 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 65 | 0 | 41600 | 0.16 | +| Register driven from within the Slice | 63 | | | | +| Register driven from outside the Slice | 2 | | | | +| LUT in front of the register is unused | 0 | | | | +| LUT in front of the register is used | 2 | | | | +| Unique Control Sets | 3 | | 8150 | 0.04 | ++--------------------------------------------+------+-------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| DSPs | 1 | 0 | 90 | 1.11 | +| DSP48E1 only | 1 | | | | ++----------------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 34 | 34 | 106 | 32.08 | +| IOB Master Pads | 16 | | | | +| IOB Slave Pads | 17 | | | | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 64 | Flop & Latch | +| LUT2 | 51 | LUT | +| LUT4 | 32 | LUT | +| CARRY4 | 22 | CarryLogic | +| IBUF | 18 | IO | +| OBUF | 16 | IO | +| LUT3 | 16 | LUT | +| LUT6 | 15 | LUT | +| LUT5 | 4 | LUT | +| LUT1 | 3 | LUT | +| LDPE | 1 | Flop & Latch | +| DSP48E1 | 1 | Block Arithmetic | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/htr.txt b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/htr.txt new file mode 100644 index 0000000..115224b --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log KittCar.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source KittCar.tcl -notrace diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/project.wdf b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/project.wdf new file mode 100644 index 0000000..61908fb --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6635356365666130633361663437363461656435356437643038343135393562:506172656e742050412070726f6a656374204944:00 +eof:3337883414 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/rundef.js b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/rundef.js new file mode 100644 index 0000000..2e5b3b0 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2020.2/bin;"; +} else { + PathVal = "C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2020.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log KittCar.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source KittCar.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/runme.bat b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/runme.bat new file mode 100644 index 0000000..44f0077 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/runme.sh b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/runme.sh new file mode 100644 index 0000000..05c5e51 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2020.2/bin +else + PATH=C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2020.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log KittCar.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source KittCar.tcl -notrace + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/usage_statistics_webtalk.html b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..9fd6ac4 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,745 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version3064766
date_generatedMon Mar 17 20:34:53 2025os_platformWIN64
product_versionVivado v2020.2 (64-bit)project_idf55cefa0c3af4764aed55d7d0841595b
project_iteration22random_id883cc468a2bd5c84ae5bff6c9bd19760
registration_id883cc468a2bd5c84ae5bff6c9bd19760route_designTRUE
target_devicexc7a35ttarget_familyartix7
target_packagecpg236target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_name13th Gen Intel(R) Core(TM) i3-1315Ucpu_speed2496 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
gui_handlers
abstractfileview_reload=1addsrcwizard_specify_hdl_netlist_block_design=1addsrcwizard_specify_or_create_constraint_files=2basedialog_apply=2
basedialog_cancel=4basedialog_no=1basedialog_ok=93basedialog_yes=25
boardchooser_board_table=6cmdmsgdialog_ok=5constraintschooserpanel_add_files=1createsrcfiledialog_file_name=2
filesetpanel_file_set_panel_tree=37flownavigatortreepanel_flow_navigator_tree=76fpgachooser_fpga_table=1gettingstartedview_create_new_project=1
gettingstartedview_open_project=1hjfilechooserhelpers_jump_to_downloads_directory=2hjfilechooserhelpers_refresh_folder_view_to_reflect_external=1hjfilechooserrecentlistpreview_recent_directories=1
logmonitor_monitor=2mainmenumgr_help=2mainmenumgr_reports=4mainmenumgr_tools=6
mainmenumgr_view=9mainmenumgr_window=12maintoolbarmgr_run=3mainwinmenumgr_layout=32
mainwinmenumgr_load=5msgtreepanel_message_view_tree=7numjobschooser_number_of_jobs=2packagetreepanel_package_tree_panel=10
pacommandnames_add_sources=2pacommandnames_auto_connect_target=2pacommandnames_auto_update_hier=4pacommandnames_run_bitgen=20
pacommandnames_src_replace_file=1paviews_code=12paviews_device=2paviews_project_summary=17
programdebugtab_open_target=2programdebugtab_program_device=19programdebugtab_refresh_device=5programfpgadialog_program=30
programfpgadialog_specify_bitstream_file=2progressdialog_background=1projectnamechooser_choose_project_location=1projectnamechooser_project_name=2
projecttab_close_design=1projecttab_reload=4rdicommands_custom_commands=3rdicommands_delete=1
rungadget_show_warning_and_error_messages_in_messages=1searchcommandcomponent_quick_access=2settingsdialog_project_tree=1settingsprojectgeneralpage_choose_device_for_your_project=1
signaltreepanel_signal_tree_table=12srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1srcchooserpanel_create_file=1srcchoosertable_src_chooser_table=2
srcmenu_ip_hierarchy=3syntheticagettingstartedview_recent_projects=1syntheticastatemonitor_cancel=1touchpointsurveydialog_no=1
touchpointsurveydialog_remind_me_later=1
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
java_command_handlers
addsources=2autoconnecttarget=2editdelete=1exitapp=2
fliptoviewtaskimplementation=1fliptoviewtasksynthesis=1launchprogramfpga=32newproject=1
openhardwaremanager=15openproject=1openrecenttarget=2programdevice=15
refreshdevice=5runbitgen=32runimplementation=5runschematic=2
runsynthesis=9savedesign=1showview=30timingconstraintswizard=1
toolssettings=5updatesourcefiles=1viewlayoutcmd=5viewtaskimplementation=7
viewtaskprogramanddebug=1viewtaskprojectmanager=8viewtasksynthesis=1
+ + + +
other_data
guimode=3
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=1synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDLtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + + + + + + + +
post_unisim_transformation
bufg=1carry4=22dsp48e1=1fdce=64
gnd=2ibuf=18ldpe=1lut1=3
lut2=51lut3=16lut4=32lut5=4
lut6=15obuf=16vcc=2
+
+ + + + + + + + + + + + + + + + + +
pre_unisim_transformation
bufg=1carry4=22dsp48e1=1fdce=64
gnd=2ibuf=18ldpe=1lut1=3
lut2=51lut3=16lut4=32lut5=4
lut6=15obuf=16vcc=2
+

+ + + +
phys_opt_design_post_place
+ + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-aggressive_hold_fix=default::[not_specified]-bram_register_opt=default::[not_specified]-clock_opt=default::[not_specified]-critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified]-directive=default::[not_specified]-dsp_register_opt=default::[not_specified]-effort_level=default::[not_specified]
-fanout_opt=default::[not_specified]-hold_fix=default::[not_specified]-insert_negative_edge_ffs=default::[not_specified]-multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified]-restruct_opt=default::[not_specified]-retime=default::[not_specified]-rewire=default::[not_specified]
-shift_register_opt=default::[not_specified]-uram_register_opt=default::[not_specified]-verbose=default::[not_specified]-vhfn=default::[not_specified]
+

+ + + + +
report_drc
+ + + + + + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified]-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]
-ruledecks=default::[not_specified]-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + + + + + +
results
cfgbvs-1=1dpip-1=1dpop-1=1dpop-2=1
pdrc-153=1
+

+ + + + +
report_methodology
+ + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified]-waived=default::[not_specified]
+
+ + + + +
results
timing-18=33timing-20=1
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-hierarchical_depth=default::4-l=default::[not_specified]-name=default::[not_specified]
-no_propagation=default::[not_specified]-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]
-vid=default::[not_specified]-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")clocks=0.000880confidence_level_clock_activity=High
confidence_level_design_state=Highconfidence_level_device_models=Highconfidence_level_internal_activity=Mediumconfidence_level_io_activity=Low
confidence_level_overall=Lowcustomer=TBDcustomer_class=TBDdevstatic=0.071708
die=xc7a35tcpg236-1dsp=0.000751dsp_output_toggle=12.500000dynamic=0.003182
effective_thetaja=5.00enable_probability=0.990000family=artix7ff_toggle=12.500000
flow_state=routedheatsink=medium (Medium Profile)i/o=0.000582input_toggle=12.500000
junction_temp=25.4 (C)logic=0.000562mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000netlist_net_matched=NAoff-chip_power=0.000000
on-chip_power=0.074889output_enable=1.000000output_load=5.000000output_toggle=12.500000
package=cpg236pct_clock_constrained=0.000000pct_inputs_defined=5platform=nt64
process=typicalram_enable=50.000000ram_write=50.000000read_saif=False
set/reset_probability=0.000000signal_rate=Falsesignals=0.000407simulation_file=None
speedgrade=-1static_prob=Falsetemp_grade=commercialthetajb=7.5 (C/W)
thetasa=4.6 (C/W)toggle_rate=Falseuser_board_temp=25.0 (C)user_effective_thetaja=5.00
user_junc_temp=25.4 (C)user_thetajb=7.5 (C/W)user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000vccadc_total_current=0.020000vccadc_voltage=1.800000vccaux_dynamic_current=0.000017
vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000
vccaux_static_current=0.012615vccaux_total_current=0.012632vccaux_voltage=1.800000vccbram_dynamic_current=0.000000
vccbram_static_current=0.000161vccbram_total_current=0.000161vccbram_voltage=1.000000vccint_dynamic_current=0.002727
vccint_static_current=0.009539vccint_total_current=0.012266vccint_voltage=1.000000vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000vcco12_total_current=0.000000vcco12_voltage=1.200000vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000vcco135_total_current=0.000000vcco135_voltage=1.350000vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000vcco15_total_current=0.000000vcco15_voltage=1.500000vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000vcco18_total_current=0.000000vcco18_voltage=1.800000vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000vcco25_total_current=0.000000vcco25_voltage=2.500000vcco33_dynamic_current=0.000129
vcco33_static_current=0.001000vcco33_total_current=0.001129vcco33_voltage=3.300000version=2020.2
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=72bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=20bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=10bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=20bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=5mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=5plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + + +
dsp
dsp48e1_only_used=1dsps_available=90dsps_fixed=0dsps_used=1
dsps_util_percentage=1.11
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=50block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=100ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=50ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1carry4_functional_category=CarryLogiccarry4_used=22
dsp48e1_functional_category=Block Arithmeticdsp48e1_used=1fdce_functional_category=Flop & Latchfdce_used=64
ibuf_functional_category=IOibuf_used=18ldpe_functional_category=Flop & Latchldpe_used=1
lut1_functional_category=LUTlut1_used=3lut2_functional_category=LUTlut2_used=51
lut3_functional_category=LUTlut3_used=16lut4_functional_category=LUTlut4_used=32
lut5_functional_category=LUTlut5_used=4lut6_functional_category=LUTlut6_used=15
obuf_functional_category=IOobuf_used=16
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=16300f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=8150f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=93lut_as_logic_util_percentage=0.45
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600register_as_flip_flop_fixed=0register_as_flip_flop_used=64register_as_flip_flop_util_percentage=0.15
register_as_latch_available=41600register_as_latch_fixed=0register_as_latch_used=1register_as_latch_util_percentage=<0.01
slice_luts_available=20800slice_luts_fixed=0slice_luts_used=93slice_luts_util_percentage=0.45
slice_registers_available=41600slice_registers_fixed=0slice_registers_used=65slice_registers_util_percentage=0.16
lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0lut_as_logic_available=20800lut_as_logic_fixed=0
lut_as_logic_used=93lut_as_logic_util_percentage=0.45lut_as_memory_available=9600lut_as_memory_fixed=0
lut_as_memory_used=0lut_as_memory_util_percentage=0.00lut_as_shift_register_fixed=0lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0lut_in_front_of_the_register_is_unused_used=0lut_in_front_of_the_register_is_used_fixed=0lut_in_front_of_the_register_is_used_used=2
register_driven_from_outside_the_slice_fixed=2register_driven_from_outside_the_slice_used=2register_driven_from_within_the_slice_fixed=2register_driven_from_within_the_slice_used=63
slice_available=8150slice_fixed=0slice_registers_available=41600slice_registers_fixed=0
slice_registers_used=65slice_registers_util_percentage=0.16slice_used=31slice_util_percentage=0.38
slicel_fixed=0slicel_used=12slicem_fixed=0slicem_used=19
unique_control_sets_available=8150unique_control_sets_fixed=8150unique_control_sets_used=3unique_control_sets_util_percentage=0.04
using_o5_and_o6_fixed=0.04using_o5_and_o6_used=28using_o5_output_only_fixed=28using_o5_output_only_used=0
using_o6_output_only_fixed=0using_o6_output_only_used=65
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-debug_log=default::[not_specified]-directive=default::default-fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]
-include_dirs=default::[not_specified]-keep_equivalent_registers=default::[not_specified]-lint=default::[not_specified]-max_bram=default::-1
-max_bram_cascade_height=default::-1-max_dsp=default::-1-max_uram=default::-1-max_uram_cascade_height=default::-1
-mode=default::default-name=default::[not_specified]-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]
-no_timing_driven=default::[not_specified]-os=default::[not_specified]-part=xc7a35tcpg236-1-resource_sharing=default::auto
-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]-rtl_skip_ip=default::[not_specified]
-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3-top=KittCar
-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:21shls_ip=0memory_gain=18.500MBmemory_peak=1018.504MB
+

+ + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/.Vivado_Synthesis.queue.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/.vivado.begin.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..a6d44a1 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/.vivado.end.rst b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/ISEWrap.js b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..97a2ecb --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/ISEWrap.sh b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..f679f2e --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/KittCar.vds b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/KittCar.vds new file mode 100644 index 0000000..dfdc72b --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/KittCar.vds @@ -0,0 +1,243 @@ +#----------------------------------------------------------- +# Vivado v2020.2 (64-bit) +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 +# Start of session at: Mon Mar 17 20:33:46 2025 +# Process ID: 9996 +# Current directory: C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1 +# Command line: vivado.exe -log KittCar.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source KittCar.tcl +# Log file: C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/KittCar.vds +# Journal file: C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source KittCar.tcl -notrace +Command: synth_design -top KittCar -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 3432 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'KittCar' [C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd:32] + Parameter CLK_PERIOD_NS bound to: 10 - type: integer + Parameter MIN_KITT_CAR_STEP_MS bound to: 1 - type: integer + Parameter NUM_OF_SWS bound to: 16 - type: integer + Parameter NUM_OF_LEDS bound to: 16 - type: integer +WARNING: [Synth 8-614] signal 'leds_sr' is read in the process but is not in the sensitivity list [C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd:38] +INFO: [Synth 8-256] done synthesizing module 'KittCar' (1#1) [C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd:32] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1000.004 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/DESD/basys3_master.xdc] +Finished Parsing XDC File [C:/DESD/basys3_master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/DESD/basys3_master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/KittCar_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/KittCar_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1000.004 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-327] inferring latch for variable 'up_reg' [C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd:43] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 17 Bit Adders := 1 ++---Registers : + 16 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 2 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +DSP Report: Generating DSP counter2, operation Mode is: (A:0xf4240)*B. +DSP Report: operator counter2 is absorbed into DSP counter2. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +DSP: Preliminary Mapping Report (see note below) ++------------+---------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++------------+---------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|KittCar | (A:0xf4240)*B | 21 | 18 | - | - | 39 | 0 | 0 | - | - | - | 0 | 0 | ++------------+---------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1000.004 ; gain = 0.000 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1010.969 ; gain = 10.965 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1011.715 ; gain = 11.711 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1018.504 ; gain = 18.500 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1018.504 ; gain = 18.500 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1018.504 ; gain = 18.500 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1018.504 ; gain = 18.500 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1018.504 ; gain = 18.500 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1018.504 ; gain = 18.500 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+--------+------+ +| |Cell |Count | ++------+--------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 22| +|3 |DSP48E1 | 1| +|4 |LUT1 | 3| +|5 |LUT2 | 51| +|6 |LUT3 | 16| +|7 |LUT4 | 32| +|8 |LUT5 | 4| +|9 |LUT6 | 15| +|10 |FDCE | 64| +|11 |LDP | 1| +|12 |IBUF | 18| +|13 |OBUF | 16| ++------+--------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1018.504 ; gain = 18.500 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1018.504 ; gain = 18.500 +Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1018.504 ; gain = 18.500 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1028.793 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 24 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1028.793 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + LDP => LDPE: 1 instance + +INFO: [Common 17-83] Releasing license: Synthesis +17 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1028.793 ; gain = 28.789 +INFO: [Common 17-1381] The checkpoint 'C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/KittCar.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file KittCar_utilization_synth.rpt -pb KittCar_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon Mar 17 20:34:10 2025... diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/KittCar_utilization_synth.rpt b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/KittCar_utilization_synth.rpt new file mode 100644 index 0000000..f0ab7b4 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/KittCar_utilization_synth.rpt @@ -0,0 +1,184 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +| Date : Mon Mar 17 20:34:10 2025 +| Host : Davide-Samsung running 64-bit major release (build 9200) +| Command : report_utilization -file KittCar_utilization_synth.rpt -pb KittCar_utilization_synth.pb +| Design : KittCar +| Device : 7a35tcpg236-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 93 | 0 | 20800 | 0.45 | +| LUT as Logic | 93 | 0 | 20800 | 0.45 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 65 | 0 | 41600 | 0.16 | +| Register as Flip Flop | 64 | 0 | 41600 | 0.15 | +| Register as Latch | 1 | 0 | 41600 | <0.01 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 1 | Yes | - | Set | +| 64 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| DSPs | 1 | 0 | 90 | 1.11 | +| DSP48E1 only | 1 | | | | ++----------------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 34 | 0 | 106 | 32.08 | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 64 | Flop & Latch | +| LUT2 | 51 | LUT | +| LUT4 | 32 | LUT | +| CARRY4 | 22 | CarryLogic | +| IBUF | 18 | IO | +| OBUF | 16 | IO | +| LUT3 | 16 | LUT | +| LUT6 | 15 | LUT | +| LUT5 | 4 | LUT | +| LUT1 | 3 | LUT | +| LDPE | 1 | Flop & Latch | +| DSP48E1 | 1 | Block Arithmetic | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/__synthesis_is_complete__ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/htr.txt b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/htr.txt new file mode 100644 index 0000000..f5086e3 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log KittCar.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source KittCar.tcl diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/rundef.js b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/rundef.js new file mode 100644 index 0000000..56a21b4 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2020.2/bin;"; +} else { + PathVal = "C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2020.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log KittCar.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source KittCar.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/runme.bat b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/runme.bat new file mode 100644 index 0000000..44f0077 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/runme.sh b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/runme.sh new file mode 100644 index 0000000..9d6a1d0 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2020.2/bin +else + PATH=C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2020.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log KittCar.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source KittCar.tcl diff --git a/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd b/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd new file mode 100644 index 0000000..6382814 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd @@ -0,0 +1,80 @@ +---------- DEFAULT LIBRARY --------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +------------------------------------ + +ENTITY KittCar IS + GENERIC ( + + CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds + MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t) + + NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches + NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16 -- Number of output LEDs + + ); + PORT ( + + ------- Reset/Clock -------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + ---------------------------- + + -------- LEDs/SWs ---------- + sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3 + led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3 + ---------------------------- + + ); +END KittCar; + +ARCHITECTURE Behavioral OF KittCar IS + SIGNAL leds_sr : STD_LOGIC_VECTOR(led'RANGE) := (OTHERS => '0'); + SIGNAL counter : UNSIGNED(47 DOWNTO 0) := (OTHERS => '0'); + SIGNAL n_period : POSITIVE RANGE 1 TO 2 ** NUM_OF_SWS := 1; +BEGIN + + PROCESS (clk, reset) + VARIABLE up : STD_LOGIC := '1'; + BEGIN + -- up/down logic + IF leds_sr(NUM_OF_LEDS - 1) = '1' THEN + up := '0'; + ELSIF leds_sr(0) = '1' THEN + up := '1'; + END IF; + + -- Reset the leds + IF unsigned(leds_sr) = 0 THEN + leds_sr <= (0 => '1', OTHERS => '0'); + END IF; + + IF reset = '1' THEN + leds_sr <= (OTHERS => '0'); + up := '1'; + counter <= (OTHERS => '0'); + ELSIF rising_edge(clk) THEN + -- Calculate the number of periods + IF counter >= ((MIN_KITT_CAR_STEP_MS * 1000000) * n_period) THEN + counter <= (OTHERS => '0'); + -- Shift the leds + IF up = '1' THEN + leds_sr <= leds_sr(NUM_OF_LEDS - 2 DOWNTO 0) & '0'; + ELSIF up = '0' THEN + leds_sr <= '0' & leds_sr(NUM_OF_LEDS - 1 DOWNTO 1); + END IF; + ELSE + counter <= counter + to_unsigned(CLK_PERIOD_NS, counter'LENGTH); + END IF; + END IF; + END PROCESS; + + PROCESS (sw) + BEGIN + n_period <= to_integer(unsigned(sw)) + 1; + END PROCESS; + + led <= leds_sr; + +END Behavioral; \ No newline at end of file