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Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.

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Davide Cavagnola
2025-05-16 16:43:45 +02:00
parent c3967c3124
commit 55c5c84247
9 changed files with 356 additions and 621 deletions
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LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
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@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Thu May 15 16:34:14 2025
--Date : Fri May 16 16:28:03 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper