diff --git a/LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd b/LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd index c171dd7..1340572 100644 --- a/LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd +++ b/LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd @@ -1,8 +1,8 @@ --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 ---Date : Tue Apr 22 22:40:46 2025 ---Host : Davide-Samsung running 64-bit major release (build 9200) +--Date : Thu Apr 24 15:46:08 2025 +--Host : DavideASUS running 64-bit major release (build 9200) --Command : generate_target pak_depak_wrapper.bd --Design : pak_depak_wrapper --Purpose : IP block netlist diff --git a/LAB2/design/pak_depak/pak_depak.bd b/LAB2/design/pak_depak/pak_depak.bd index 5cb0470..a4a65af 100644 --- a/LAB2/design/pak_depak/pak_depak.bd +++ b/LAB2/design/pak_depak/pak_depak.bd @@ -5,7 +5,7 @@ "device": "xc7a35tcpg236-1", "name": "pak_depak", "rev_ctrl_bd_flag": "RevCtrlBdOff", - "synth_flow_mode": "None", + "synth_flow_mode": "Hierarchical", "tool_version": "2020.2", "validated": "true" }, @@ -13,8 +13,8 @@ "proc_sys_reset_0": "", "clk_wiz_0": "", "AXI4Stream_UART_0": "", - "packetizer_0": "", - "depacketizer_0": "" + "depacketizer_0": "", + "packetizer_0": "" }, "interface_ports": { "usb_uart": { @@ -78,8 +78,8 @@ }, "clk_wiz_0": { "vlnv": "xilinx.com:ip:clk_wiz:6.0", - "xci_name": "pak_depak_clk_wiz_0_1", - "xci_path": "ip\\pak_depak_clk_wiz_0_1\\pak_depak_clk_wiz_0_1.xci", + "xci_name": "pak_depak_clk_wiz_0_0", + "xci_path": "ip\\pak_depak_clk_wiz_0_0\\pak_depak_clk_wiz_0_0.xci", "inst_hier_path": "clk_wiz_0", "parameters": { "CLK_IN1_BOARD_INTERFACE": { @@ -107,193 +107,6 @@ } } }, - "packetizer_0": { - "vlnv": "xilinx.com:module_ref:packetizer:1.0", - "xci_name": "pak_depak_packetizer_0_0", - "xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci", - "inst_hier_path": "packetizer_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "packetizer", - "boundary_crc": "0x0" - }, - "interface_ports": { - "m_axis": { - "mode": "Master", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "0", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "m_axis_tdata", - "direction": "O", - "left": "7", - "right": "0" - }, - "TVALID": { - "physical_name": "m_axis_tvalid", - "direction": "O" - }, - "TREADY": { - "physical_name": "m_axis_tready", - "direction": "I" - } - } - }, - "s_axis": { - "mode": "Slave", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "s_axis_tdata", - "direction": "I", - "left": "7", - "right": "0" - }, - "TLAST": { - "physical_name": "s_axis_tlast", - "direction": "I" - }, - "TVALID": { - "physical_name": "s_axis_tvalid", - "direction": "I" - }, - "TREADY": { - "physical_name": "s_axis_tready", - "direction": "O" - } - } - } - }, - "ports": { - "clk": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "m_axis:s_axis", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "aresetn", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - } - }, - "aresetn": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - } - } - }, "depacketizer_0": { "vlnv": "xilinx.com:module_ref:depacketizer:1.0", "xci_name": "pak_depak_depacketizer_0_0", @@ -480,13 +293,200 @@ } } } + }, + "packetizer_0": { + "vlnv": "xilinx.com:module_ref:packetizer:1.0", + "xci_name": "pak_depak_packetizer_0_0", + "xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci", + "inst_hier_path": "packetizer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "packetizer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } } }, "interface_nets": { - "AXI4Stream_UART_0_UART": { + "AXI4Stream_UART_0_M00_AXIS_RX": { "interface_ports": [ - "usb_uart", - "AXI4Stream_UART_0/UART" + "AXI4Stream_UART_0/M00_AXIS_RX", + "depacketizer_0/s_axis" ] }, "depacketizer_0_m_axis": { @@ -495,17 +495,17 @@ "packetizer_0/s_axis" ] }, - "AXI4Stream_UART_0_M00_AXIS_RX": { - "interface_ports": [ - "AXI4Stream_UART_0/M00_AXIS_RX", - "depacketizer_0/s_axis" - ] - }, "packetizer_0_m_axis": { "interface_ports": [ "packetizer_0/m_axis", "AXI4Stream_UART_0/S00_AXIS_TX" ] + }, + "AXI4Stream_UART_0_UART": { + "interface_ports": [ + "usb_uart", + "AXI4Stream_UART_0/UART" + ] } }, "nets": { @@ -529,8 +529,8 @@ "proc_sys_reset_0/slowest_sync_clk", "AXI4Stream_UART_0/m00_axis_rx_aclk", "AXI4Stream_UART_0/s00_axis_tx_aclk", - "packetizer_0/clk", - "depacketizer_0/clk" + "depacketizer_0/clk", + "packetizer_0/clk" ] }, "proc_sys_reset_0_peripheral_reset": { @@ -550,8 +550,8 @@ "proc_sys_reset_0/peripheral_aresetn", "AXI4Stream_UART_0/m00_axis_rx_aresetn", "AXI4Stream_UART_0/s00_axis_tx_aresetn", - "packetizer_0/aresetn", - "depacketizer_0/aresetn" + "depacketizer_0/aresetn", + "packetizer_0/aresetn" ] } } diff --git a/LAB2/design/pak_depak/pak_depak.bda b/LAB2/design/pak_depak/pak_depak.bda index a4f338d..09153b4 100644 --- a/LAB2/design/pak_depak/pak_depak.bda +++ b/LAB2/design/pak_depak/pak_depak.bda @@ -21,22 +21,22 @@ - pak_depak - BC - - 2 pak_depak VR - + active 2 PM - + + pak_depak + BC + + - + diff --git a/LAB2/sim/tb_packetizer.vhd b/LAB2/sim/tb_packetizer.vhd index 980c7f5..87fa788 100644 --- a/LAB2/sim/tb_packetizer.vhd +++ b/LAB2/sim/tb_packetizer.vhd @@ -64,7 +64,7 @@ ARCHITECTURE Behavioral OF tb_packetizer IS 0 => x"10", 1 => x"20", 2 => x"30", - 3 => x"4", + 3 => x"04", 4 => x"54", 5 => x"65", 6 => x"73", @@ -150,12 +150,12 @@ BEGIN END LOOP; s_axis_tlast <= '0'; - -- Wait a bit, then send another packet of 2 words + -- Wait a bit, then send another packet of 1 words WAIT FOR 50 ns; - FOR i IN 4 TO 5 LOOP + FOR i IN 4 TO 4 LOOP s_axis_tdata <= mem(i); s_axis_tvalid <= '1'; - IF i = 5 THEN + IF i = 4 THEN s_axis_tlast <= '1'; ELSE s_axis_tlast <= '0'; diff --git a/LAB2/src/packetizer.vhd b/LAB2/src/packetizer.vhd index 856f9b6..b87261d 100644 --- a/LAB2/src/packetizer.vhd +++ b/LAB2/src/packetizer.vhd @@ -82,8 +82,14 @@ BEGIN m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)); -- Prepare header m_axis_tvalid_int <= '1'; --Send header + IF s_axis_tlast = '1' THEN + s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss + state <= SENDING_FOOTER; + ELSE + state <= STREAMING; + END IF; + trigger <= '1'; - state <= STREAMING; END IF; WHEN STREAMING => @@ -99,7 +105,7 @@ BEGIN WHEN SENDING_FOOTER => IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss - + data_buffer <= STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)); -- Send footer m_axis_tvalid_int <= '1'; diff --git a/LAB2/test/LAB2-Test_new.exe b/LAB2/test/test.exe similarity index 70% rename from LAB2/test/LAB2-Test_new.exe rename to LAB2/test/test.exe index 2a27756..6a63719 100644 Binary files a/LAB2/test/LAB2-Test_new.exe and b/LAB2/test/test.exe differ diff --git a/LAB2/test/test.py b/LAB2/test/test.py index c3e4b7c..9449bd1 100644 --- a/LAB2/test/test.py +++ b/LAB2/test/test.py @@ -1,4 +1,4 @@ -""" import sys +import sys import subprocess def install_and_import(package, package_name=None): @@ -16,7 +16,7 @@ install_and_import("serial", "pyserial") install_and_import("PIL", "pillow") install_and_import("tqdm") install_and_import("numpy") -install_and_import("scipy") """ +install_and_import("scipy") from serial import Serial import serial.tools.list_ports @@ -30,6 +30,7 @@ IMAGE_UF = r'C:\DESD\LAB2\test\test_uf.png' IMAGE_NAME3 = r'C:\DESD\LAB2\test\test3.png' IMAGE_NAME2 = r'C:\DESD\LAB2\test\test2.png' IMAGE_NAME1 = r'C:\DESD\LAB2\test\test1.png' +IMAGE_DEPACK_PACK = r'C:\DESD\LAB2\test\test_depack_pack.png' BASYS3_PID = 0x6010 BASYS3_VID = 0x0403 @@ -45,17 +46,22 @@ for port in serial.tools.list_ports.comports(): if not dev: raise RuntimeError("Basys 3 Not Found!") -test_n = int(input("Insert test number (1, 2, 3, overflow (4) or underflow (5)): ").strip()) +test_n = int(input("Insert test number (1, 2, 3, 4 (overflow), 5 (underflow) or 6 (depack > pack only)): ").strip()) -if test_n not in [1, 2, 3, 4, 5]: - raise RuntimeError("Test number must be 1, 2, 3, 4 (overflow) or 5 (underflow)") +if test_n not in [1, 2, 3, 4, 5, 6]: + raise RuntimeError("Test number must be 1, 2, 3, 4 (overflow), 5 (underflow) or 6 (depack > pack only)") dev = Serial(dev, 115200) -img = Image.open(IMAGE_NAME1 if test_n == 1 else IMAGE_NAME2 if test_n == 2 else IMAGE_NAME3 if test_n == 3 else IMAGE_UF if test_n == 5 else IMAGE_OF) +img = Image.open(IMAGE_NAME1 if test_n == 1 else IMAGE_NAME2 if test_n == 2 else IMAGE_NAME3 if test_n == 3 else IMAGE_OF if test_n == 4 else IMAGE_UF if test_n == 5 else IMAGE_DEPACK_PACK) if img.mode != "RGB": img = img.convert("RGB") +if test_n == 4: + print("Check for overflow (LED U16)") +elif test_n == 5: + print("Check for underflow (LED U19)") + IMG_WIDTH, IMG_HEIGHT = img.size # Get dimensions from the image mat = np.asarray(img, dtype=np.uint8) @@ -64,39 +70,59 @@ mat = mat[:, :, :3] if mat.max() > 127: mat = mat // 2 -buff = mat.tobytes() +res = b'' -mat_gray = np.sum(mat, axis=2) // 3 +if test_n == 6: + print("Check for depack > pack") -sim_img = convolve2d(mat_gray, [[-1, -1, -1], [-1, 8, -1], [-1, -1, -1]], mode="same") + total_bytes = IMG_HEIGHT * IMG_WIDTH * 3 + for idx in tqdm(range(total_bytes)): + i = idx // (IMG_WIDTH * 3) + j = (idx // 3) % IMG_WIDTH + k = idx % 3 -sim_img[sim_img < 0] = 0 -sim_img[sim_img > 127] = 127 -sim_img = sim_img.astype(np.uint8) + dev.write(b'\xff') + dev.write(bytes([mat[i, j, k]])) + dev.write(b'\xf1') + dev.flush() -dev.write(b'\xff') -for i in tqdm(range(IMG_HEIGHT)): - dev.write(buff[i * IMG_WIDTH * 3:(i + 1) * IMG_WIDTH * 3]) + # Read 3 bytes: header, data, footer + resp = dev.read(3) + res += resp[1:2] # Only keep the data byte -dev.write(b'\xf1') -dev.flush() + res_img = np.frombuffer(res, dtype=np.uint8) + res_img = res_img.reshape((IMG_HEIGHT, IMG_WIDTH, 3)) -if test_n == 4: - print("Check for overflow (LED U16)") - exit() -elif test_n == 5: - print("Check for underflow (LED U19)") - exit() +else: + buff = mat.tobytes() -res = dev.read(IMG_HEIGHT * IMG_WIDTH + 2) + mat_gray = np.sum(mat, axis=2) // 3 -res_img = np.frombuffer(res[1:-1], dtype=np.uint8) -res_img = res_img.reshape((IMG_HEIGHT, IMG_WIDTH)) + sim_img = convolve2d(mat_gray, [[-1, -1, -1], [-1, 8, -1], [-1, -1, -1]], mode="same") + + sim_img[sim_img < 0] = 0 + sim_img[sim_img > 127] = 127 + sim_img = sim_img.astype(np.uint8) + + dev.write(b'\xff') + for i in tqdm(range(IMG_HEIGHT)): + dev.write(buff[i * IMG_WIDTH * 3:(i + 1) * IMG_WIDTH * 3]) + + dev.write(b'\xf1') + dev.flush() + + if test_n == 4 or test_n == 5: + exit() + else: + res = dev.read(IMG_HEIGHT * IMG_WIDTH + 2) + + res_img = np.frombuffer(res[1:-1], dtype=np.uint8) + res_img = res_img.reshape((IMG_HEIGHT, IMG_WIDTH)) + +if (test_n == 6 and (res_img == mat).all()) or (res_img == sim_img).all(): + print("Image Match!") +else: + print("Image Mismatch!") im = Image.fromarray(res_img) im.show() - -if np.all(res_img != sim_img): - print("Image Mismatch!") - -dev.close() diff --git a/LAB2/test/test_depack_pack.png b/LAB2/test/test_depack_pack.png new file mode 100644 index 0000000..bb8edfc Binary files /dev/null and b/LAB2/test/test_depack_pack.png differ diff --git a/LAB2/vivado/packetizer_test/packetizer_test.xpr b/LAB2/vivado/packetizer_test/packetizer_test.xpr index 092d185..7cc40b2 100644 --- a/LAB2/vivado/packetizer_test/packetizer_test.xpr +++ b/LAB2/vivado/packetizer_test/packetizer_test.xpr @@ -47,7 +47,7 @@