From 5f30651763da546f802c34a14b2f75bc3a611195 Mon Sep 17 00:00:00 2001 From: Davide Date: Mon, 19 May 2025 00:43:25 +0200 Subject: [PATCH] Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust node connections in diligent_jstk.bda, and modify delay parameter in digilent_jstk2.vhd for improved functionality and performance. --- LAB3/design/diligent_jstk/diligent_jstk.bd | 36 ++++----- LAB3/design/diligent_jstk/diligent_jstk.bda | 14 ++-- .../hdl/diligent_jstk_wrapper.vhd | 2 +- LAB3/src/LFO.vhd | 2 +- LAB3/src/digilent_jstk2.vhd | 2 +- LAB3/src/effect_selector.vhd | 22 +----- LAB3/vivado/diligent_jstk/diligent_jstk.xpr | 74 +++++++------------ 7 files changed, 54 insertions(+), 98 deletions(-) diff --git a/LAB3/design/diligent_jstk/diligent_jstk.bd b/LAB3/design/diligent_jstk/diligent_jstk.bd index d267b4c..dbd3add 100644 --- a/LAB3/design/diligent_jstk/diligent_jstk.bd +++ b/LAB3/design/diligent_jstk/diligent_jstk.bd @@ -591,30 +591,12 @@ } }, "interface_nets": { - "axi4stream_spi_master_0_SPI_M": { - "interface_ports": [ - "SPI_M_0", - "axi4stream_spi_master_0/SPI_M" - ] - }, - "AXI4Stream_UART_0_M00_AXIS_RX": { - "interface_ports": [ - "AXI4Stream_UART_0/M00_AXIS_RX", - "jstk_uart_bridge_0/s_axis" - ] - }, "AXI4Stream_UART_0_UART": { "interface_ports": [ "usb_uart", "AXI4Stream_UART_0/UART" ] }, - "jstk_uart_bridge_0_m_axis": { - "interface_ports": [ - "AXI4Stream_UART_0/S00_AXIS_TX", - "jstk_uart_bridge_0/m_axis" - ] - }, "axi4stream_spi_master_0_M_AXIS": { "interface_ports": [ "axi4stream_spi_master_0/M_AXIS", @@ -622,12 +604,30 @@ "system_ila_0/SLOT_1_AXIS" ] }, + "AXI4Stream_UART_0_M00_AXIS_RX": { + "interface_ports": [ + "AXI4Stream_UART_0/M00_AXIS_RX", + "jstk_uart_bridge_0/s_axis" + ] + }, + "jstk_uart_bridge_0_m_axis": { + "interface_ports": [ + "AXI4Stream_UART_0/S00_AXIS_TX", + "jstk_uart_bridge_0/m_axis" + ] + }, "digilent_jstk2_0_m_axis": { "interface_ports": [ "digilent_jstk2_0/m_axis", "axi4stream_spi_master_0/S_AXIS", "system_ila_0/SLOT_0_AXIS" ] + }, + "axi4stream_spi_master_0_SPI_M": { + "interface_ports": [ + "SPI_M_0", + "axi4stream_spi_master_0/SPI_M" + ] } }, "nets": { diff --git a/LAB3/design/diligent_jstk/diligent_jstk.bda b/LAB3/design/diligent_jstk/diligent_jstk.bda index 50ac58c..1612b92 100644 --- a/LAB3/design/diligent_jstk/diligent_jstk.bda +++ b/LAB3/design/diligent_jstk/diligent_jstk.bda @@ -25,18 +25,18 @@ BC - 2 - diligent_jstk - VR - - active 2 PM - + + 2 + diligent_jstk + VR + + - + diff --git a/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd b/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd index 7ff2210..460a63b 100644 --- a/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd +++ b/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd @@ -1,7 +1,7 @@ --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 ---Date : Sat May 17 14:20:44 2025 +--Date : Sun May 18 23:39:32 2025 --Host : DavideASUS running 64-bit major release (build 9200) --Command : generate_target diligent_jstk_wrapper.bd --Design : diligent_jstk_wrapper diff --git a/LAB3/src/LFO.vhd b/LAB3/src/LFO.vhd index 48d8fe8..dc0d4be 100644 --- a/LAB3/src/LFO.vhd +++ b/LAB3/src/LFO.vhd @@ -149,7 +149,7 @@ BEGIN signed(s_axis_tdata) * tri_counter ); ELSE - lfo_product <= s_axis_tdata; + lfo_product <= s_axis_tdata & (TRIANGULAR_COUNTER_LENGHT - 1 downto 0 => '0'); END IF; trigger <= '1'; diff --git a/LAB3/src/digilent_jstk2.vhd b/LAB3/src/digilent_jstk2.vhd index 1131ce3..1206cd3 100644 --- a/LAB3/src/digilent_jstk2.vhd +++ b/LAB3/src/digilent_jstk2.vhd @@ -3,7 +3,7 @@ USE IEEE.STD_LOGIC_1164.ALL; ENTITY digilent_jstk2 IS GENERIC ( - DELAY_US : INTEGER := 100; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work + DELAY_US : INTEGER := 300; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz) SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz) ); diff --git a/LAB3/src/effect_selector.vhd b/LAB3/src/effect_selector.vhd index f8b1184..4efe6d7 100644 --- a/LAB3/src/effect_selector.vhd +++ b/LAB3/src/effect_selector.vhd @@ -1,24 +1,3 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 04/29/2024 10:12:03 AM --- Design Name: --- Module Name: effect_selector - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -38,6 +17,7 @@ entity effect_selector is Port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; + effect : in STD_LOGIC; jstck_x : in STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0); jstck_y : in STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0); diff --git a/LAB3/vivado/diligent_jstk/diligent_jstk.xpr b/LAB3/vivado/diligent_jstk/diligent_jstk.xpr index e8c8d8d..66fb777 100644 --- a/LAB3/vivado/diligent_jstk/diligent_jstk.xpr +++ b/LAB3/vivado/diligent_jstk/diligent_jstk.xpr @@ -95,17 +95,8 @@ - - - - - - - - - - - + + @@ -113,8 +104,17 @@ - - + + + + + + + + + + + @@ -238,9 +238,7 @@ - - Vivado Synthesis Defaults - + @@ -250,9 +248,7 @@ - - Vivado Synthesis Defaults - + @@ -262,9 +258,7 @@ - - Vivado Synthesis Defaults - + @@ -274,9 +268,7 @@ - - Vivado Synthesis Defaults - + @@ -286,9 +278,7 @@ - - Vivado Synthesis Defaults - + @@ -298,9 +288,7 @@ - - Vivado Synthesis Defaults - + @@ -340,9 +328,7 @@ - - Default settings for Implementation. - + @@ -359,9 +345,7 @@ - - Default settings for Implementation. - + @@ -378,9 +362,7 @@ - - Default settings for Implementation. - + @@ -397,9 +379,7 @@ - - Default settings for Implementation. - + @@ -416,9 +396,7 @@ - - Default settings for Implementation. - + @@ -435,9 +413,7 @@ - - Default settings for Implementation. - +