Add initial design files and project configuration for LAB3

- Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design.
- Added a placeholder README file in the simulation directory.
- Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation.
- Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.

LAB3/cons/io.xdc

@@ -0,0 +1,13 @@
+# SPI connected to JA, top row
+set_property PACKAGE_PIN J1 [get_ports SPI_M_0_ss_io]
+set_property PACKAGE_PIN G2 [get_ports SPI_M_0_sck_io]
+set_property PACKAGE_PIN L2 [get_ports SPI_M_0_io0_io]
+set_property PACKAGE_PIN J2 [get_ports SPI_M_0_io1_io]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io0_io]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io1_io]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_sck_io]
+set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_ss_io]
+set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io0_io]
+set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io1_io]
+set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_sck_io]
+set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_ss_io]