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Add initial design files and project configuration for LAB3

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- Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design.
- Added a placeholder README file in the simulation directory.
- Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation.
- Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.
This commit is contained in:
Davide Cavagnola
2025-05-12 14:20:41 +02:00
parent 079d1ab0d5
commit 60a8aa912d
7 changed files with 2493 additions and 5 deletions
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LAB3/design/lab_3/lab_3.bd Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">lab_3</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">lab_3</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n0">
</edge>
<edge id="e1" source="n0" target="n2">
</edge>
</graph>
</graphml>