diff --git a/LAB2/sim/tb_bram_writer.vhd b/LAB2/sim/tb_bram_writer.vhd
index 1c6ee0e..a013bf3 100644
--- a/LAB2/sim/tb_bram_writer.vhd
+++ b/LAB2/sim/tb_bram_writer.vhd
@@ -127,6 +127,12 @@ BEGIN
wait until write_ok = '1';
wait until rising_edge(clk);
+ -- Require data
+ for i in 0 to IMG_SIZE*IMG_SIZE-1 loop
+ conv_addr <= std_logic_vector(to_unsigned(i, ADDR_WIDTH));
+ wait until rising_edge(clk);
+ end loop;
+
-- Simulate convolution done
done_conv <= '1';
wait until rising_edge(clk);
diff --git a/LAB2/src/bram_writer.vhd b/LAB2/src/bram_writer.vhd
index 00f7cd8..9af41db 100644
--- a/LAB2/src/bram_writer.vhd
+++ b/LAB2/src/bram_writer.vhd
@@ -46,11 +46,13 @@ ARCHITECTURE rtl OF bram_writer IS
);
END COMPONENT;
- TYPE state_type IS (IDLE, RECEIVING, CONVOLUTION);
+ TYPE state_type IS (IDLE, RECEIVING, CHECK_START_CONV, CONVOLUTION);
SIGNAL state : state_type := IDLE;
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
+ SIGNAL bram_data_out : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- BRAM data output
+ SIGNAL bram_data_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- BRAM data input
SIGNAL bram_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); -- BRAM address
SIGNAL bram_we : STD_LOGIC := '0'; -- Write enable signal for BRAM
@@ -67,14 +69,17 @@ BEGIN
clk => clk,
aresetn => aresetn,
addr => bram_addr,
- dout => conv_data,
- din => s_axis_tdata,
+ dout => bram_data_out,
+ din => bram_data_in,
we => bram_we
);
-- Assign AXIS ready signal
s_axis_tready <= s_axis_tready_int;
+ -- Binding BRAM data to output
+ conv_data <= bram_data_out(6 DOWNTO 0);
+
-- Select BRAM address based on state
WITH state SELECT bram_addr <= conv_addr WHEN CONVOLUTION,
wr_addr WHEN OTHERS;
@@ -112,6 +117,7 @@ BEGIN
-- valid data received, start receiving
wr_addr <= (OTHERS => '0');
bram_we <= '1'; -- Enable write to BRAM
+ bram_data_in <= s_axis_tdata; -- Write data to BRAM
state <= RECEIVING;
END IF;
@@ -126,24 +132,28 @@ BEGIN
-- Increment write address and write data to BRAM
wr_addr <= STD_LOGIC_VECTOR(unsigned(wr_addr) + 1);
bram_we <= '1'; -- Enable write to BRAM
+ bram_data_in <= s_axis_tdata; -- Write data to BRAM
-- Check for last data signal
IF s_axis_tlast = '1' THEN
- -- Check for underflow: if not enough data received
- IF unsigned(wr_addr) < (IMG_SIZE ** 2 - 2) THEN
- underflow <= '1';
- state <= IDLE;
- ELSE
- -- Data reception complete, start convolution
- write_ok <= '1';
-
- s_axis_tready_int <= '0';
- start_conv <= '1';
- state <= CONVOLUTION;
- END IF;
+ state <= CHECK_START_CONV;
END IF;
END IF;
END IF;
+
+ WHEN CHECK_START_CONV =>
+ -- Check for underflow: if not enough data received
+ IF unsigned(wr_addr) < (IMG_SIZE ** 2 - 2) THEN
+ underflow <= '1';
+ state <= IDLE;
+ ELSE
+ -- Data reception complete, start convolution
+ write_ok <= '1';
+
+ s_axis_tready_int <= '0';
+ start_conv <= '1';
+ state <= CONVOLUTION;
+ END IF;
WHEN CONVOLUTION =>
-- Wait for convolution to finish
diff --git a/LAB2/vivado/bram_writer_test/bram_writer_test.xpr b/LAB2/vivado/bram_writer_test/bram_writer_test.xpr
new file mode 100644
index 0000000..e613b7c
--- /dev/null
+++ b/LAB2/vivado/bram_writer_test/bram_writer_test.xpr
@@ -0,0 +1,220 @@
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+ Vivado Synthesis Defaults
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+ Default settings for Implementation.
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+ default_dashboard
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diff --git a/LAB2/vivado/bram_writer_test/tb_bram_writer_behav.wcfg b/LAB2/vivado/bram_writer_test/tb_bram_writer_behav.wcfg
new file mode 100644
index 0000000..c9bedd3
--- /dev/null
+++ b/LAB2/vivado/bram_writer_test/tb_bram_writer_behav.wcfg
@@ -0,0 +1,107 @@
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+ aresetn
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+ AXI4
+ label
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+ s_axis_tdata[7:0]
+ s_axis_tdata[7:0]
+
+
+ s_axis_tvalid
+ s_axis_tvalid
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+ s_axis_tready
+ s_axis_tready
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+ s_axis_tlast
+ s_axis_tlast
+
+
+ FSM
+ label
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+ state
+ state
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+ BRAM
+ label
+
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+ bram_addr[3:0]
+ bram_addr[3:0]
+
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+ wr_addr[3:0]
+ wr_addr[3:0]
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+ bram_we
+ bram_we
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+ conv_addr[3:0]
+ conv_addr[3:0]
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+ conv_data[6:0]
+ conv_data[6:0]
+
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+ start_conv
+ start_conv
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+ done_conv
+ done_conv
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+ Out status
+ label
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+ write_ok
+ write_ok
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+ overflow
+ overflow
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+ underflow
+ underflow
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