diff --git a/LAB3/sim/tb_moving_average.vhd b/LAB3/sim/tb_moving_average.vhd
new file mode 100644
index 0000000..d8a0bd2
--- /dev/null
+++ b/LAB3/sim/tb_moving_average.vhd
@@ -0,0 +1,142 @@
+-- filepath: c:\DESD\LAB3\sim\tb_moving_average.vhd
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_moving_average IS
+END tb_moving_average;
+
+ARCHITECTURE sim OF tb_moving_average IS
+
+ CONSTANT TDATA_WIDTH : INTEGER := 24;
+ CONSTANT FILTER_ORDER_PWR : INTEGER := 5;
+
+ SIGNAL aclk : STD_LOGIC := '0';
+ SIGNAL aresetn : STD_LOGIC := '0';
+
+ SIGNAL s_axis_tvalid : STD_LOGIC := '0';
+ SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL s_axis_tlast : STD_LOGIC := '0';
+ SIGNAL s_axis_tready : STD_LOGIC;
+
+ SIGNAL m_axis_tvalid : STD_LOGIC;
+ SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0);
+ SIGNAL m_axis_tlast : STD_LOGIC;
+ SIGNAL m_axis_tready : STD_LOGIC := '1';
+
+ SIGNAL enable_filter : STD_LOGIC := '0';
+
+ -- DUT
+ COMPONENT moving_average_filter_en
+ GENERIC (
+ FILTER_ORDER_POWER : INTEGER := 5;
+ TDATA_WIDTH : POSITIVE := 24
+ );
+ PORT (
+ aclk : IN STD_LOGIC;
+ aresetn : IN STD_LOGIC;
+ s_axis_tvalid : IN STD_LOGIC;
+ s_axis_tdata : IN STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0);
+ s_axis_tlast : IN STD_LOGIC;
+ s_axis_tready : OUT STD_LOGIC;
+ m_axis_tvalid : OUT STD_LOGIC;
+ m_axis_tdata : OUT STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0);
+ m_axis_tlast : OUT STD_LOGIC;
+ m_axis_tready : IN STD_LOGIC;
+ enable_filter : IN STD_LOGIC
+ );
+ END COMPONENT;
+
+BEGIN
+
+ -- Clock generation
+ clk_proc : PROCESS
+ BEGIN
+ aclk <= '0';
+ WAIT FOR 5 ns;
+ aclk <= '1';
+ WAIT FOR 5 ns;
+ END PROCESS;
+
+ -- DUT instantiation
+ dut: moving_average_filter_en
+ GENERIC MAP (
+ FILTER_ORDER_POWER => FILTER_ORDER_PWR,
+ TDATA_WIDTH => TDATA_WIDTH
+ )
+ PORT MAP (
+ aclk => aclk,
+ aresetn => aresetn,
+ s_axis_tvalid => s_axis_tvalid,
+ s_axis_tdata => s_axis_tdata,
+ s_axis_tlast => s_axis_tlast,
+ s_axis_tready => s_axis_tready,
+ m_axis_tvalid => m_axis_tvalid,
+ m_axis_tdata => m_axis_tdata,
+ m_axis_tlast => m_axis_tlast,
+ m_axis_tready => m_axis_tready,
+ enable_filter => enable_filter
+ );
+
+ -- Stimulus process
+ stim_proc : PROCESS
+ BEGIN
+ -- Reset
+ aresetn <= '0';
+ WAIT FOR 20 ns;
+ aresetn <= '1';
+ WAIT FOR 10 ns;
+
+ -- Test All Pass (enable_filter = '0')
+ enable_filter <= '0';
+ FOR i IN 0 TO 7 LOOP
+ -- SX sample
+ s_axis_tdata <= std_logic_vector(to_signed(i*100, TDATA_WIDTH));
+ s_axis_tvalid <= '1';
+ s_axis_tlast <= '0';
+ WAIT UNTIL rising_edge(aclk);
+ WHILE s_axis_tready /= '1' LOOP
+ WAIT UNTIL rising_edge(aclk);
+ END LOOP;
+ s_axis_tvalid <= '0';
+
+ -- DX sample (tlast high)
+ s_axis_tdata <= std_logic_vector(to_signed(i*100+50, TDATA_WIDTH));
+ s_axis_tvalid <= '1';
+ s_axis_tlast <= '1';
+ WAIT UNTIL rising_edge(aclk);
+ WHILE s_axis_tready /= '1' LOOP
+ WAIT UNTIL rising_edge(aclk);
+ END LOOP;
+ s_axis_tvalid <= '0';
+ END LOOP;
+
+ -- Test Moving Average (enable_filter = '1')
+ enable_filter <= '1';
+ FOR i IN 0 TO 7 LOOP
+ -- SX sample
+ s_axis_tdata <= std_logic_vector(to_signed(i*100, TDATA_WIDTH));
+ s_axis_tvalid <= '1';
+ s_axis_tlast <= '0';
+ WAIT UNTIL rising_edge(aclk);
+ WHILE s_axis_tready /= '1' LOOP
+ WAIT UNTIL rising_edge(aclk);
+ END LOOP;
+ s_axis_tvalid <= '0';
+
+ -- DX sample (tlast high)
+ s_axis_tdata <= std_logic_vector(to_signed(i*100+50, TDATA_WIDTH));
+ s_axis_tvalid <= '1';
+ s_axis_tlast <= '1';
+ WAIT UNTIL rising_edge(aclk);
+ WHILE s_axis_tready /= '1' LOOP
+ WAIT UNTIL rising_edge(aclk);
+ END LOOP;
+ s_axis_tvalid <= '0';
+ END LOOP;
+
+ -- End simulation
+ WAIT FOR 50 ns;
+ END PROCESS;
+
+END sim;
\ No newline at end of file
diff --git a/LAB3/src/all_pass_filter.vhd b/LAB3/src/all_pass_filter.vhd
index 43796f8..420e83c 100644
--- a/LAB3/src/all_pass_filter.vhd
+++ b/LAB3/src/all_pass_filter.vhd
@@ -24,7 +24,6 @@ END all_pass_filter;
ARCHITECTURE Behavioral OF all_pass_filter IS
- SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
BEGIN
@@ -33,17 +32,17 @@ BEGIN
-- of the moving_average_filter, but does not process or modify the samples.
-- It simply passes input data to the output unchanged, ensuring the same latency and interface behavior.
- -- Output assignments
- s_axis_tready <= s_axis_tready_int;
+ -- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
+ s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
PROCESS (aclk)
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
- s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
+ m_axis_tlast <= '0';
ELSE
-- Clear valid flag when master interface is ready
@@ -51,16 +50,12 @@ BEGIN
m_axis_tvalid_int <= '0';
END IF;
- -- Hndle data transfer
- IF s_axis_tvalid = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
- s_axis_tready_int <= '1';
+ -- Handle data transfer
+ IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
m_axis_tvalid_int <= '1';
m_axis_tdata <= s_axis_tdata;
m_axis_tlast <= s_axis_tlast;
-
- ELSE
- s_axis_tready_int <= '0';
-
+
END IF;
END IF;
diff --git a/LAB3/src/moving_average_filter.vhd b/LAB3/src/moving_average_filter.vhd
index c31ab83..b90ff42 100644
--- a/LAB3/src/moving_average_filter.vhd
+++ b/LAB3/src/moving_average_filter.vhd
@@ -41,14 +41,13 @@ ARCHITECTURE Behavioral OF moving_average_filter IS
SIGNAL sum_sx : signed(TDATA_WIDTH + FILTER_ORDER_POWER - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_ptr_sx : INTEGER RANGE 0 TO FILTER_ORDER - 1 := 0;
- SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
BEGIN
- -- Output assignments
+ -- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
- s_axis_tready <= s_axis_tready_int;
+ s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
PROCESS (aclk)
BEGIN
@@ -57,14 +56,14 @@ BEGIN
IF aresetn = '0' THEN
samples_dx <= (OTHERS => (OTHERS => '0'));
+ samples_sx <= (OTHERS => (OTHERS => '0'));
sum_dx <= (OTHERS => '0');
+ sum_sx <= (OTHERS => '0');
wr_ptr_dx <= 0;
+ wr_ptr_sx <= 0;
- s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
-
m_axis_tlast <= '0';
- m_axis_tdata <= (OTHERS => '0');
ELSE
-- Clear valid flag when master interface is ready
@@ -73,8 +72,10 @@ BEGIN
END IF;
-- Get and process data
- IF s_axis_tvalid = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
- IF s_axis_tlast = '1' THEN
+ IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
+
+ IF s_axis_tlast = '1' THEN
+ -- Right channel
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
samples_dx(wr_ptr_dx) <= signed(s_axis_tdata);
@@ -95,6 +96,7 @@ BEGIN
)
);
ELSE
+ -- Left channel
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
samples_sx(wr_ptr_sx) <= signed(s_axis_tdata);
@@ -116,13 +118,9 @@ BEGIN
);
END IF;
- s_axis_tready_int <= '1';
m_axis_tvalid_int <= '1';
m_axis_tlast <= s_axis_tlast;
- ELSE
- s_axis_tready_int <= '0';
-
END IF;
END IF;
diff --git a/LAB3/vivado/moving_average_filter/moving_average_filter.xpr b/LAB3/vivado/moving_average_filter/moving_average_filter.xpr
new file mode 100644
index 0000000..9098315
--- /dev/null
+++ b/LAB3/vivado/moving_average_filter/moving_average_filter.xpr
@@ -0,0 +1,406 @@
+
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+ Vivado Synthesis Defaults
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+ Default settings for Implementation.
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+ default_dashboard
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diff --git a/LAB3/vivado/moving_average_filter/tb_moving_average_behav.wcfg b/LAB3/vivado/moving_average_filter/tb_moving_average_behav.wcfg
new file mode 100644
index 0000000..3b05bf4
--- /dev/null
+++ b/LAB3/vivado/moving_average_filter/tb_moving_average_behav.wcfg
@@ -0,0 +1,86 @@
+
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+
+ aclk
+ aclk
+
+
+ aresetn
+ aresetn
+
+
+ enable_filter
+ enable_filter
+ #FF00FF
+ true
+
+
+ s_axis
+ label
+
+
+ s_axis_tdata[23:0]
+ s_axis_tdata[23:0]
+ SIGNEDDECRADIX
+
+
+ s_axis_tlast
+ s_axis_tlast
+
+
+ s_axis_tvalid
+ s_axis_tvalid
+ #00FFFF
+ true
+
+
+ s_axis_tready
+ s_axis_tready
+ #FFD700
+ true
+
+
+ m_axis
+ label
+
+
+ m_axis_tdata[23:0]
+ m_axis_tdata[23:0]
+ SIGNEDDECRADIX
+
+
+ m_axis_tlast
+ m_axis_tlast
+
+
+ m_axis_tvalid
+ m_axis_tvalid
+ #00FFFF
+ true
+
+
+ m_axis_tready
+ m_axis_tready
+ #FFD700
+ true
+
+