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Fix LFO

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This commit is contained in:
Davide Cavagnola
2025-05-27 14:18:46 +02:00
parent aa01b3a6e2
commit 6dea73806c
7 changed files with 512 additions and 308 deletions
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4
LAB3/design/lab_3/hdl/lab_3_wrapper.vhd
View File

@@ -1,8 +1,8 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Mon May 26 18:41:02 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Date : Tue May 27 14:09:13 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target lab_3_wrapper.bd
--Design : lab_3_wrapper
--Purpose : IP block netlist

544
LAB3/design/lab_3/lab_3.bd
View File

@@ -19,13 +19,13 @@
"axis_broadcaster_0": "",
"axi4stream_spi_master_0": "",
"axis_dual_i2s_0": "",
"digilent_jstk2_0": "",
"volume_controller_0": "",
"balance_controller_0": "",
"effect_selector_0": "",
"led_level_controller_0": "",
"led_controller_0": "",
"mute_controller_0": "",
"digilent_jstk2_0": "",
"moving_average_filte_0": "",
"LFO_0": ""
},
@@ -117,19 +117,19 @@
"inst_hier_path": "clk_wiz_0",
"parameters": {
"CLKOUT1_JITTER": {
"value": "149.337"
"value": "224.262"
},
"CLKOUT1_PHASE_ERROR": {
"value": "122.577"
"value": "296.868"
},
"CLKOUT1_REQUESTED_OUT_FREQ": {
"value": "100"
"value": "180"
},
"CLKOUT2_JITTER": {
"value": "201.826"
"value": "316.348"
},
"CLKOUT2_PHASE_ERROR": {
"value": "122.577"
"value": "296.868"
},
"CLKOUT2_REQUESTED_OUT_FREQ": {
"value": "22.579"
@@ -141,16 +141,16 @@
"value": "sys_clock"
},
"MMCM_CLKFBOUT_MULT_F": {
"value": "7.000"
"value": "49.500"
},
"MMCM_CLKOUT0_DIVIDE_F": {
"value": "7.000"
"value": "5.500"
},
"MMCM_CLKOUT1_DIVIDE": {
"value": "31"
"value": "44"
},
"MMCM_DIVCLK_DIVIDE": {
"value": "1"
"value": "5"
},
"NUM_OUT_CLKS": {
"value": "2"
@@ -201,7 +201,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -252,7 +252,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -305,7 +305,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -362,221 +362,6 @@
"xci_path": "ip\\lab_3_axis_dual_i2s_0_0\\lab_3_axis_dual_i2s_0_0.xci",
"inst_hier_path": "axis_dual_i2s_0"
},
"digilent_jstk2_0": {
"vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
"xci_name": "lab_3_digilent_jstk2_0_0",
"xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci",
"inst_hier_path": "digilent_jstk2_0",
"parameters": {
"CLKFREQ": {
"value": "215000000"
}
},
"reference_info": {
"ref_type": "hdl",
"ref_name": "digilent_jstk2",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "0",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
}
}
}
},
"ports": {
"aclk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"jstk_x": {
"direction": "O",
"left": "9",
"right": "0"
},
"jstk_y": {
"direction": "O",
"left": "9",
"right": "0"
},
"btn_jstk": {
"direction": "O"
},
"btn_trigger": {
"direction": "O"
},
"led_r": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_g": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_b": {
"direction": "I",
"left": "7",
"right": "0"
}
}
},
"volume_controller_0": {
"vlnv": "xilinx.com:module_ref:volume_controller:1.0",
"xci_name": "lab_3_volume_controller_0_0",
@@ -630,7 +415,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -700,7 +485,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -748,7 +533,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -826,7 +611,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -896,7 +681,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -944,7 +729,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -994,7 +779,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1100,7 +885,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1148,7 +933,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1260,7 +1045,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1330,7 +1115,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1378,7 +1163,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1406,6 +1191,221 @@
}
}
},
"digilent_jstk2_0": {
"vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
"xci_name": "lab_3_digilent_jstk2_0_0",
"xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci",
"inst_hier_path": "digilent_jstk2_0",
"parameters": {
"CLKFREQ": {
"value": "215000000"
}
},
"reference_info": {
"ref_type": "hdl",
"ref_name": "digilent_jstk2",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "0",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
}
}
}
},
"ports": {
"aclk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"jstk_x": {
"direction": "O",
"left": "9",
"right": "0"
},
"jstk_y": {
"direction": "O",
"left": "9",
"right": "0"
},
"btn_jstk": {
"direction": "O"
},
"btn_trigger": {
"direction": "O"
},
"led_r": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_g": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_b": {
"direction": "I",
"left": "7",
"right": "0"
}
}
},
"moving_average_filte_0": {
"vlnv": "xilinx.com:module_ref:moving_average_filter_en:1.0",
"xci_name": "lab_3_moving_average_filte_0_0",
@@ -1454,7 +1454,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1524,7 +1524,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1572,7 +1572,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1653,7 +1653,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1723,7 +1723,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1771,7 +1771,7 @@
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value": "180000000",
"value_src": "ip_prop"
},
"PHASE": {
@@ -1812,30 +1812,6 @@
"axi4stream_spi_master_0/SPI_M"
]
},
"balance_controller_0_m_axis": {
"interface_ports": [
"balance_controller_0/m_axis",
"volume_controller_0/s_axis"
]
},
"axis_broadcaster_0_M01_AXIS": {
"interface_ports": [
"axis_broadcaster_0/M01_AXIS",
"led_level_controller_0/s_axis"
]
},
"mute_controller_0_m_axis": {
"interface_ports": [
"mute_controller_0/m_axis",
"axis_broadcaster_0/S_AXIS"
]
},
"volume_controller_0_m_axis": {
"interface_ports": [
"volume_controller_0/m_axis",
"LFO_0/s_axis"
]
},
"axis_dual_i2s_0_m_axis": {
"interface_ports": [
"axis_dual_i2s_0/m_axis",
@@ -1848,18 +1824,42 @@
"axis_dual_i2s_0/s_axis"
]
},
"mute_controller_0_m_axis": {
"interface_ports": [
"mute_controller_0/m_axis",
"axis_broadcaster_0/S_AXIS"
]
},
"moving_average_filte_0_m_axis": {
"interface_ports": [
"balance_controller_0/s_axis",
"moving_average_filte_0/m_axis"
]
},
"balance_controller_0_m_axis": {
"interface_ports": [
"balance_controller_0/m_axis",
"volume_controller_0/s_axis"
]
},
"digilent_jstk2_0_m_axis": {
"interface_ports": [
"digilent_jstk2_0/m_axis",
"axi4stream_spi_master_0/S_AXIS"
]
},
"volume_controller_0_m_axis": {
"interface_ports": [
"volume_controller_0/m_axis",
"LFO_0/s_axis"
]
},
"axis_broadcaster_0_M01_AXIS": {
"interface_ports": [
"axis_broadcaster_0/M01_AXIS",
"led_level_controller_0/s_axis"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
@@ -1890,12 +1890,12 @@
"axis_broadcaster_0/aclk",
"axi4stream_spi_master_0/aclk",
"axis_dual_i2s_0/aclk",
"digilent_jstk2_0/aclk",
"volume_controller_0/aclk",
"balance_controller_0/aclk",
"effect_selector_0/aclk",
"led_level_controller_0/aclk",
"mute_controller_0/aclk",
"digilent_jstk2_0/aclk",
"moving_average_filte_0/aclk",
"LFO_0/aclk"
]
@@ -1929,12 +1929,12 @@
"axis_broadcaster_0/aresetn",
"axi4stream_spi_master_0/aresetn",
"axis_dual_i2s_0/aresetn",
"digilent_jstk2_0/aresetn",
"volume_controller_0/aresetn",
"balance_controller_0/aresetn",
"effect_selector_0/aresetn",
"led_level_controller_0/aresetn",
"mute_controller_0/aresetn",
"digilent_jstk2_0/aresetn",
"moving_average_filte_0/aresetn",
"LFO_0/aresetn"
]

22
LAB3/design/lab_3/lab_3.bda
View File

@@ -21,22 +21,22 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n1">
<data key="VM">lab_3</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="VH">2</data>
<data key="VM">lab_3</data>
<data key="VT">VR</data>
</node>
<edge id="e0" source="n1" target="n2">
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">lab_3</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0">
</edge>
<edge id="e1" source="n2" target="n0">
<edge id="e1" source="n0" target="n1">
</edge>
</graph>
</graphml>

43
LAB3/sim/tb_LFO.vhd
View File

@@ -90,6 +90,7 @@ BEGIN
-- Stimulus process
stim_proc : PROCESS
VARIABLE data_cnt : INTEGER := 0;
VARIABLE lr_flag : STD_LOGIC := '0'; -- '0' = SX, '1' = DX
BEGIN
-- Reset
aresetn <= '0';
@@ -98,20 +99,48 @@ BEGIN
WAIT FOR 10 ns;
-- Imposta parametri iniziali
lfo_enable <= '1'; -- o '0' se vuoi testare la modalit<69> bypass
lfo_period <= std_logic_vector(to_unsigned(512, JOYSTICK_LENGHT)); -- Valore fisso
lfo_enable <= '1';
lfo_period <= std_logic_vector(to_unsigned(1, JOYSTICK_LENGHT));
-- Loop infinito: invia dati ad ogni ciclo di clock
WHILE TRUE LOOP
WAIT UNTIL rising_edge(aclk);
-- Prepara il dato
IF lr_flag = '0' THEN
-- SX: aggiungi +100
s_axis_tdata <= std_logic_vector(to_signed(data_cnt + 100, CHANNEL_LENGHT));
s_axis_tlast <= '0';
ELSE
-- DX: valore normale
s_axis_tdata <= std_logic_vector(to_signed(data_cnt, CHANNEL_LENGHT));
s_axis_tlast <= '1';
END IF;
s_axis_tvalid <= '1';
s_axis_tlast <= '0'; -- Puoi impostare a '1' ogni N campioni se vuoi testare tlast
IF s_axis_tready = '1' THEN
data_cnt := data_cnt + 1;
-- Attendi handshake
WAIT UNTIL rising_edge(aclk);
WHILE s_axis_tready = '0' LOOP
WAIT UNTIL rising_edge(aclk);
END LOOP;
-- Dopo handshake, aggiorna flag/counter
IF lr_flag = '0' THEN
lr_flag := '1'; -- prossimo sar<61> DX
ELSE
lr_flag := '0'; -- prossimo sar<61> SX
data_cnt := data_cnt + 1; -- passa al prossimo campione solo dopo DX
END IF;
END LOOP;
END PROCESS;
-- Simula backpressure abbassando m_axis_tready ogni tanto
backpressure_proc : PROCESS
BEGIN
WAIT FOR 60 ns;
WAIT UNTIL rising_edge(aclk);
m_axis_tready <= '0';
WAIT FOR 20 ns;
WAIT UNTIL rising_edge(aclk);
m_axis_tready <= '1';
WAIT;
END PROCESS;
END sim;

8
LAB3/src/LFO.vhd
View File

@@ -50,7 +50,6 @@ ARCHITECTURE Behavioral OF LFO IS
SIGNAL trigger : STD_LOGIC := '0';
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL s_axis_tlast_reg : STD_LOGIC := '0';
SIGNAL m_axis_tdata_temp : SIGNED(CHANNEL_LENGHT + TRIANGULAR_COUNTER_LENGHT DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
@@ -59,7 +58,7 @@ BEGIN
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= s_axis_tready_int;
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
-- Optimized single process for LFO step and triangular waveform generation
PROCESS (aclk)
@@ -118,7 +117,6 @@ BEGIN
IF aresetn = '0' THEN
s_axis_tlast_reg <= '0';
s_axis_tready_int <= '0';
m_axis_tdata_temp <= (OTHERS => '0');
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
@@ -148,7 +146,7 @@ BEGIN
END IF;
-- Data input logic
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
IF s_axis_tvalid = '1' AND (m_axis_tready = '1' OR m_axis_tvalid_int = '0') THEN
IF lfo_enable = '1' THEN
m_axis_tdata_temp <= signed(s_axis_tdata) * tri_counter;
s_axis_tlast_reg <= s_axis_tlast;
@@ -169,8 +167,6 @@ BEGIN
END IF;
s_axis_tready_int <= m_axis_tready OR NOT m_axis_tvalid_int;
END IF;
END IF;

11
LAB3/vivado/LFO/LFO.xpr
View File

@@ -47,7 +47,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="10"/>
<Option Name="WTXSimLaunchSim" Val="53"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -95,6 +95,7 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../sim/tb_LFO.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -150,9 +151,7 @@
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
@@ -161,9 +160,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>

186
LAB3/vivado/lab3/lab3.xpr
View File

@@ -247,16 +247,17 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
@@ -269,11 +270,192 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
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<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
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<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
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<MsgAttr Name="RuleType" Val="1"/>
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