From 722b479811325ab1803f2b52b1047d56b935504c Mon Sep 17 00:00:00 2001 From: Davide Date: Tue, 22 Apr 2025 22:56:28 +0200 Subject: [PATCH] Create design folder and update projects --- .gitignore | 10 +- LAB2/design/lab_2/hdl/lab_2_wrapper.vhd | 49 + LAB2/design/lab_2/lab_2.bd | 1338 +++++++++++++++++ LAB2/design/lab_2/lab_2.bda | 42 + .../pak_depak/hdl/pak_depak_wrapper.vhd | 40 + LAB2/design/pak_depak/pak_depak.bd | 559 +++++++ LAB2/design/pak_depak/pak_depak.bda | 42 + LAB2/vivado/lab2/lab2.xpr | 36 +- LAB2/vivado/pak_depak/pak_depak.xpr | 26 +- 9 files changed, 2107 insertions(+), 35 deletions(-) create mode 100644 LAB2/design/lab_2/hdl/lab_2_wrapper.vhd create mode 100644 LAB2/design/lab_2/lab_2.bd create mode 100644 LAB2/design/lab_2/lab_2.bda create mode 100644 LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd create mode 100644 LAB2/design/pak_depak/pak_depak.bd create mode 100644 LAB2/design/pak_depak/pak_depak.bda diff --git a/.gitignore b/.gitignore index 0753da4..ced2a1e 100644 --- a/.gitignore +++ b/.gitignore @@ -68,4 +68,12 @@ vivado*.backup.log # SDK workspace -.sdk/ \ No newline at end of file +.sdk/ + +# design files +**/design/**/ipshared/ +**/design/**/ip/ +**/design/**/sim/ +**/design/**/synth/ +**/design/**/ui/ +**/design/**/hw_handoff/ \ No newline at end of file diff --git a/LAB2/design/lab_2/hdl/lab_2_wrapper.vhd b/LAB2/design/lab_2/hdl/lab_2_wrapper.vhd new file mode 100644 index 0000000..5326568 --- /dev/null +++ b/LAB2/design/lab_2/hdl/lab_2_wrapper.vhd @@ -0,0 +1,49 @@ +--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +--Date : Tue Apr 22 22:53:03 2025 +--Host : Davide-Samsung running 64-bit major release (build 9200) +--Command : generate_target lab_2_wrapper.bd +--Design : lab_2_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity lab_2_wrapper is + port ( + led_of : out STD_LOGIC; + led_ok : out STD_LOGIC; + led_uf : out STD_LOGIC; + reset : in STD_LOGIC; + sys_clock : in STD_LOGIC; + usb_uart_rxd : in STD_LOGIC; + usb_uart_txd : out STD_LOGIC + ); +end lab_2_wrapper; + +architecture STRUCTURE of lab_2_wrapper is + component lab_2 is + port ( + led_of : out STD_LOGIC; + led_ok : out STD_LOGIC; + led_uf : out STD_LOGIC; + sys_clock : in STD_LOGIC; + reset : in STD_LOGIC; + usb_uart_txd : out STD_LOGIC; + usb_uart_rxd : in STD_LOGIC + ); + end component lab_2; +begin +lab_2_i: component lab_2 + port map ( + led_of => led_of, + led_ok => led_ok, + led_uf => led_uf, + reset => reset, + sys_clock => sys_clock, + usb_uart_rxd => usb_uart_rxd, + usb_uart_txd => usb_uart_txd + ); +end STRUCTURE; diff --git a/LAB2/design/lab_2/lab_2.bd b/LAB2/design/lab_2/lab_2.bd new file mode 100644 index 0000000..16d6447 --- /dev/null +++ b/LAB2/design/lab_2/lab_2.bd @@ -0,0 +1,1338 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x880B1E867400A6BE", + "device": "xc7a35tcpg236-1", + "name": "lab_2", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "None", + "tool_version": "2020.2", + "validated": "true" + }, + "design_tree": { + "system_ila_0": "", + "clk_wiz_0": "", + "proc_sys_reset_1": "", + "AXI4Stream_UART_0": "", + "bram_writer_0": "", + "led_blinker_0": "", + "led_blinker_1": "", + "led_blinker_2": "", + "img_conv_0": "", + "depacketizer_0": "", + "packetizer_0": "", + "rgb2gray_0": "" + }, + "interface_ports": { + "usb_uart": { + "mode": "Master", + "vlnv": "xilinx.com:interface:uart_rtl:1.0" + } + }, + "ports": { + "led_of": { + "direction": "O" + }, + "led_ok": { + "direction": "O" + }, + "led_uf": { + "direction": "O" + }, + "sys_clock": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "lab_2_sys_clock", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000" + } + } + }, + "reset": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_HIGH" + } + } + } + }, + "components": { + "system_ila_0": { + "vlnv": "xilinx.com:ip:system_ila:1.1", + "xci_name": "lab_2_system_ila_0_1", + "xci_path": "ip\\lab_2_system_ila_0_1\\lab_2_system_ila_0_1.xci", + "inst_hier_path": "system_ila_0", + "parameters": { + "C_MON_TYPE": { + "value": "MIX" + }, + "C_NUM_MONITOR_SLOTS": { + "value": "3" + }, + "C_NUM_OF_PROBES": { + "value": "4" + }, + "C_SLOT": { + "value": "2" + }, + "C_SLOT_0_INTF_TYPE": { + "value": "xilinx.com:interface:axis_rtl:1.0" + }, + "C_SLOT_1_INTF_TYPE": { + "value": "xilinx.com:interface:axis_rtl:1.0" + }, + "C_SLOT_2_INTF_TYPE": { + "value": "xilinx.com:interface:axis_rtl:1.0" + } + }, + "interface_ports": { + "SLOT_0_AXIS": { + "mode": "Monitor", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + }, + "SLOT_1_AXIS": { + "mode": "Monitor", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + }, + "SLOT_2_AXIS": { + "mode": "Monitor", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + } + } + }, + "clk_wiz_0": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "xci_name": "lab_2_clk_wiz_0_1", + "xci_path": "ip\\lab_2_clk_wiz_0_1\\lab_2_clk_wiz_0_1.xci", + "inst_hier_path": "clk_wiz_0", + "parameters": { + "CLK_IN1_BOARD_INTERFACE": { + "value": "sys_clock" + }, + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "proc_sys_reset_1": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "lab_2_proc_sys_reset_1_1", + "xci_path": "ip\\lab_2_proc_sys_reset_1_1\\lab_2_proc_sys_reset_1_1.xci", + "inst_hier_path": "proc_sys_reset_1", + "parameters": { + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "AXI4Stream_UART_0": { + "vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1", + "xci_name": "lab_2_AXI4Stream_UART_0_2", + "xci_path": "ip\\lab_2_AXI4Stream_UART_0_2\\lab_2_AXI4Stream_UART_0_2.xci", + "inst_hier_path": "AXI4Stream_UART_0", + "parameters": { + "UART_BOARD_INTERFACE": { + "value": "usb_uart" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "bram_writer_0": { + "vlnv": "xilinx.com:module_ref:bram_writer:1.0", + "xci_name": "lab_2_bram_writer_0_0", + "xci_path": "ip\\lab_2_bram_writer_0_0\\lab_2_bram_writer_0_0.xci", + "inst_hier_path": "bram_writer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "bram_writer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "conv_addr": { + "direction": "I", + "left": "15", + "right": "0" + }, + "conv_data": { + "direction": "O", + "left": "6", + "right": "0" + }, + "start_conv": { + "direction": "O" + }, + "done_conv": { + "direction": "I" + }, + "write_ok": { + "direction": "O" + }, + "overflow": { + "direction": "O" + }, + "underflow": { + "direction": "O" + } + } + }, + "led_blinker_0": { + "vlnv": "xilinx.com:module_ref:led_blinker:1.0", + "xci_name": "lab_2_led_blinker_0_0", + "xci_path": "ip\\lab_2_led_blinker_0_0\\lab_2_led_blinker_0_0.xci", + "inst_hier_path": "led_blinker_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "led_blinker", + "boundary_crc": "0x0" + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "start_blink": { + "direction": "I" + }, + "led": { + "direction": "O" + } + } + }, + "led_blinker_1": { + "vlnv": "xilinx.com:module_ref:led_blinker:1.0", + "xci_name": "lab_2_led_blinker_1_0", + "xci_path": "ip\\lab_2_led_blinker_1_0\\lab_2_led_blinker_1_0.xci", + "inst_hier_path": "led_blinker_1", + "reference_info": { + "ref_type": "hdl", + "ref_name": "led_blinker", + "boundary_crc": "0x0" + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "start_blink": { + "direction": "I" + }, + "led": { + "direction": "O" + } + } + }, + "led_blinker_2": { + "vlnv": "xilinx.com:module_ref:led_blinker:1.0", + "xci_name": "lab_2_led_blinker_2_0", + "xci_path": "ip\\lab_2_led_blinker_2_0\\lab_2_led_blinker_2_0.xci", + "inst_hier_path": "led_blinker_2", + "reference_info": { + "ref_type": "hdl", + "ref_name": "led_blinker", + "boundary_crc": "0x0" + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "start_blink": { + "direction": "I" + }, + "led": { + "direction": "O" + } + } + }, + "img_conv_0": { + "vlnv": "xilinx.com:module_ref:img_conv:1.0", + "xci_name": "lab_2_img_conv_0_0", + "xci_path": "ip\\lab_2_img_conv_0_0\\lab_2_img_conv_0_0.xci", + "inst_hier_path": "img_conv_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "img_conv", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "conv_addr": { + "direction": "O", + "left": "15", + "right": "0" + }, + "conv_data": { + "direction": "I", + "left": "6", + "right": "0" + }, + "start_conv": { + "direction": "I" + }, + "done_conv": { + "direction": "O" + } + } + }, + "depacketizer_0": { + "vlnv": "xilinx.com:module_ref:depacketizer:1.0", + "xci_name": "lab_2_depacketizer_0_0", + "xci_path": "ip\\lab_2_depacketizer_0_0\\lab_2_depacketizer_0_0.xci", + "inst_hier_path": "depacketizer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "depacketizer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + }, + "packetizer_0": { + "vlnv": "xilinx.com:module_ref:packetizer:1.0", + "xci_name": "lab_2_packetizer_0_0", + "xci_path": "ip\\lab_2_packetizer_0_0\\lab_2_packetizer_0_0.xci", + "inst_hier_path": "packetizer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "packetizer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + }, + "rgb2gray_0": { + "vlnv": "xilinx.com:module_ref:rgb2gray:1.0", + "xci_name": "lab_2_rgb2gray_0_0", + "xci_path": "ip\\lab_2_rgb2gray_0_0\\lab_2_rgb2gray_0_0.xci", + "inst_hier_path": "rgb2gray_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "rgb2gray", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "resetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "resetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + } + }, + "interface_nets": { + "img_conv_0_m_axis": { + "interface_ports": [ + "img_conv_0/m_axis", + "packetizer_0/s_axis", + "system_ila_0/SLOT_1_AXIS" + ] + }, + "AXI4Stream_UART_0_UART": { + "interface_ports": [ + "usb_uart", + "AXI4Stream_UART_0/UART" + ] + }, + "AXI4Stream_UART_0_M00_AXIS_RX": { + "interface_ports": [ + "AXI4Stream_UART_0/M00_AXIS_RX", + "depacketizer_0/s_axis" + ] + }, + "Conn": { + "interface_ports": [ + "rgb2gray_0/s_axis", + "depacketizer_0/m_axis", + "system_ila_0/SLOT_0_AXIS" + ] + }, + "rgb2gray_0_m_axis": { + "interface_ports": [ + "rgb2gray_0/m_axis", + "bram_writer_0/s_axis", + "system_ila_0/SLOT_2_AXIS" + ] + }, + "packetizer_0_m_axis": { + "interface_ports": [ + "packetizer_0/m_axis", + "AXI4Stream_UART_0/S00_AXIS_TX" + ] + } + }, + "nets": { + "clk_wiz_0_clk_out1": { + "ports": [ + "clk_wiz_0/clk_out1", + "system_ila_0/clk", + "proc_sys_reset_1/slowest_sync_clk", + "AXI4Stream_UART_0/clk_uart", + "AXI4Stream_UART_0/m00_axis_rx_aclk", + "AXI4Stream_UART_0/s00_axis_tx_aclk", + "bram_writer_0/clk", + "led_blinker_0/clk", + "led_blinker_1/clk", + "led_blinker_2/clk", + "img_conv_0/clk", + "depacketizer_0/clk", + "packetizer_0/clk", + "rgb2gray_0/clk" + ] + }, + "proc_sys_reset_0_peripheral_aresetn": { + "ports": [ + "proc_sys_reset_1/peripheral_aresetn", + "system_ila_0/resetn", + "AXI4Stream_UART_0/m00_axis_rx_aresetn", + "AXI4Stream_UART_0/s00_axis_tx_aresetn", + "bram_writer_0/aresetn", + "led_blinker_0/aresetn", + "led_blinker_1/aresetn", + "led_blinker_2/aresetn", + "img_conv_0/aresetn", + "depacketizer_0/aresetn", + "packetizer_0/aresetn", + "rgb2gray_0/resetn" + ] + }, + "bram_writer_0_conv_data": { + "ports": [ + "bram_writer_0/conv_data", + "system_ila_0/probe0", + "img_conv_0/conv_data" + ] + }, + "bram_writer_0_start_conv": { + "ports": [ + "bram_writer_0/start_conv", + "system_ila_0/probe1", + "img_conv_0/start_conv" + ] + }, + "Net": { + "ports": [ + "img_conv_0/conv_addr", + "system_ila_0/probe2", + "bram_writer_0/conv_addr" + ] + }, + "Net1": { + "ports": [ + "img_conv_0/done_conv", + "system_ila_0/probe3", + "bram_writer_0/done_conv" + ] + }, + "bram_writer_0_write_ok": { + "ports": [ + "bram_writer_0/write_ok", + "led_blinker_0/start_blink" + ] + }, + "bram_writer_0_overflow": { + "ports": [ + "bram_writer_0/overflow", + "led_blinker_2/start_blink" + ] + }, + "bram_writer_0_underflow": { + "ports": [ + "bram_writer_0/underflow", + "led_blinker_1/start_blink" + ] + }, + "led_blinker_0_led": { + "ports": [ + "led_blinker_0/led", + "led_ok" + ] + }, + "led_blinker_1_led": { + "ports": [ + "led_blinker_1/led", + "led_uf" + ] + }, + "led_blinker_2_led": { + "ports": [ + "led_blinker_2/led", + "led_of" + ] + }, + "sys_clock_1": { + "ports": [ + "sys_clock", + "clk_wiz_0/clk_in1" + ] + }, + "clk_wiz_0_locked": { + "ports": [ + "clk_wiz_0/locked", + "proc_sys_reset_1/dcm_locked" + ] + }, + "reset_1": { + "ports": [ + "reset", + "proc_sys_reset_1/ext_reset_in", + "clk_wiz_0/reset" + ] + }, + "proc_sys_reset_1_peripheral_reset": { + "ports": [ + "proc_sys_reset_1/peripheral_reset", + "AXI4Stream_UART_0/rst" + ] + } + } + } +} \ No newline at end of file diff --git a/LAB2/design/lab_2/lab_2.bda b/LAB2/design/lab_2/lab_2.bda new file mode 100644 index 0000000..136d79c --- /dev/null +++ b/LAB2/design/lab_2/lab_2.bda @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + 2 + lab_2 + VR + + + active + 2 + PM + + + lab_2 + BC + + + + + + + diff --git a/LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd b/LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd new file mode 100644 index 0000000..c171dd7 --- /dev/null +++ b/LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd @@ -0,0 +1,40 @@ +--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +--Date : Tue Apr 22 22:40:46 2025 +--Host : Davide-Samsung running 64-bit major release (build 9200) +--Command : generate_target pak_depak_wrapper.bd +--Design : pak_depak_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity pak_depak_wrapper is + port ( + reset : in STD_LOGIC; + sys_clock : in STD_LOGIC; + usb_uart_rxd : in STD_LOGIC; + usb_uart_txd : out STD_LOGIC + ); +end pak_depak_wrapper; + +architecture STRUCTURE of pak_depak_wrapper is + component pak_depak is + port ( + reset : in STD_LOGIC; + sys_clock : in STD_LOGIC; + usb_uart_txd : out STD_LOGIC; + usb_uart_rxd : in STD_LOGIC + ); + end component pak_depak; +begin +pak_depak_i: component pak_depak + port map ( + reset => reset, + sys_clock => sys_clock, + usb_uart_rxd => usb_uart_rxd, + usb_uart_txd => usb_uart_txd + ); +end STRUCTURE; diff --git a/LAB2/design/pak_depak/pak_depak.bd b/LAB2/design/pak_depak/pak_depak.bd new file mode 100644 index 0000000..5cb0470 --- /dev/null +++ b/LAB2/design/pak_depak/pak_depak.bd @@ -0,0 +1,559 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x9157799052A71E23", + "device": "xc7a35tcpg236-1", + "name": "pak_depak", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "None", + "tool_version": "2020.2", + "validated": "true" + }, + "design_tree": { + "proc_sys_reset_0": "", + "clk_wiz_0": "", + "AXI4Stream_UART_0": "", + "packetizer_0": "", + "depacketizer_0": "" + }, + "interface_ports": { + "usb_uart": { + "mode": "Master", + "vlnv": "xilinx.com:interface:uart_rtl:1.0" + } + }, + "ports": { + "reset": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_HIGH" + } + } + }, + "sys_clock": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "pak_depak_sys_clock", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000" + } + } + } + }, + "components": { + "proc_sys_reset_0": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "pak_depak_proc_sys_reset_0_0", + "xci_path": "ip\\pak_depak_proc_sys_reset_0_0\\pak_depak_proc_sys_reset_0_0.xci", + "inst_hier_path": "proc_sys_reset_0", + "parameters": { + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "clk_wiz_0": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "xci_name": "pak_depak_clk_wiz_0_1", + "xci_path": "ip\\pak_depak_clk_wiz_0_1\\pak_depak_clk_wiz_0_1.xci", + "inst_hier_path": "clk_wiz_0", + "parameters": { + "CLK_IN1_BOARD_INTERFACE": { + "value": "sys_clock" + }, + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "AXI4Stream_UART_0": { + "vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1", + "xci_name": "pak_depak_AXI4Stream_UART_0_0", + "xci_path": "ip\\pak_depak_AXI4Stream_UART_0_0\\pak_depak_AXI4Stream_UART_0_0.xci", + "inst_hier_path": "AXI4Stream_UART_0", + "parameters": { + "UART_BOARD_INTERFACE": { + "value": "usb_uart" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "packetizer_0": { + "vlnv": "xilinx.com:module_ref:packetizer:1.0", + "xci_name": "pak_depak_packetizer_0_0", + "xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci", + "inst_hier_path": "packetizer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "packetizer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + }, + "depacketizer_0": { + "vlnv": "xilinx.com:module_ref:depacketizer:1.0", + "xci_name": "pak_depak_depacketizer_0_0", + "xci_path": "ip\\pak_depak_depacketizer_0_0\\pak_depak_depacketizer_0_0.xci", + "inst_hier_path": "depacketizer_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "depacketizer", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + } + } + } + }, + "interface_nets": { + "AXI4Stream_UART_0_UART": { + "interface_ports": [ + "usb_uart", + "AXI4Stream_UART_0/UART" + ] + }, + "depacketizer_0_m_axis": { + "interface_ports": [ + "depacketizer_0/m_axis", + "packetizer_0/s_axis" + ] + }, + "AXI4Stream_UART_0_M00_AXIS_RX": { + "interface_ports": [ + "AXI4Stream_UART_0/M00_AXIS_RX", + "depacketizer_0/s_axis" + ] + }, + "packetizer_0_m_axis": { + "interface_ports": [ + "packetizer_0/m_axis", + "AXI4Stream_UART_0/S00_AXIS_TX" + ] + } + }, + "nets": { + "reset_1": { + "ports": [ + "reset", + "proc_sys_reset_0/ext_reset_in", + "clk_wiz_0/reset" + ] + }, + "sys_clock_1": { + "ports": [ + "sys_clock", + "clk_wiz_0/clk_in1" + ] + }, + "clk_wiz_0_clk_out1": { + "ports": [ + "clk_wiz_0/clk_out1", + "AXI4Stream_UART_0/clk_uart", + "proc_sys_reset_0/slowest_sync_clk", + "AXI4Stream_UART_0/m00_axis_rx_aclk", + "AXI4Stream_UART_0/s00_axis_tx_aclk", + "packetizer_0/clk", + "depacketizer_0/clk" + ] + }, + "proc_sys_reset_0_peripheral_reset": { + "ports": [ + "proc_sys_reset_0/peripheral_reset", + "AXI4Stream_UART_0/rst" + ] + }, + "clk_wiz_0_locked": { + "ports": [ + "clk_wiz_0/locked", + "proc_sys_reset_0/dcm_locked" + ] + }, + "proc_sys_reset_0_peripheral_aresetn": { + "ports": [ + "proc_sys_reset_0/peripheral_aresetn", + "AXI4Stream_UART_0/m00_axis_rx_aresetn", + "AXI4Stream_UART_0/s00_axis_tx_aresetn", + "packetizer_0/aresetn", + "depacketizer_0/aresetn" + ] + } + } + } +} \ No newline at end of file diff --git a/LAB2/design/pak_depak/pak_depak.bda b/LAB2/design/pak_depak/pak_depak.bda new file mode 100644 index 0000000..a4f338d --- /dev/null +++ b/LAB2/design/pak_depak/pak_depak.bda @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + pak_depak + BC + + + 2 + pak_depak + VR + + + active + 2 + PM + + + + + + + diff --git a/LAB2/vivado/lab2/lab2.xpr b/LAB2/vivado/lab2/lab2.xpr index 611d728..548f521 100644 --- a/LAB2/vivado/lab2/lab2.xpr +++ b/LAB2/vivado/lab2/lab2.xpr @@ -55,13 +55,13 @@