Enhance bram_writer: add image size parameter, improve state machine for data handling, and refine signal management for better performance
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141
LAB2/sim/tb_bram_writer.vhd
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141
LAB2/sim/tb_bram_writer.vhd
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@@ -0,0 +1,141 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 04/17/2025
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-- Design Name:
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-- Module Name: tb_bram_writer - sim
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description: Testbench for bram_writer, stimulus and timing inspired by tb_img_conv.vhd
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY tb_bram_writer IS
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END ENTITY;
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ARCHITECTURE sim OF tb_bram_writer IS
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-- Testbench constants
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CONSTANT ADDR_WIDTH : POSITIVE := 4;
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CONSTANT IMG_SIZE : POSITIVE := 2; -- Small size for quick simulation
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-- Signals for DUT
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL aresetn : STD_LOGIC := '0';
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SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
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SIGNAL s_axis_tvalid : STD_LOGIC := '0';
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SIGNAL s_axis_tready : STD_LOGIC;
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SIGNAL s_axis_tlast : STD_LOGIC := '0';
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SIGNAL conv_addr : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL conv_data : STD_LOGIC_VECTOR(6 DOWNTO 0);
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SIGNAL start_conv : STD_LOGIC;
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SIGNAL done_conv : STD_LOGIC := '0';
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SIGNAL write_ok : STD_LOGIC;
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SIGNAL overflow : STD_LOGIC;
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SIGNAL underflow : STD_LOGIC;
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-- Instantiate DUT
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COMPONENT bram_writer IS
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GENERIC (
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ADDR_WIDTH : POSITIVE := 4;
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IMG_SIZE : POSITIVE := 2
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);
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PORT (
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clk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tready : OUT STD_LOGIC;
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s_axis_tlast : IN STD_LOGIC;
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conv_addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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conv_data : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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start_conv : OUT STD_LOGIC;
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done_conv : IN STD_LOGIC;
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write_ok : OUT STD_LOGIC;
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overflow : OUT STD_LOGIC;
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underflow : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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-- Clock generation
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clk <= not clk after 5 ns;
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-- Instantiate DUT
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bram_writer_inst: bram_writer
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GENERIC MAP (
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ADDR_WIDTH => ADDR_WIDTH,
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IMG_SIZE => IMG_SIZE
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)
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PORT MAP (
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clk => clk,
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aresetn => aresetn,
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s_axis_tdata => s_axis_tdata,
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s_axis_tvalid => s_axis_tvalid,
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s_axis_tready => s_axis_tready,
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s_axis_tlast => s_axis_tlast,
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conv_addr => conv_addr,
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conv_data => conv_data,
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start_conv => start_conv,
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done_conv => done_conv,
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write_ok => write_ok,
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overflow => overflow,
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underflow => underflow
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);
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-- Stimulus process
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stimulus : process
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begin
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-- Initial reset
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aresetn <= '0';
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wait for 10 ns;
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aresetn <= '1';
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wait until rising_edge(clk);
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-- Send IMG_SIZE*IMG_SIZE data words
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for i in 0 to IMG_SIZE*IMG_SIZE-1 loop
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s_axis_tdata <= std_logic_vector(to_unsigned(i, 8));
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s_axis_tvalid <= '1';
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if i = IMG_SIZE*IMG_SIZE-1 then
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s_axis_tlast <= '1';
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else
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s_axis_tlast <= '0';
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end if;
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wait until rising_edge(clk);
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-- Wait for ready
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while s_axis_tready /= '1' loop
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wait until rising_edge(clk);
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end loop;
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end loop;
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s_axis_tvalid <= '0';
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s_axis_tlast <= '0';
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-- Wait for write_ok and start_conv
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wait until write_ok = '1';
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wait until rising_edge(clk);
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-- Simulate convolution done
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done_conv <= '1';
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wait until rising_edge(clk);
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done_conv <= '0';
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-- Wait and finish
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wait for 20 ns;
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assert false report "Simulation finished." severity note;
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wait;
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end process;
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END ARCHITECTURE;
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@@ -1,67 +1,69 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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entity bram_writer is
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generic(
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ADDR_WIDTH: POSITIVE :=16
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ENTITY bram_writer IS
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GENERIC (
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ADDR_WIDTH : POSITIVE := 16;
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IMG_SIZE : POSITIVE := 256 -- Image size (256x256)
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);
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port (
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clk : in std_logic;
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aresetn : in std_logic;
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PORT (
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clk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_tdata : in std_logic_vector(7 downto 0);
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s_axis_tvalid : in std_logic;
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s_axis_tready : out std_logic;
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s_axis_tlast : in std_logic;
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s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tready : OUT STD_LOGIC;
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s_axis_tlast : IN STD_LOGIC;
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conv_addr: in std_logic_vector(ADDR_WIDTH-1 downto 0);
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conv_data: out std_logic_vector(6 downto 0);
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conv_addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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conv_data : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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start_conv: out std_logic;
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done_conv: in std_logic;
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start_conv : OUT STD_LOGIC;
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done_conv : IN STD_LOGIC;
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write_ok : out std_logic;
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overflow : out std_logic;
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underflow: out std_logic
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write_ok : OUT STD_LOGIC;
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overflow : OUT STD_LOGIC;
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underflow : OUT STD_LOGIC
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);
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end entity bram_writer;
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END ENTITY bram_writer;
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architecture rtl of bram_writer is
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ARCHITECTURE rtl OF bram_writer IS
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component bram_controller is
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generic (
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ADDR_WIDTH: POSITIVE :=16
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COMPONENT bram_controller IS
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GENERIC (
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ADDR_WIDTH : POSITIVE := 16
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);
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port (
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clk : in std_logic;
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aresetn : in std_logic;
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PORT (
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clk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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addr: in std_logic_vector(ADDR_WIDTH-1 downto 0);
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dout: out std_logic_vector(7 downto 0);
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din: in std_logic_vector(7 downto 0);
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we: in std_logic
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addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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we : IN STD_LOGIC
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);
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end component;
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END COMPONENT;
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TYPE state_type is (IDLE, RECEIVING, CONVOLUTION);
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TYPE state_type IS (IDLE, RECEIVING, CONVOLUTION);
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SIGNAL state : state_type := IDLE;
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SIGNAL s_axis_tready_int : std_logic := '0';
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SIGNAL s_axis_tready_int : STD_LOGIC := '0';
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SIGNAL bram_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); -- Indirizzo BRAM
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SIGNAL bram_we : std_logic := '0'; -- Segnale di scrittura per il BRAM
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SIGNAL bram_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); -- BRAM address
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SIGNAL bram_we : STD_LOGIC := '0'; -- Write enable signal for BRAM
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SIGNAL wr_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); -- Indirizzo di scrittura BRAM
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SIGNAL wr_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); -- Write address for BRAM
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begin
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BEGIN
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BRAM_CTRL: bram_controller
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generic map (
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-- Instantiate BRAM controller
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BRAM_CTRL : bram_controller
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GENERIC MAP(
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ADDR_WIDTH => ADDR_WIDTH
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)
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port map (
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PORT MAP(
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clk => clk,
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aresetn => aresetn,
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addr => bram_addr,
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@@ -70,47 +72,90 @@ begin
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we => bram_we
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);
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-- AXIS
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s_axis_tready <= s_axis_tready_int
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-- Assign AXIS ready signal
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s_axis_tready <= s_axis_tready_int;
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-- Gestione addr BRAM
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with state select bram_addr <= conv_addr when CONVOLUTION,
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wr_addr when Others;
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-- Select BRAM address based on state
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WITH state SELECT bram_addr <= conv_addr WHEN CONVOLUTION,
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wr_addr WHEN OTHERS;
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process(clk)
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begin
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if rising_edge(clk) then
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if aresetn = '0' then
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PROCESS (clk)
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BEGIN
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IF rising_edge(clk) THEN
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IF aresetn = '0' THEN
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-- Reset all signals and state
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state <= IDLE;
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s_axis_tready_int <= '0';
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bram_we <= '0';
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wr_addr <= (others => '0');
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wr_addr <= (OTHERS => '0');
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start_conv <= '0';
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write_ok <= '0';
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overflow <= '0';
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underflow <= '0';
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else
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ELSE
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-- Default assignments for each clock cycle
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start_conv <= '0';
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bram_we <= '0';
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write_ok <= '0';
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overflow <= '0';
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underflow <= '0';
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case state is
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when IDLE =>
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s_axis_tready_int <= '1';
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-- State machine for data handling
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CASE state IS
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WHEN IDLE =>
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-- Wait for valid input data
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IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
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-- valid data received, start receiving
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wr_addr <= (OTHERS => '0');
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bram_we <= '1'; -- Enable write to BRAM
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state <= RECEIVING;
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END IF;
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when RECEIVING =>
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WHEN RECEIVING =>
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-- Receiving data, increment write address
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IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
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-- Check for overflow: if address reaches max image size
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IF unsigned(wr_addr) = (IMG_SIZE ** 2 - 1) THEN
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overflow <= '1';
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state <= IDLE;
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ELSE
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-- Increment write address and write data to BRAM
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wr_addr <= STD_LOGIC_VECTOR(unsigned(wr_addr) + 1);
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bram_we <= '1'; -- Enable write to BRAM
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-- Check for last data signal
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IF s_axis_tlast = '1' THEN
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-- Check for underflow: if not enough data received
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IF unsigned(wr_addr) < (IMG_SIZE ** 2 - 2) THEN
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underflow <= '1';
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state <= IDLE;
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ELSE
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-- Data reception complete, start convolution
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write_ok <= '1';
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when CONVOLUTION =>
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s_axis_tready_int <= '0';
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start_conv <= '1';
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state <= CONVOLUTION;
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END IF;
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END IF;
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END IF;
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END IF;
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end case;
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end if;
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end if;
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end process;
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WHEN CONVOLUTION =>
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-- Wait for convolution to finish
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s_axis_tready_int <= '0';
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end architecture;
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IF done_conv = '1' THEN
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state <= IDLE;
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END IF;
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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END ARCHITECTURE;
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