Refactor and update various components in LAB2 design

- Updated node connections in lab_2.bda and pak_depak.bda to correct source and target references.
- Modified pak_depak_wrapper.vhd to reflect the correct timestamp.
- Rearranged the order of components in pak_depak.bd for clarity and consistency.
- Adjusted BRAM writer logic in bram_writer.vhd for improved data handling and comments for clarity.
- Enhanced depacketizer.vhd with additional comments and logic adjustments for better data reception.
- Refined divider_by_3.vhd to optimize division calculations and improve clarity in comments.
- Improved img_conv.vhd with better state management and comments for the convolution process.
- Updated led_blinker.vhd to enhance readability and maintainability with clearer comments.
- Enhanced packetizer.vhd to improve data handling and added comments for better understanding.
- Adjusted rgb2gray.vhd to include standard library comments for consistency.
- Updated test.py to improve image processing logic and added visualization for differences.
- Added new binary files for test_nopath.exe and archived project files for lab2 and pak_depak.
- Updated Vivado project files to ensure correct paths and settings for synthesis and implementation.

LAB2/src/bram_writer.vhd

@@ -1,6 +1,8 @@
+---------- DEFAULT LIBRARIES -------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.numeric_std.ALL;
+------------------------------------
 
 ENTITY bram_writer IS
     GENERIC (
@@ -79,7 +81,7 @@ BEGIN
     -- Assign AXIS ready signal
     s_axis_tready <= s_axis_tready_int;
 
-    -- Binding BRAM data to output
+    -- Output only the lower 7 bits of BRAM data
     conv_data <= bram_data_out(6 DOWNTO 0);
 
     -- Select BRAM address based on state
@@ -116,9 +118,8 @@ BEGIN
                 -- State machine for data handling
                 CASE state IS
                     WHEN IDLE =>
-                        -- Wait for valid input data
+                        -- Wait for valid input data to start writing
                         IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-                            -- valid data received, start receiving
                             wr_addr <= (OTHERS => '0');
                             bram_we <= '1'; -- Enable write to BRAM
                             bram_data_in <= s_axis_tdata; -- Write data to BRAM
@@ -145,7 +146,7 @@ BEGIN
                         END IF;
 
                     WHEN CHECK_DATA =>
-                        -- Check for overflow/underflow
+                        -- Check for overflow/underflow after data reception
                         IF overflow_flag = '1' THEN
                             overflow <= '1';
                             overflow_flag <= '0';
@@ -156,7 +157,6 @@ BEGIN
                         ELSE
                             -- Data reception complete, start convolution
                             write_ok <= '1';
-
                             s_axis_tready_int <= '0';
                             start_conv <= '1';
                             state <= CONVOLUTION;