From 86bf16abaf8351d0891c3ebf0d82bc8be793883d Mon Sep 17 00:00:00 2001 From: Cd16d Date: Fri, 23 May 2025 15:53:03 +0200 Subject: [PATCH] Refactor and optimize various components in LAB3 design - Updated lab_3.bda to correct node connections and attributes. - Enhanced LFO.vhd with improved signal handling and clamping logic. - Modified all_pass_filter.vhd to ensure proper data transfer. - Adjusted balance_controller.vhd to incorporate reset logic in signal assignments. - Cleaned up effect_selector.vhd by removing unnecessary assignments. - Improved led_level_controller.vhd for better readability and functionality. - Refined moving_average_filter_en.vhd to streamline AXIS assignments. - Enhanced mute_controller.vhd for clearer data flow management. - Updated lab3.xpr to correct file paths and simulation settings. --- LAB3/cons/io.xdc | 64 +- LAB3/design/lab_3/hdl/lab_3_wrapper.vhd | 6 +- LAB3/design/lab_3/lab_3.bd | 1710 +++++++++++------------ LAB3/design/lab_3/lab_3.bda | 12 +- LAB3/src/LFO.vhd | 50 +- LAB3/src/all_pass_filter.vhd | 3 +- LAB3/src/balance_controller.vhd | 2 +- LAB3/src/effect_selector.vhd | 1 - LAB3/src/led_level_controller.vhd | 183 +-- LAB3/src/moving_average_filter_en.vhd | 1 + LAB3/src/mute_controller.vhd | 29 +- LAB3/vivado/lab3/lab3.xpr | 52 +- 12 files changed, 1085 insertions(+), 1028 deletions(-) diff --git a/LAB3/cons/io.xdc b/LAB3/cons/io.xdc index ee4f8ea..262649a 100644 --- a/LAB3/cons/io.xdc +++ b/LAB3/cons/io.xdc @@ -1,3 +1,21 @@ +# pmod I2S2 connected to JB +set_property IOSTANDARD LVCMOS33 [get_ports rx_lrck_0] +set_property IOSTANDARD LVCMOS33 [get_ports rx_mclk_0] +set_property IOSTANDARD LVCMOS33 [get_ports rx_sclk_0] +set_property IOSTANDARD LVCMOS33 [get_ports rx_sdin_0] +set_property IOSTANDARD LVCMOS33 [get_ports tx_lrck_0] +set_property IOSTANDARD LVCMOS33 [get_ports tx_mclk_0] +set_property IOSTANDARD LVCMOS33 [get_ports tx_sclk_0] +set_property IOSTANDARD LVCMOS33 [get_ports tx_sdout_0] +set_property PACKAGE_PIN A14 [get_ports tx_mclk_0] +set_property PACKAGE_PIN A16 [get_ports tx_lrck_0] +set_property PACKAGE_PIN B15 [get_ports tx_sclk_0] +set_property PACKAGE_PIN B16 [get_ports tx_sdout_0] +set_property PACKAGE_PIN A15 [get_ports rx_mclk_0] +set_property PACKAGE_PIN A17 [get_ports rx_lrck_0] +set_property PACKAGE_PIN C15 [get_ports rx_sclk_0] +set_property PACKAGE_PIN C16 [get_ports rx_sdin_0] + # SPI connected to JA, top row set_property PACKAGE_PIN J1 [get_ports SPI_M_0_ss_io] set_property PACKAGE_PIN G2 [get_ports SPI_M_0_sck_io] @@ -7,7 +25,45 @@ set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io0_io] set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io1_io] set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_sck_io] set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_ss_io] -set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io0_io] -set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io1_io] -set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_sck_io] -set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_ss_io] + +# Button +set_property IOSTANDARD LVCMOS33 [get_ports effect] +set_property PACKAGE_PIN T18 [get_ports effect] + +# Switch +set_property IOSTANDARD LVCMOS33 [get_ports {lfo_enable}] +set_property PACKAGE_PIN V17 [get_ports {lfo_enable}] + +# LEDs +set_property PACKAGE_PIN U16 [get_ports {LED[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}] +set_property PACKAGE_PIN E19 [get_ports {LED[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}] +set_property PACKAGE_PIN U19 [get_ports {LED[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}] +set_property PACKAGE_PIN V19 [get_ports {LED[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}] +set_property PACKAGE_PIN W18 [get_ports {LED[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}] +set_property PACKAGE_PIN U15 [get_ports {LED[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}] +set_property PACKAGE_PIN U14 [get_ports {LED[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}] +set_property PACKAGE_PIN V14 [get_ports {LED[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}] +set_property PACKAGE_PIN V13 [get_ports {LED[8]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}] +set_property PACKAGE_PIN V3 [get_ports {LED[9]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}] +set_property PACKAGE_PIN W3 [get_ports {LED[10]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}] +set_property PACKAGE_PIN U3 [get_ports {LED[11]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}] +set_property PACKAGE_PIN P3 [get_ports {LED[12]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}] +set_property PACKAGE_PIN N3 [get_ports {LED[13]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}] +set_property PACKAGE_PIN P1 [get_ports {LED[14]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}] +set_property PACKAGE_PIN L1 [get_ports {LED[15]}] + set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}] \ No newline at end of file diff --git a/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd b/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd index 9f928f5..2d63faa 100644 --- a/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd +++ b/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd @@ -1,7 +1,7 @@ --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 ---Date : Mon May 19 16:34:49 2025 +--Date : Fri May 23 15:41:37 2025 --Host : Davide-Samsung running 64-bit major release (build 9200) --Command : generate_target lab_3_wrapper.bd --Design : lab_3_wrapper @@ -48,7 +48,6 @@ architecture STRUCTURE of lab_3_wrapper is tx_mclk_0 : out STD_LOGIC; lfo_enable : in STD_LOGIC; effect : in STD_LOGIC; - LED : out STD_LOGIC_VECTOR ( 15 downto 0 ); SPI_M_0_sck_t : out STD_LOGIC; SPI_M_0_io1_o : out STD_LOGIC; SPI_M_0_ss_t : out STD_LOGIC; @@ -60,7 +59,8 @@ architecture STRUCTURE of lab_3_wrapper is SPI_M_0_sck_o : out STD_LOGIC; SPI_M_0_ss_i : in STD_LOGIC; SPI_M_0_io1_i : in STD_LOGIC; - SPI_M_0_io0_i : in STD_LOGIC + SPI_M_0_io0_i : in STD_LOGIC; + LED : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); end component lab_3; component IOBUF is diff --git a/LAB3/design/lab_3/lab_3.bd b/LAB3/design/lab_3/lab_3.bd index 672426c..c927d19 100644 --- a/LAB3/design/lab_3/lab_3.bd +++ b/LAB3/design/lab_3/lab_3.bd @@ -17,17 +17,17 @@ "edge_detector_toggle_1": "", "debouncer_0": "", "axis_broadcaster_0": "", - "moving_average_filte_0": "", - "volume_controller_0": "", - "balance_controller_0": "", - "effect_selector_0": "", "led_controller_0": "", - "led_level_controller_0": "", "mute_controller_0": "", "axi4stream_spi_master_0": "", "axis_dual_i2s_0": "", "digilent_jstk2_0": "", - "LFO_0": "" + "moving_average_filte_0": "", + "volume_controller_0": "", + "led_level_controller_0": "", + "LFO_0": "", + "balance_controller_0": "", + "effect_selector_0": "" }, "interface_ports": { "SPI_M_0": { @@ -287,7 +287,7 @@ "inst_hier_path": "debouncer_0", "parameters": { "CLOCK_FREQ": { - "value": "200000000" + "value": "100000000" } }, "reference_info": { @@ -342,6 +342,469 @@ "xci_path": "ip\\lab_3_axis_broadcaster_0_0\\lab_3_axis_broadcaster_0_0.xci", "inst_hier_path": "axis_broadcaster_0" }, + "led_controller_0": { + "vlnv": "xilinx.com:module_ref:led_controller:1.0", + "xci_name": "lab_3_led_controller_0_0", + "xci_path": "ip\\lab_3_led_controller_0_0\\lab_3_led_controller_0_0.xci", + "inst_hier_path": "led_controller_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "led_controller", + "boundary_crc": "0x0" + }, + "ports": { + "mute_enable": { + "direction": "I" + }, + "filter_enable": { + "direction": "I" + }, + "led_r": { + "direction": "O", + "left": "7", + "right": "0" + }, + "led_g": { + "direction": "O", + "left": "7", + "right": "0" + }, + "led_b": { + "direction": "O", + "left": "7", + "right": "0" + } + } + }, + "mute_controller_0": { + "vlnv": "xilinx.com:module_ref:mute_controller:1.0", + "xci_name": "lab_3_mute_controller_0_0", + "xci_path": "ip\\lab_3_mute_controller_0_0\\lab_3_mute_controller_0_0.xci", + "inst_hier_path": "mute_controller_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "mute_controller", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "3", + "value_src": "auto" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "23", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "3", + "value_src": "auto" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "23", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "mute": { + "direction": "I" + } + } + }, + "axi4stream_spi_master_0": { + "vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0", + "xci_name": "lab_3_axi4stream_spi_master_0_0", + "xci_path": "ip\\lab_3_axi4stream_spi_master_0_0\\lab_3_axi4stream_spi_master_0_0.xci", + "inst_hier_path": "axi4stream_spi_master_0", + "parameters": { + "c_clkfreq": { + "value": "100000000" + }, + "c_sclkfreq": { + "value": "5000" + } + } + }, + "axis_dual_i2s_0": { + "vlnv": "DigiLAB:ip:axis_dual_i2s:1.0", + "xci_name": "lab_3_axis_dual_i2s_0_0", + "xci_path": "ip\\lab_3_axis_dual_i2s_0_0\\lab_3_axis_dual_i2s_0_0.xci", + "inst_hier_path": "axis_dual_i2s_0" + }, + "digilent_jstk2_0": { + "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0", + "xci_name": "lab_3_digilent_jstk2_0_0", + "xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci", + "inst_hier_path": "digilent_jstk2_0", + "parameters": { + "CLKFREQ": { + "value": "215000000" + } + }, + "reference_info": { + "ref_type": "hdl", + "ref_name": "digilent_jstk2", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "0", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + } + } + } + }, + "ports": { + "aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "jstk_x": { + "direction": "O", + "left": "9", + "right": "0" + }, + "jstk_y": { + "direction": "O", + "left": "9", + "right": "0" + }, + "btn_jstk": { + "direction": "O" + }, + "btn_trigger": { + "direction": "O" + }, + "led_r": { + "direction": "I", + "left": "7", + "right": "0" + }, + "led_g": { + "direction": "I", + "left": "7", + "right": "0" + }, + "led_b": { + "direction": "I", + "left": "7", + "right": "0" + } + } + }, "moving_average_filte_0": { "vlnv": "xilinx.com:module_ref:moving_average_filter_en:1.0", "xci_name": "lab_3_moving_average_filte_0_0", @@ -737,6 +1200,341 @@ } } }, + "led_level_controller_0": { + "vlnv": "xilinx.com:module_ref:led_level_controller:1.0", + "xci_name": "lab_3_led_level_controller_0_0", + "xci_path": "ip\\lab_3_led_level_controller_0_0\\lab_3_led_level_controller_0_0.xci", + "inst_hier_path": "led_level_controller_0", + "parameters": { + "clock_period_ns": { + "value": "10" + } + }, + "reference_info": { + "ref_type": "hdl", + "ref_name": "led_level_controller", + "boundary_crc": "0x0" + }, + "interface_ports": { + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "3", + "value_src": "auto" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "23", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "led": { + "direction": "O", + "left": "15", + "right": "0" + } + } + }, + "LFO_0": { + "vlnv": "xilinx.com:module_ref:LFO:1.0", + "xci_name": "lab_3_LFO_0_0", + "xci_path": "ip\\lab_3_LFO_0_0\\lab_3_LFO_0_0.xci", + "inst_hier_path": "LFO_0", + "parameters": { + "CLK_PERIOD_NS": { + "value": "10" + } + }, + "reference_info": { + "ref_type": "hdl", + "ref_name": "LFO", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "3", + "value_src": "auto" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "23", + "right": "0" + }, + "TLAST": { + "physical_name": "m_axis_tlast", + "direction": "O" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "3", + "value_src": "auto" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "1", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "23", + "right": "0" + }, + "TLAST": { + "physical_name": "s_axis_tlast", + "direction": "I" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "lfo_period": { + "direction": "I", + "left": "9", + "right": "0" + }, + "lfo_enable": { + "direction": "I" + } + } + }, "balance_controller_0": { "vlnv": "xilinx.com:module_ref:balance_controller:1.0", "xci_name": "lab_3_balance_controller_0_0", @@ -1005,817 +1803,25 @@ "right": "0" } } - }, - "led_controller_0": { - "vlnv": "xilinx.com:module_ref:led_controller:1.0", - "xci_name": "lab_3_led_controller_0_0", - "xci_path": "ip\\lab_3_led_controller_0_0\\lab_3_led_controller_0_0.xci", - "inst_hier_path": "led_controller_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "led_controller", - "boundary_crc": "0x0" - }, - "ports": { - "mute_enable": { - "direction": "I" - }, - "filter_enable": { - "direction": "I" - }, - "led_r": { - "direction": "O", - "left": "7", - "right": "0" - }, - "led_g": { - "direction": "O", - "left": "7", - "right": "0" - }, - "led_b": { - "direction": "O", - "left": "7", - "right": "0" - } - } - }, - "led_level_controller_0": { - "vlnv": "xilinx.com:module_ref:led_level_controller:1.0", - "xci_name": "lab_3_led_level_controller_0_0", - "xci_path": "ip\\lab_3_led_level_controller_0_0\\lab_3_led_level_controller_0_0.xci", - "inst_hier_path": "led_level_controller_0", - "parameters": { - "clock_period_ns": { - "value": "10" - } - }, - "reference_info": { - "ref_type": "hdl", - "ref_name": "led_level_controller", - "boundary_crc": "0x0" - }, - "interface_ports": { - "s_axis": { - "mode": "Slave", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "3", - "value_src": "auto" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "s_axis_tdata", - "direction": "I", - "left": "23", - "right": "0" - }, - "TLAST": { - "physical_name": "s_axis_tlast", - "direction": "I" - }, - "TVALID": { - "physical_name": "s_axis_tvalid", - "direction": "I" - }, - "TREADY": { - "physical_name": "s_axis_tready", - "direction": "O" - } - } - } - }, - "ports": { - "aclk": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "s_axis", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "aresetn", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - } - }, - "aresetn": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - }, - "led": { - "direction": "O", - "left": "15", - "right": "0" - } - } - }, - "mute_controller_0": { - "vlnv": "xilinx.com:module_ref:mute_controller:1.0", - "xci_name": "lab_3_mute_controller_0_0", - "xci_path": "ip\\lab_3_mute_controller_0_0\\lab_3_mute_controller_0_0.xci", - "inst_hier_path": "mute_controller_0", - "reference_info": { - "ref_type": "hdl", - "ref_name": "mute_controller", - "boundary_crc": "0x0" - }, - "interface_ports": { - "m_axis": { - "mode": "Master", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "3", - "value_src": "auto" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "m_axis_tdata", - "direction": "O", - "left": "23", - "right": "0" - }, - "TLAST": { - "physical_name": "m_axis_tlast", - "direction": "O" - }, - "TVALID": { - "physical_name": "m_axis_tvalid", - "direction": "O" - }, - "TREADY": { - "physical_name": "m_axis_tready", - "direction": "I" - } - } - }, - "s_axis": { - "mode": "Slave", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "3", - "value_src": "auto" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "s_axis_tdata", - "direction": "I", - "left": "23", - "right": "0" - }, - "TLAST": { - "physical_name": "s_axis_tlast", - "direction": "I" - }, - "TVALID": { - "physical_name": "s_axis_tvalid", - "direction": "I" - }, - "TREADY": { - "physical_name": "s_axis_tready", - "direction": "O" - } - } - } - }, - "ports": { - "aclk": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "m_axis:s_axis", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "aresetn", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - } - }, - "aresetn": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - }, - "mute": { - "direction": "I" - } - } - }, - "axi4stream_spi_master_0": { - "vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0", - "xci_name": "lab_3_axi4stream_spi_master_0_0", - "xci_path": "ip\\lab_3_axi4stream_spi_master_0_0\\lab_3_axi4stream_spi_master_0_0.xci", - "inst_hier_path": "axi4stream_spi_master_0", - "parameters": { - "c_clkfreq": { - "value": "215000000" - }, - "c_sclkfreq": { - "value": "5000" - } - } - }, - "axis_dual_i2s_0": { - "vlnv": "DigiLAB:ip:axis_dual_i2s:1.0", - "xci_name": "lab_3_axis_dual_i2s_0_0", - "xci_path": "ip\\lab_3_axis_dual_i2s_0_0\\lab_3_axis_dual_i2s_0_0.xci", - "inst_hier_path": "axis_dual_i2s_0" - }, - "digilent_jstk2_0": { - "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0", - "xci_name": "lab_3_digilent_jstk2_0_0", - "xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci", - "inst_hier_path": "digilent_jstk2_0", - "parameters": { - "CLKFREQ": { - "value": "215000000" - } - }, - "reference_info": { - "ref_type": "hdl", - "ref_name": "digilent_jstk2", - "boundary_crc": "0x0" - }, - "interface_ports": { - "m_axis": { - "mode": "Master", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "0", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "m_axis_tdata", - "direction": "O", - "left": "7", - "right": "0" - }, - "TVALID": { - "physical_name": "m_axis_tvalid", - "direction": "O" - }, - "TREADY": { - "physical_name": "m_axis_tready", - "direction": "I" - } - } - }, - "s_axis": { - "mode": "Slave", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "1", - "value_src": "constant" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "0", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "0", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "s_axis_tdata", - "direction": "I", - "left": "7", - "right": "0" - }, - "TVALID": { - "physical_name": "s_axis_tvalid", - "direction": "I" - } - } - } - }, - "ports": { - "aclk": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "m_axis:s_axis", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "aresetn", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - } - }, - "aresetn": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - }, - "jstk_x": { - "direction": "O", - "left": "9", - "right": "0" - }, - "jstk_y": { - "direction": "O", - "left": "9", - "right": "0" - }, - "btn_jstk": { - "direction": "O" - }, - "btn_trigger": { - "direction": "O" - }, - "led_r": { - "direction": "I", - "left": "7", - "right": "0" - }, - "led_g": { - "direction": "I", - "left": "7", - "right": "0" - }, - "led_b": { - "direction": "I", - "left": "7", - "right": "0" - } - } - }, - "LFO_0": { - "vlnv": "xilinx.com:module_ref:LFO:1.0", - "xci_name": "lab_3_LFO_0_0", - "xci_path": "ip\\lab_3_LFO_0_0\\lab_3_LFO_0_0.xci", - "inst_hier_path": "LFO_0", - "parameters": { - "CLK_PERIOD_NS": { - "value": "10" - } - }, - "reference_info": { - "ref_type": "hdl", - "ref_name": "LFO", - "boundary_crc": "0x0" - }, - "interface_ports": { - "m_axis": { - "mode": "Master", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "3", - "value_src": "auto" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "m_axis_tdata", - "direction": "O", - "left": "23", - "right": "0" - }, - "TLAST": { - "physical_name": "m_axis_tlast", - "direction": "O" - }, - "TVALID": { - "physical_name": "m_axis_tvalid", - "direction": "O" - }, - "TREADY": { - "physical_name": "m_axis_tready", - "direction": "I" - } - } - }, - "s_axis": { - "mode": "Slave", - "vlnv": "xilinx.com:interface:axis_rtl:1.0", - "parameters": { - "TDATA_NUM_BYTES": { - "value": "3", - "value_src": "auto" - }, - "TDEST_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TID_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "TUSER_WIDTH": { - "value": "0", - "value_src": "constant" - }, - "HAS_TREADY": { - "value": "1", - "value_src": "constant" - }, - "HAS_TSTRB": { - "value": "0", - "value_src": "constant" - }, - "HAS_TKEEP": { - "value": "0", - "value_src": "constant" - }, - "HAS_TLAST": { - "value": "1", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - }, - "port_maps": { - "TDATA": { - "physical_name": "s_axis_tdata", - "direction": "I", - "left": "23", - "right": "0" - }, - "TLAST": { - "physical_name": "s_axis_tlast", - "direction": "I" - }, - "TVALID": { - "physical_name": "s_axis_tvalid", - "direction": "I" - }, - "TREADY": { - "physical_name": "s_axis_tready", - "direction": "O" - } - } - } - }, - "ports": { - "aclk": { - "type": "clk", - "direction": "I", - "parameters": { - "ASSOCIATED_BUSIF": { - "value": "m_axis:s_axis", - "value_src": "constant" - }, - "ASSOCIATED_RESET": { - "value": "aresetn", - "value_src": "constant" - }, - "FREQ_HZ": { - "value": "100000000", - "value_src": "ip_prop" - }, - "PHASE": { - "value": "0.0", - "value_src": "ip_prop" - }, - "CLK_DOMAIN": { - "value": "/clk_wiz_0_clk_out1", - "value_src": "ip_prop" - } - } - }, - "aresetn": { - "type": "rst", - "direction": "I", - "parameters": { - "POLARITY": { - "value": "ACTIVE_LOW", - "value_src": "constant" - } - } - }, - "lfo_period": { - "direction": "I", - "left": "9", - "right": "0" - }, - "lfo_enable": { - "direction": "I" - } - } } }, "interface_nets": { - "axi4stream_spi_master_0_M_AXIS": { + "axi4stream_spi_master_0_SPI_M": { "interface_ports": [ - "axi4stream_spi_master_0/M_AXIS", - "digilent_jstk2_0/s_axis" + "SPI_M_0", + "axi4stream_spi_master_0/SPI_M" ] }, - "digilent_jstk2_0_m_axis": { + "axis_broadcaster_0_M00_AXIS": { "interface_ports": [ - "digilent_jstk2_0/m_axis", - "axi4stream_spi_master_0/S_AXIS" + "axis_broadcaster_0/M00_AXIS", + "axis_dual_i2s_0/s_axis" + ] + }, + "mute_controller_0_m_axis": { + "interface_ports": [ + "mute_controller_0/m_axis", + "axis_broadcaster_0/S_AXIS" ] }, "moving_average_filte_0_m_axis": { @@ -1824,12 +1830,6 @@ "moving_average_filte_0/m_axis" ] }, - "axis_broadcaster_0_M01_AXIS": { - "interface_ports": [ - "axis_broadcaster_0/M01_AXIS", - "led_level_controller_0/s_axis" - ] - }, "balance_controller_0_m_axis": { "interface_ports": [ "balance_controller_0/m_axis", @@ -1842,22 +1842,10 @@ "LFO_0/s_axis" ] }, - "axis_broadcaster_0_M00_AXIS": { + "axis_broadcaster_0_M01_AXIS": { "interface_ports": [ - "axis_broadcaster_0/M00_AXIS", - "axis_dual_i2s_0/s_axis" - ] - }, - "LFO_0_m_axis": { - "interface_ports": [ - "LFO_0/m_axis", - "mute_controller_0/s_axis" - ] - }, - "axi4stream_spi_master_0_SPI_M": { - "interface_ports": [ - "SPI_M_0", - "axi4stream_spi_master_0/SPI_M" + "axis_broadcaster_0/M01_AXIS", + "led_level_controller_0/s_axis" ] }, "axis_dual_i2s_0_m_axis": { @@ -1866,10 +1854,22 @@ "moving_average_filte_0/s_axis" ] }, - "mute_controller_0_m_axis": { + "digilent_jstk2_0_m_axis": { "interface_ports": [ - "mute_controller_0/m_axis", - "axis_broadcaster_0/S_AXIS" + "digilent_jstk2_0/m_axis", + "axi4stream_spi_master_0/S_AXIS" + ] + }, + "axi4stream_spi_master_0_M_AXIS": { + "interface_ports": [ + "axi4stream_spi_master_0/M_AXIS", + "digilent_jstk2_0/s_axis" + ] + }, + "LFO_0_m_axis": { + "interface_ports": [ + "LFO_0/m_axis", + "mute_controller_0/s_axis" ] } }, @@ -1888,16 +1888,16 @@ "edge_detector_toggle_1/clk", "debouncer_0/clk", "axis_broadcaster_0/aclk", - "moving_average_filte_0/aclk", - "volume_controller_0/aclk", - "balance_controller_0/aclk", - "effect_selector_0/aclk", - "led_level_controller_0/aclk", "mute_controller_0/aclk", "axi4stream_spi_master_0/aclk", "axis_dual_i2s_0/aclk", "digilent_jstk2_0/aclk", - "LFO_0/aclk" + "moving_average_filte_0/aclk", + "volume_controller_0/aclk", + "led_level_controller_0/aclk", + "LFO_0/aclk", + "balance_controller_0/aclk", + "effect_selector_0/aclk" ] }, "reset_1": { @@ -1927,16 +1927,16 @@ "proc_sys_reset_0/peripheral_aresetn", "debouncer_0/reset", "axis_broadcaster_0/aresetn", - "moving_average_filte_0/aresetn", - "volume_controller_0/aresetn", - "balance_controller_0/aresetn", - "effect_selector_0/aresetn", - "led_level_controller_0/aresetn", "mute_controller_0/aresetn", "axi4stream_spi_master_0/aresetn", "axis_dual_i2s_0/aresetn", "digilent_jstk2_0/aresetn", - "LFO_0/aresetn" + "moving_average_filte_0/aresetn", + "volume_controller_0/aresetn", + "led_level_controller_0/aresetn", + "LFO_0/aresetn", + "balance_controller_0/aresetn", + "effect_selector_0/aresetn" ] }, "proc_sys_reset_1_peripheral_aresetn": { @@ -2015,8 +2015,8 @@ "edge_detector_toggle_1_output_signal": { "ports": [ "edge_detector_toggle_1/output_signal", - "moving_average_filte_0/enable_filter", - "led_controller_0/filter_enable" + "led_controller_0/filter_enable", + "moving_average_filte_0/enable_filter" ] }, "led_controller_0_led_r": { @@ -2086,17 +2086,17 @@ "debouncer_0/input_signal" ] }, - "led_level_controller_0_led": { - "ports": [ - "led_level_controller_0/led", - "LED" - ] - }, "debouncer_0_debounced": { "ports": [ "debouncer_0/debounced", "effect_selector_0/effect" ] + }, + "led_level_controller_0_led": { + "ports": [ + "led_level_controller_0/led", + "LED" + ] } } } diff --git a/LAB3/design/lab_3/lab_3.bda b/LAB3/design/lab_3/lab_3.bda index 93a605f..8488c07 100644 --- a/LAB3/design/lab_3/lab_3.bda +++ b/LAB3/design/lab_3/lab_3.bda @@ -21,22 +21,22 @@ + lab_3 + BC + + active 2 PM - - lab_3 - BC - 2 lab_3 VR - + - + diff --git a/LAB3/src/LFO.vhd b/LAB3/src/LFO.vhd index be8272b..8252860 100644 --- a/LAB3/src/LFO.vhd +++ b/LAB3/src/LFO.vhd @@ -37,22 +37,23 @@ ARCHITECTURE Behavioral OF LFO IS CONSTANT LFO_COUNTER_BASE_PERIOD_US : INTEGER := 1000; -- 1ms CONSTANT ADJUSTMENT_FACTOR : INTEGER := 90; - CONSTANT JSTK_CENTER_VALUE : INTEGER := 2 ** (JOYSTICK_LENGHT - 1); - CONSTANT LFO_COUNTER_BASE_CLK_CYCLES : INTEGER := LFO_COUNTER_BASE_PERIOD_US * 1000 / CLK_PERIOD_NS; + CONSTANT JSTK_CENTER_VALUE : INTEGER := 2 ** (JOYSTICK_LENGHT - 1); -- 512 for 10 bits + CONSTANT LFO_COUNTER_BASE_CLK_CYCLES : INTEGER := LFO_COUNTER_BASE_PERIOD_US * 1000 / CLK_PERIOD_NS; -- 1ms = 100_000 clk cycles + CONSTANT LFO_CLK_CYCLES_MIN : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1)); -- 53_920 clk cycles + CONSTANT LFO_CLK_CYCLES_MAX : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES + ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1) - 1); -- 145_990 clk cycles - SIGNAL step_clk_cycles : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES; - SIGNAL step_counter : INTEGER RANGE 0 TO 2 ** TRIANGULAR_COUNTER_LENGHT - 1 := 0; - SIGNAL tri_counter : signed(TRIANGULAR_COUNTER_LENGHT - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL step_clk_cycles : INTEGER RANGE LFO_CLK_CYCLES_MIN TO LFO_CLK_CYCLES_MAX := LFO_COUNTER_BASE_CLK_CYCLES; + SIGNAL step_counter : INTEGER RANGE 0 TO LFO_CLK_CYCLES_MAX := 0; + SIGNAL tri_counter : SIGNED(TRIANGULAR_COUNTER_LENGHT - 1 DOWNTO 0) := (OTHERS => '0'); SIGNAL direction_up : STD_LOGIC := '1'; - SIGNAL s_axis_tready_int : STD_LOGIC := '0'; SIGNAL m_axis_tvalid_int : STD_LOGIC := '0'; BEGIN - -- Output assignments - s_axis_tready <= s_axis_tready_int; - m_axis_tvalid <= m_axis_tvalid_int; + -- Assigning the output signals + m_axis_tvalid <= m_axis_tvalid_int; + s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn; -- Optimized single process for LFO step and triangular waveform generation PROCESS (aclk) @@ -60,24 +61,21 @@ BEGIN IF rising_edge(aclk) THEN IF aresetn = '0' THEN + step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES; step_counter <= 0; tri_counter <= (OTHERS => '0'); direction_up <= '1'; ELSE - -- Clamp step_clk_cycles to a minimum of 1 to avoid negative or zero values - IF (LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * to_integer(JSTK_CENTER_VALUE - unsigned(lfo_period))) < 1 THEN - step_clk_cycles <= 1; - ELSE - step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * to_integer(JSTK_CENTER_VALUE - unsigned(lfo_period)); - END IF; + -- Set the step_clk_cycles based on the joystick input + step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * (JSTK_CENTER_VALUE - to_integer(unsigned(lfo_period))); IF lfo_enable = '1' THEN IF step_counter >= step_clk_cycles THEN step_counter <= 0; - IF tri_counter = 2 ** TRIANGULAR_COUNTER_LENGHT - 2 THEN + IF tri_counter = (2 ** TRIANGULAR_COUNTER_LENGHT) - 2 THEN direction_up <= '0'; ELSIF tri_counter = 1 THEN @@ -107,14 +105,12 @@ BEGIN END PROCESS; -- Handshake logic for the AXIS interface - PROCESS (aclk) + AXIS: PROCESS (aclk) BEGIN IF rising_edge(aclk) THEN IF aresetn = '0' THEN - s_axis_tready_int <= '0'; m_axis_tvalid_int <= '0'; - m_axis_tdata <= (OTHERS => '0'); m_axis_tlast <= '0'; ELSE @@ -123,12 +119,15 @@ BEGIN m_axis_tvalid_int <= '0'; END IF; - IF s_axis_tvalid = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN + IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN IF lfo_enable = '1' THEN m_axis_tdata <= STD_LOGIC_VECTOR( resize( - signed(s_axis_tdata) * tri_counter, - m_axis_tdata'LENGTH + shift_right( + signed(s_axis_tdata) * tri_counter, + TRIANGULAR_COUNTER_LENGHT + ), + CHANNEL_LENGHT ) ); @@ -136,19 +135,16 @@ BEGIN m_axis_tdata <= s_axis_tdata; END IF; - s_axis_tready_int <= '1'; + m_axis_tvalid_int <= '1'; m_axis_tlast <= s_axis_tlast; - ELSE - s_axis_tready_int <= '0'; - END IF; END IF; END IF; - END PROCESS; + END PROCESS AXIS; END ARCHITECTURE Behavioral; \ No newline at end of file diff --git a/LAB3/src/all_pass_filter.vhd b/LAB3/src/all_pass_filter.vhd index 420e83c..3980e15 100644 --- a/LAB3/src/all_pass_filter.vhd +++ b/LAB3/src/all_pass_filter.vhd @@ -52,8 +52,9 @@ BEGIN -- Handle data transfer IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN - m_axis_tvalid_int <= '1'; m_axis_tdata <= s_axis_tdata; + + m_axis_tvalid_int <= '1'; m_axis_tlast <= s_axis_tlast; END IF; diff --git a/LAB3/src/balance_controller.vhd b/LAB3/src/balance_controller.vhd index c1f0d2b..9941019 100644 --- a/LAB3/src/balance_controller.vhd +++ b/LAB3/src/balance_controller.vhd @@ -40,7 +40,7 @@ ARCHITECTURE Behavioral OF balance_controller IS BEGIN -- Assigning the output signals m_axis_tvalid <= m_axis_tvalid_int; - s_axis_tready <= m_axis_tready OR NOT m_axis_tvalid_int; + s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn; -- Balance to exp process to avoid changing the balance value when multiplying it for the sample data BALANCE_CALC : PROCESS (aclk) diff --git a/LAB3/src/effect_selector.vhd b/LAB3/src/effect_selector.vhd index 2d7025e..3936ea5 100644 --- a/LAB3/src/effect_selector.vhd +++ b/LAB3/src/effect_selector.vhd @@ -42,7 +42,6 @@ BEGIN ELSE -- volume/balance control volume <= jstck_y; - lfo_period <= (OTHERS => '0'); END IF; diff --git a/LAB3/src/led_level_controller.vhd b/LAB3/src/led_level_controller.vhd index b48f151..8558470 100644 --- a/LAB3/src/led_level_controller.vhd +++ b/LAB3/src/led_level_controller.vhd @@ -1,121 +1,122 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; -entity led_level_controller is - generic( - NUM_LEDS : positive := 16; - CHANNEL_LENGHT : positive := 24; - refresh_time_ms: positive :=1; - clock_period_ns: positive :=10 +ENTITY led_level_controller IS + GENERIC ( + NUM_LEDS : POSITIVE := 16; + CHANNEL_LENGHT : POSITIVE := 24; + refresh_time_ms : POSITIVE := 1; + clock_period_ns : POSITIVE := 10 ); - Port ( - - aclk : in std_logic; - aresetn : in std_logic; - - led : out std_logic_vector(NUM_LEDS-1 downto 0); + PORT ( - s_axis_tvalid : in std_logic; - s_axis_tdata : in std_logic_vector(CHANNEL_LENGHT-1 downto 0); - s_axis_tlast : in std_logic; - s_axis_tready : out std_logic + aclk : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + + led : OUT STD_LOGIC_VECTOR(NUM_LEDS - 1 DOWNTO 0); + + s_axis_tvalid : IN STD_LOGIC; + s_axis_tdata : IN STD_LOGIC_VECTOR(CHANNEL_LENGHT - 1 DOWNTO 0); + s_axis_tlast : IN STD_LOGIC; + s_axis_tready : OUT STD_LOGIC ); -end led_level_controller; +END led_level_controller; -architecture Behavioral of led_level_controller is - constant REFRESH_CYCLES : natural := (refresh_time_ms * 1_000_000) / clock_period_ns; +ARCHITECTURE Behavioral OF led_level_controller IS + CONSTANT REFRESH_CYCLES : NATURAL := (refresh_time_ms * 1_000_000) / clock_period_ns; - signal volume_value : signed(CHANNEL_LENGHT-1 downto 0) := (others => '0'); - signal abs_audio_left : unsigned(CHANNEL_LENGHT-2 downto 0) := (others => '0'); - signal abs_audio_right : unsigned(CHANNEL_LENGHT-2 downto 0) := (others => '0'); - signal leds_int : std_logic_vector(NUM_LEDS-1 downto 0) := (others => '0'); - signal led_update : std_logic := '0'; - signal refresh_counter : natural range 0 to REFRESH_CYCLES-1 := 0; + SIGNAL volume_value : signed(CHANNEL_LENGHT - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL abs_audio_left : unsigned(CHANNEL_LENGHT - 2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL abs_audio_right : unsigned(CHANNEL_LENGHT - 2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL leds_int : STD_LOGIC_VECTOR(NUM_LEDS - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL led_update : STD_LOGIC := '0'; + SIGNAL refresh_counter : NATURAL RANGE 0 TO REFRESH_CYCLES - 1 := 0; -begin +BEGIN led <= leds_int; s_axis_tready <= '1'; - -- Registrazione del valore audio assoluto - process(aclk) - variable sdata_signed : signed(CHANNEL_LENGHT-1 downto 0); - variable abs_value : unsigned(CHANNEL_LENGHT-1 downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - volume_value <= (others => '0'); - abs_audio_left <= (others => '0'); - abs_audio_right<= (others => '0'); - elsif s_axis_tvalid = '1' then + -- Registering the absolute audio value + PROCESS (aclk) + VARIABLE sdata_signed : signed(CHANNEL_LENGHT - 1 DOWNTO 0); + VARIABLE abs_value : unsigned(CHANNEL_LENGHT - 1 DOWNTO 0); + BEGIN + IF rising_edge(aclk) THEN + IF aresetn = '0' THEN + volume_value <= (OTHERS => '0'); + abs_audio_left <= (OTHERS => '0'); + abs_audio_right <= (OTHERS => '0'); + ELSIF s_axis_tvalid = '1' THEN sdata_signed := signed(s_axis_tdata); volume_value <= sdata_signed; - -- Calcolo valore assoluto - if sdata_signed(CHANNEL_LENGHT-1) = '1' then + -- Absolute value calculation + IF sdata_signed(CHANNEL_LENGHT - 1) = '1' THEN abs_value := unsigned(-sdata_signed); - else + ELSE abs_value := unsigned(sdata_signed); - end if; - -- Assegna al canale corretto - if s_axis_tlast = '1' then -- Canale sinistro - abs_audio_left <= abs_value(CHANNEL_LENGHT-2 downto 0); - else -- Canale destro - abs_audio_right <= abs_value(CHANNEL_LENGHT-2 downto 0); - end if; - end if; - end if; - end process; + END IF; + -- Assign to the correct channel + IF s_axis_tlast = '1' THEN -- Left channel + abs_audio_left <= abs_value(CHANNEL_LENGHT - 2 DOWNTO 0); + ELSE -- Right channel + abs_audio_right <= abs_value(CHANNEL_LENGHT - 2 DOWNTO 0); + END IF; + END IF; + END IF; + END PROCESS; - -- Contatore di refresh - process(aclk) - begin - if rising_edge(aclk) then - if aresetn = '0' then + -- Refresh counter + PROCESS (aclk) + BEGIN + IF rising_edge(aclk) THEN + IF aresetn = '0' THEN refresh_counter <= 0; led_update <= '0'; - elsif refresh_counter = REFRESH_CYCLES-1 then + ELSIF refresh_counter = REFRESH_CYCLES - 1 THEN refresh_counter <= 0; led_update <= '1'; - else + ELSE refresh_counter <= refresh_counter + 1; led_update <= '0'; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - -- Scaling lineare e aggiornamento LED - process(aclk) - variable leds_on : natural range 0 to NUM_LEDS; - variable temp_led_level : integer range 0 to NUM_LEDS; - variable abs_audio_sum : unsigned(CHANNEL_LENGHT-1 downto 0); - begin - if rising_edge(aclk) then - if aresetn = '0' then - leds_int <= (others => '0'); - elsif led_update = '1' then + -- Linear scaling and LED update + PROCESS (aclk) + VARIABLE leds_on : NATURAL RANGE 0 TO NUM_LEDS; + VARIABLE temp_led_level : INTEGER RANGE 0 TO NUM_LEDS; + VARIABLE abs_audio_sum : unsigned(CHANNEL_LENGHT - 1 DOWNTO 0); + BEGIN + IF rising_edge(aclk) THEN + IF aresetn = '0' THEN + leds_int <= (OTHERS => '0'); + ELSIF led_update = '1' THEN abs_audio_sum := resize(abs_audio_left, CHANNEL_LENGHT) + resize(abs_audio_right, CHANNEL_LENGHT); - if (abs_audio_left = 0 and abs_audio_right = 0) then + IF (abs_audio_left = 0 AND abs_audio_right = 0) THEN temp_led_level := 0; - else - -- Scaling automatico: puoi regolare la costante di shift per la sensibilità - temp_led_level := 1 + to_integer(shift_right(abs_audio_sum, CHANNEL_LENGHT-4)); - end if; + ELSE + -- Automatic scaling + -- Sensitivity can be adjusted by changing the shift constant + temp_led_level := 1 + to_integer(shift_right(abs_audio_sum, CHANNEL_LENGHT - 4)); + END IF; - -- Limita al massimo numero di LED - if temp_led_level > NUM_LEDS then + -- Limit to the maximum number of LEDs + IF temp_led_level > NUM_LEDS THEN leds_on := NUM_LEDS; - else + ELSE leds_on := temp_led_level; - end if; + END IF; - -- Aggiorna i LED - leds_int <= (others => '0'); - if leds_on > 0 then - leds_int(leds_on-1 downto 0) <= (others => '1'); - end if; - end if; - end if; - end process; -end Behavioral; + -- Update the LEDs + leds_int <= (OTHERS => '0'); + IF leds_on > 0 THEN + leds_int(leds_on - 1 DOWNTO 0) <= (OTHERS => '1'); + END IF; + END IF; + END IF; + END PROCESS; +END Behavioral; \ No newline at end of file diff --git a/LAB3/src/moving_average_filter_en.vhd b/LAB3/src/moving_average_filter_en.vhd index e768456..d7ad547 100644 --- a/LAB3/src/moving_average_filter_en.vhd +++ b/LAB3/src/moving_average_filter_en.vhd @@ -141,6 +141,7 @@ BEGIN -- Main AXIS assignments based on enable_filter s_axis_tready <= all_pass_s_tready WHEN enable_filter = '0' ELSE moving_avg_s_tready; + m_axis_tvalid <= all_pass_m_tvalid WHEN enable_filter = '0' ELSE moving_avg_m_tvalid; m_axis_tdata <= all_pass_m_tdata WHEN enable_filter = '0' ELSE moving_avg_m_tdata; m_axis_tlast <= all_pass_m_tlast WHEN enable_filter = '0' ELSE moving_avg_m_tlast; diff --git a/LAB3/src/mute_controller.vhd b/LAB3/src/mute_controller.vhd index f46eab0..217c66a 100644 --- a/LAB3/src/mute_controller.vhd +++ b/LAB3/src/mute_controller.vhd @@ -25,37 +25,40 @@ ENTITY mute_controller IS END mute_controller; ARCHITECTURE Behavioral OF mute_controller IS + + SIGNAL m_axis_tvalid_int : STD_LOGIC; + BEGIN + -- Assigning the output signals + m_axis_tvalid <= m_axis_tvalid_int; + s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn; + PROCESS (aclk) BEGIN IF rising_edge(aclk) THEN IF aresetn = '0' THEN - m_axis_tvalid <= '0'; - m_axis_tdata <= (OTHERS => '0'); + m_axis_tvalid_int <= '0'; m_axis_tlast <= '0'; - s_axis_tready <= '0'; ELSE - IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN - -- Accept input data - s_axis_tready <= '1'; - m_axis_tvalid <= '1'; - m_axis_tlast <= s_axis_tlast; + -- Clear valid flag when master interface is ready + IF m_axis_tready = '1' THEN + m_axis_tvalid_int <= '0'; + END IF; + -- Handle the data flow + IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN IF mute = '1' THEN m_axis_tdata <= (OTHERS => '0'); ELSE m_axis_tdata <= s_axis_tdata; END IF; - ELSE - -- Do not accept new data - s_axis_tready <= '0'; - m_axis_tvalid <= '0'; - m_axis_tlast <= '0'; + m_axis_tvalid_int <= '1'; + m_axis_tlast <= s_axis_tlast; END IF; diff --git a/LAB3/vivado/lab3/lab3.xpr b/LAB3/vivado/lab3/lab3.xpr index 7e2c548..246b498 100644 --- a/LAB3/vivado/lab3/lab3.xpr +++ b/LAB3/vivado/lab3/lab3.xpr @@ -55,13 +55,13 @@