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Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.

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Davide Cavagnola
2025-05-16 22:49:31 +02:00
parent 460378cdaa
commit 8fd7db7575
5 changed files with 40 additions and 37 deletions
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LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
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@@ -1,8 +1,8 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri May 16 16:28:03 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Date : Fri May 16 22:32:02 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper
--Purpose : IP block netlist