diff --git a/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd b/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd new file mode 100644 index 0000000..1709770 --- /dev/null +++ b/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd @@ -0,0 +1,143 @@ +--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +--Date : Mon May 12 14:54:08 2025 +--Host : Davide-Samsung running 64-bit major release (build 9200) +--Command : generate_target lab_3_wrapper.bd +--Design : lab_3_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity lab_3_wrapper is + port ( + LED : out STD_LOGIC_VECTOR ( 15 downto 0 ); + SPI_M_0_io0_io : inout STD_LOGIC; + SPI_M_0_io1_io : inout STD_LOGIC; + SPI_M_0_sck_io : inout STD_LOGIC; + SPI_M_0_ss_io : inout STD_LOGIC; + effect : in STD_LOGIC; + lfo_enable : in STD_LOGIC; + reset : in STD_LOGIC; + rx_lrck_0 : out STD_LOGIC; + rx_mclk_0 : out STD_LOGIC; + rx_sclk_0 : out STD_LOGIC; + rx_sdin_0 : in STD_LOGIC; + sys_clock : in STD_LOGIC; + tx_lrck_0 : out STD_LOGIC; + tx_mclk_0 : out STD_LOGIC; + tx_sclk_0 : out STD_LOGIC; + tx_sdout_0 : out STD_LOGIC + ); +end lab_3_wrapper; + +architecture STRUCTURE of lab_3_wrapper is + component lab_3 is + port ( + sys_clock : in STD_LOGIC; + reset : in STD_LOGIC; + tx_lrck_0 : out STD_LOGIC; + rx_sdin_0 : in STD_LOGIC; + rx_sclk_0 : out STD_LOGIC; + rx_lrck_0 : out STD_LOGIC; + rx_mclk_0 : out STD_LOGIC; + tx_sdout_0 : out STD_LOGIC; + tx_sclk_0 : out STD_LOGIC; + tx_mclk_0 : out STD_LOGIC; + lfo_enable : in STD_LOGIC; + effect : in STD_LOGIC; + LED : out STD_LOGIC_VECTOR ( 15 downto 0 ); + SPI_M_0_sck_t : out STD_LOGIC; + SPI_M_0_io1_o : out STD_LOGIC; + SPI_M_0_ss_t : out STD_LOGIC; + SPI_M_0_io0_o : out STD_LOGIC; + SPI_M_0_sck_i : in STD_LOGIC; + SPI_M_0_ss_o : out STD_LOGIC; + SPI_M_0_io0_t : out STD_LOGIC; + SPI_M_0_io1_t : out STD_LOGIC; + SPI_M_0_sck_o : out STD_LOGIC; + SPI_M_0_ss_i : in STD_LOGIC; + SPI_M_0_io1_i : in STD_LOGIC; + SPI_M_0_io0_i : in STD_LOGIC + ); + end component lab_3; + component IOBUF is + port ( + I : in STD_LOGIC; + O : out STD_LOGIC; + T : in STD_LOGIC; + IO : inout STD_LOGIC + ); + end component IOBUF; + signal SPI_M_0_io0_i : STD_LOGIC; + signal SPI_M_0_io0_o : STD_LOGIC; + signal SPI_M_0_io0_t : STD_LOGIC; + signal SPI_M_0_io1_i : STD_LOGIC; + signal SPI_M_0_io1_o : STD_LOGIC; + signal SPI_M_0_io1_t : STD_LOGIC; + signal SPI_M_0_sck_i : STD_LOGIC; + signal SPI_M_0_sck_o : STD_LOGIC; + signal SPI_M_0_sck_t : STD_LOGIC; + signal SPI_M_0_ss_i : STD_LOGIC; + signal SPI_M_0_ss_o : STD_LOGIC; + signal SPI_M_0_ss_t : STD_LOGIC; +begin +SPI_M_0_io0_iobuf: component IOBUF + port map ( + I => SPI_M_0_io0_o, + IO => SPI_M_0_io0_io, + O => SPI_M_0_io0_i, + T => SPI_M_0_io0_t + ); +SPI_M_0_io1_iobuf: component IOBUF + port map ( + I => SPI_M_0_io1_o, + IO => SPI_M_0_io1_io, + O => SPI_M_0_io1_i, + T => SPI_M_0_io1_t + ); +SPI_M_0_sck_iobuf: component IOBUF + port map ( + I => SPI_M_0_sck_o, + IO => SPI_M_0_sck_io, + O => SPI_M_0_sck_i, + T => SPI_M_0_sck_t + ); +SPI_M_0_ss_iobuf: component IOBUF + port map ( + I => SPI_M_0_ss_o, + IO => SPI_M_0_ss_io, + O => SPI_M_0_ss_i, + T => SPI_M_0_ss_t + ); +lab_3_i: component lab_3 + port map ( + LED(15 downto 0) => LED(15 downto 0), + SPI_M_0_io0_i => SPI_M_0_io0_i, + SPI_M_0_io0_o => SPI_M_0_io0_o, + SPI_M_0_io0_t => SPI_M_0_io0_t, + SPI_M_0_io1_i => SPI_M_0_io1_i, + SPI_M_0_io1_o => SPI_M_0_io1_o, + SPI_M_0_io1_t => SPI_M_0_io1_t, + SPI_M_0_sck_i => SPI_M_0_sck_i, + SPI_M_0_sck_o => SPI_M_0_sck_o, + SPI_M_0_sck_t => SPI_M_0_sck_t, + SPI_M_0_ss_i => SPI_M_0_ss_i, + SPI_M_0_ss_o => SPI_M_0_ss_o, + SPI_M_0_ss_t => SPI_M_0_ss_t, + effect => effect, + lfo_enable => lfo_enable, + reset => reset, + rx_lrck_0 => rx_lrck_0, + rx_mclk_0 => rx_mclk_0, + rx_sclk_0 => rx_sclk_0, + rx_sdin_0 => rx_sdin_0, + sys_clock => sys_clock, + tx_lrck_0 => tx_lrck_0, + tx_mclk_0 => tx_mclk_0, + tx_sclk_0 => tx_sclk_0, + tx_sdout_0 => tx_sdout_0 + ); +end STRUCTURE; diff --git a/LAB3/design/lab_3/lab_3.bd b/LAB3/design/lab_3/lab_3.bd index d980001..a2d9475 100644 --- a/LAB3/design/lab_3/lab_3.bd +++ b/LAB3/design/lab_3/lab_3.bd @@ -3,7 +3,6 @@ "design_info": { "boundary_crc": "0xFF71C05CB0B1FCB6", "device": "xc7a35tcpg236-1", - "gen_directory": "../../../../lab3.gen/sources_1/bd/lab_3", "name": "lab_3", "rev_ctrl_bd_flag": "RevCtrlBdOff", "synth_flow_mode": "None", @@ -1428,8 +1427,8 @@ }, "led_controller_0": { "vlnv": "xilinx.com:module_ref:led_controller:1.0", - "xci_name": "lab_3_led_controller_0_1", - "xci_path": "ip\\lab_3_led_controller_0_1\\lab_3_led_controller_0_1.xci", + "xci_name": "lab_3_led_controller_0_0", + "xci_path": "ip\\lab_3_led_controller_0_0\\lab_3_led_controller_0_0.xci", "inst_hier_path": "led_controller_0", "reference_info": { "ref_type": "hdl", @@ -1807,52 +1806,40 @@ } }, "interface_nets": { - "volume_controller_0_m_axis": { - "interface_ports": [ - "volume_controller_0/m_axis", - "LFO_0/s_axis" - ] - }, - "digilent_jstk2_0_m_axis": { - "interface_ports": [ - "digilent_jstk2_0/m_axis", - "axi4stream_spi_master_0/S_AXIS" - ] - }, "axis_dual_i2s_0_m_axis": { "interface_ports": [ "axis_dual_i2s_0/m_axis", "moving_average_filte_0/s_axis" ] }, - "mute_controller_0_m_axis": { - "interface_ports": [ - "mute_controller_0/m_axis", - "axis_broadcaster_0/S_AXIS" - ] - }, "LFO_0_m_axis": { "interface_ports": [ "LFO_0/m_axis", "mute_controller_0/s_axis" ] }, + "digilent_jstk2_0_m_axis": { + "interface_ports": [ + "digilent_jstk2_0/m_axis", + "axi4stream_spi_master_0/S_AXIS" + ] + }, "axi4stream_spi_master_0_SPI_M": { "interface_ports": [ "SPI_M_0", "axi4stream_spi_master_0/SPI_M" ] }, - "moving_average_filte_0_m_axis": { + "volume_controller_0_m_axis": { "interface_ports": [ - "balance_controller_0/s_axis", - "moving_average_filte_0/m_axis" + "volume_controller_0/m_axis", + "LFO_0/s_axis" ] }, - "balance_controller_0_m_axis": { + "mute_controller_0_m_axis": { "interface_ports": [ - "balance_controller_0/m_axis", - "volume_controller_0/s_axis" + "mute_controller_0/m_axis", + "axis_broadcaster_0/S_AXIS" ] }, "axis_broadcaster_0_M01_AXIS": { @@ -1867,6 +1854,18 @@ "axis_dual_i2s_0/s_axis" ] }, + "balance_controller_0_m_axis": { + "interface_ports": [ + "balance_controller_0/m_axis", + "volume_controller_0/s_axis" + ] + }, + "moving_average_filte_0_m_axis": { + "interface_ports": [ + "balance_controller_0/s_axis", + "moving_average_filte_0/m_axis" + ] + }, "axi4stream_spi_master_0_M_AXIS": { "interface_ports": [ "axi4stream_spi_master_0/M_AXIS", diff --git a/LAB3/design/lab_3/lab_3.bda b/LAB3/design/lab_3/lab_3.bda index 3fa1797..c595aff 100644 --- a/LAB3/design/lab_3/lab_3.bda +++ b/LAB3/design/lab_3/lab_3.bda @@ -26,17 +26,17 @@ VR + lab_3 + BC + + active 2 PM - - lab_3 - BC - - + - + diff --git a/LAB3/vivado/lab3/lab3.xpr b/LAB3/vivado/lab3/lab3.xpr index bb6e17f..db3a47d 100644 --- a/LAB3/vivado/lab3/lab3.xpr +++ b/LAB3/vivado/lab3/lab3.xpr @@ -55,13 +55,13 @@