Add new VHDL entities for image processing and update test scripts for Lab2

LAB2/src/bram_writer.vhd

@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bram_writer is
+    generic(
+        ADDR_WIDTH: POSITIVE :=16
+    );
+    port (
+        clk   : in std_logic;
+        aresetn : in std_logic;
+
+        s_axis_tdata : in std_logic_vector(7 downto 0);
+        s_axis_tvalid : in std_logic; 
+        s_axis_tready : out std_logic; 
+        s_axis_tlast : in std_logic;
+
+        conv_addr: in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        conv_data: out std_logic_vector(6 downto 0);
+
+        start_conv: out std_logic;
+        done_conv: in std_logic;
+
+        write_ok : out std_logic;
+        overflow : out std_logic;
+        underflow: out std_logic
+
+    );
+end entity bram_writer;
+
+architecture rtl of bram_writer is
+
+    component bram_controller is
+        generic (
+            ADDR_WIDTH: POSITIVE :=16
+        );
+        port (
+            clk   : in std_logic;
+            aresetn : in std_logic;
+    
+            addr: in std_logic_vector(ADDR_WIDTH-1 downto 0);
+            dout: out std_logic_vector(7 downto 0);
+            din: in std_logic_vector(7 downto 0);
+            we: in std_logic
+        );
+    end component;
+
+  
+
+begin
+    
+ 
+
+end architecture;