diff --git a/LAB2/sim/tb_depacketizer.vhd b/LAB2/sim/tb_depacketizer.vhd
index 6f709ad..3d3a606 100644
--- a/LAB2/sim/tb_depacketizer.vhd
+++ b/LAB2/sim/tb_depacketizer.vhd
@@ -73,7 +73,7 @@ ARCHITECTURE Behavioral OF tb_depacketizer IS
         4 => x"54",
         5 => x"65",
         6 => x"73",
-        7 => x"90"
+        7 => x"50"
     );
 
     SIGNAL tready_block_req : STD_LOGIC := '0';
diff --git a/LAB2/src/depacketizer.vhd b/LAB2/src/depacketizer.vhd
index 3fcc315..1f2f007 100644
--- a/LAB2/src/depacketizer.vhd
+++ b/LAB2/src/depacketizer.vhd
@@ -21,89 +21,83 @@ ENTITY depacketizer IS
         m_axis_tready : IN STD_LOGIC;
         m_axis_tlast : OUT STD_LOGIC
     );
-
+    
 END ENTITY depacketizer;
 
 ARCHITECTURE rtl OF depacketizer IS
 
-    TYPE state_type IS (WAITING_HEADER, RECEIVING);
+    TYPE state_type IS (WAITING_HEADER, RECEIVING, SEND);
     SIGNAL state : state_type := WAITING_HEADER;
 
-    SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);
+    SIGNAL s_axis_tready_int : STD_LOGIC := '1';
+    SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
+    SIGNAL m_axis_tdata_int : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL m_axis_tlast_int : STD_LOGIC := '0';
 
-    SIGNAL s_axis_tready_int : STD_LOGIC;
-    SIGNAL m_axis_tvalid_int : STD_LOGIC;
-
-    SIGNAL trigger : STD_LOGIC := '0';
+    SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL data_ready : STD_LOGIC := '0';
 
 BEGIN
 
     s_axis_tready <= s_axis_tready_int;
     m_axis_tvalid <= m_axis_tvalid_int;
+    m_axis_tdata <= m_axis_tdata_int;
+    m_axis_tlast <= m_axis_tlast_int;
 
     PROCESS (clk)
     BEGIN
-
         IF rising_edge(clk) THEN
             IF aresetn = '0' THEN
                 state <= WAITING_HEADER;
-
-                data_buffer <= (OTHERS => '0');
-
-                m_axis_tdata <= (OTHERS => '0');
-                m_axis_tlast <= '0';
-
-                s_axis_tready_int <= '0';
+                m_axis_tdata_int <= (OTHERS => '0');
+                m_axis_tlast_int <= '0';
+                s_axis_tready_int <= '1';
                 m_axis_tvalid_int <= '0';
-
+                data_buffer <= (OTHERS => '0');
+                data_ready <= '0';
             ELSE
+                m_axis_tlast_int <= '0';
 
-                -- Default values
-                m_axis_tlast <= '0';
-
-                -- Input data - slave
-                s_axis_tready_int <= m_axis_tready;
-
-                IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-                    data_buffer <= s_axis_tdata;
-                END IF;
-
-                -- Output data - master
-                IF m_axis_tready = '1' THEN
-                    m_axis_tvalid_int <= '0';
-                END IF;
-
-                IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
-                    m_axis_tvalid_int <= '1';
-                    m_axis_tdata <= data_buffer;
-
-                    trigger <= '0';
-                END IF;
-
-                -- State machine for depacketization
                 CASE state IS
                     WHEN WAITING_HEADER =>
+                        s_axis_tready_int <= '1';
+                        m_axis_tvalid_int <= '0';
+                        data_ready <= '0';
                         IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-                            IF data_buffer = STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)) THEN
-                                trigger <= '1';
+                            IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)) THEN
                                 state <= RECEIVING;
                             END IF;
                         END IF;
 
                     WHEN RECEIVING =>
                         IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-                            IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)) THEN
-                                m_axis_tlast <= '1';
-                                state <= WAITING_HEADER;
-                            ELSE
-                                trigger <= '1';
+                            IF data_ready = '1' THEN
+                                m_axis_tdata_int <= data_buffer;
+                                m_axis_tvalid_int <= '1';
+
+                                IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)) THEN
+                                    m_axis_tlast_int <= '1';
+                                    state <= WAITING_HEADER;
+                                    s_axis_tready_int <= '0';
+                                    data_ready <= '0';
+                                ELSE
+                                    state <= SEND;
+                                    s_axis_tready_int <= '0';
+                                END IF;
                             END IF;
+                            data_buffer <= s_axis_tdata;
+                            data_ready <= '1';
                         END IF;
 
+                    WHEN SEND =>
+                        IF m_axis_tvalid_int = '1' AND m_axis_tready = '1' THEN
+                            m_axis_tvalid_int <= '0';
+                            s_axis_tready_int <= '1';
+                            state <= RECEIVING;
+                        END IF;
                 END CASE;
             END IF;
         END IF;
-
     END PROCESS;
 
 END ARCHITECTURE;
\ No newline at end of file