diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..9167918
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,66 @@
+# Vivado-specific files and directories to ignore
+
+# Vivado temporary files
+*.jou
+*.log
+*.str
+*.pb
+*.wdb
+*.xpr
+*.xpa
+*.backup.*
+
+# Simulation and synthesis-generated files
+*.bit
+*.bin
+*.elf
+*.mcs
+*.mem
+*.prm
+*.tsi
+*.vcd
+*.vdi
+*.xml
+*.tcl
+*.ltx
+*.xci
+*.dcp
+*.xdc
+*.xsa
+*.xise
+*.ngc
+*.ngd
+*.ncd
+*.bgn
+*.blf
+*.unroutes
+*.rpx
+*.par
+*.twr
+*.twx
+*.ptwx
+*.mrp
+*.pcf
+*.qpf
+*.qsf
+*.qws
+
+# Vivado project directories
+.sim/
+.cache/
+.hw/
+.hwdbg/
+.ip_user_files/
+.webtalk/
+.xsim/
+.xil/
+.xilinx/
+.xtclsh_history
+.fpga_editor.log
+.fpga_editor.jou
+vivado_pid*.str
+vivado*.backup.jou
+vivado*.backup.log
+
+# SDK workspace
+.sdk/
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/gui_handlers.wdf b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/gui_handlers.wdf
new file mode 100644
index 0000000..dec3c32
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/gui_handlers.wdf
@@ -0,0 +1,34 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f72656d6f76655f73656c65637465645f656c656d656e7473:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:33:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626f61726463686f6f7365725f626f6172645f7461626c65:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f656e746974795f6e616d65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:39:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3132:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f666974:3138:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:3138:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f626c616e6b5f6f7065726174696f6e73:31:00:00
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+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f627265616b:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e5f616c6c:39:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:3131:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:3130:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f636f7079:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f637573746f6d5f636f6d6d616e6473:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:3139:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6c69766572756e666f72636f6d705f737065636966795f74696d655f616e645f756e697473:39:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:33:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6f725f6372656174655f736f757263655f66696c65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f7365727461626c655f7372635f63686f6f7365725f7461626c65:35:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d766965775f676f746f5f74696d655f30:35:00:00
+eof:1749896628
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/java_command_handlers.wdf b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..ccb5646
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/java_command_handlers.wdf
@@ -0,0 +1,10 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65786974617070:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e627265616b:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3130:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e616c6c:39:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:35:00:00
+eof:2926609623
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/project.wpc b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/project.wpc
new file mode 100644
index 0000000..9b34209
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/xsim.wdf b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/xsim.wdf
new file mode 100644
index 0000000..50afb2c
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:241934075
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.hw/lab0_pulse_width_modulator.lpr b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.hw/lab0_pulse_width_modulator.lpr
new file mode 100644
index 0000000..fd04c85
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.hw/lab0_pulse_width_modulator.lpr
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.ip_user_files/README.txt b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/compile.bat b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/compile.bat
new file mode 100644
index 0000000..c6d2067
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/compile.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Fri Mar 07 17:00:35 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_PulseWidthModulator_vhdl.prj"
+call xvhdl  --incr --relax -prj tb_PulseWidthModulator_vhdl.prj -log xvhdl.log
+call type xvhdl.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/elaborate.bat b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/elaborate.bat
new file mode 100644
index 0000000..1809505
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/elaborate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Fri Mar 07 17:00:38 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab -wto 5e30cf21c5094cb99e69e33f328f026e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_PulseWidthModulator_behav xil_defaultlib.tb_PulseWidthModulator -log elaborate.log"
+call xelab  -wto 5e30cf21c5094cb99e69e33f328f026e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_PulseWidthModulator_behav xil_defaultlib.tb_PulseWidthModulator -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/simulate.bat b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/simulate.bat
new file mode 100644
index 0000000..8317726
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/simulate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Fri Mar 07 17:00:41 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim tb_PulseWidthModulator_behav -key {Behavioral:sim_1:Functional:tb_PulseWidthModulator} -tclbatch tb_PulseWidthModulator.tcl -log simulate.log"
+call xsim  tb_PulseWidthModulator_behav -key {Behavioral:sim_1:Functional:tb_PulseWidthModulator} -tclbatch tb_PulseWidthModulator.tcl -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/tb_PulseWidthModulator_vhdl.prj b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/tb_PulseWidthModulator_vhdl.prj
new file mode 100644
index 0000000..91c4bda
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/tb_PulseWidthModulator_vhdl.prj
@@ -0,0 +1,7 @@
+# compile vhdl design source files
+vhdl xil_defaultlib  \
+"../../../../lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd" \
+"../../../../../../../Users/david/Downloads/tb_PulseWidthModulator.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/Compile_Options.txt b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/Compile_Options.txt
new file mode 100644
index 0000000..c92b5bd
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/Compile_Options.txt
@@ -0,0 +1 @@
+-wto "5e30cf21c5094cb99e69e33f328f026e" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_PulseWidthModulator_behav" "xil_defaultlib.tb_PulseWidthModulator" -log "elaborate.log" 
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/TempBreakPointFile.txt b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_0.win64.obj b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_0.win64.obj
new file mode 100644
index 0000000..466db14
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_0.win64.obj differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.c b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.c
new file mode 100644
index 0000000..ab3063c
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.c
@@ -0,0 +1,112 @@
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_29(char*, char *);
+IKI_DLLESPEC extern void execute_25(char*, char *);
+IKI_DLLESPEC extern void execute_26(char*, char *);
+IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[7] = {(funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_25, (funcp)execute_26, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 7;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc",  (void **)funcTab, 7);
+	iki_vhdl_file_variable_register(dp + 3376);
+	iki_vhdl_file_variable_register(dp + 3432);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc");
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_sv_type_file_path_name("xsim.dir/tb_PulseWidthModulator_behav/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/tb_PulseWidthModulator_behav/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/tb_PulseWidthModulator_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.win64.obj b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.win64.obj
new file mode 100644
index 0000000..5bfb4b2
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.win64.obj differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/.xsim_webtallk.info b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/.xsim_webtallk.info
new file mode 100644
index 0000000..dfa7fe5
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/.xsim_webtallk.info
@@ -0,0 +1,5 @@
+1741361410
+1741805296
+20
+1
+5e30cf21c5094cb99e69e33f328f026e
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/usage_statistics_ext_xsim.html b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/usage_statistics_ext_xsim.html
new file mode 100644
index 0000000..b61b1e7
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/usage_statistics_ext_xsim.html
@@ -0,0 +1,53 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
+  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed Mar 12 19:48:16 2025</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2020.2 (64-bit)</TD>
+  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>5e30cf21c5094cb99e69e33f328f026e</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>19</TD>
+  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
+  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
+  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>command=xsim</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>iteration=2</TD>
+    <TD>runtime=4 us</TD>
+    <TD>simulation_memory=8084_KB</TD>
+    <TD>simulation_time=0.08_sec</TD>
+</TR><TR ALIGN='LEFT'>    <TD>trace_waveform=true</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+</BODY>
+</HTML>
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.dbg b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.dbg
new file mode 100644
index 0000000..2947421
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.dbg differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc
new file mode 100644
index 0000000..b4e9d3e
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.rlx b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.rlx
new file mode 100644
index 0000000..5ae3237
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{ 
+    crc :  4590108242048840028  , 
+    ccp_crc :  0  , 
+    cmdline : " -wto 5e30cf21c5094cb99e69e33f328f026e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_PulseWidthModulator_behav xil_defaultlib.tb_PulseWidthModulator" , 
+    buildDate : "Nov 18 2020" , 
+    buildTime : "09:47:47" , 
+    linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/tb_PulseWidthModulator_behav/xsimk.exe\"   \"xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_0.win64.obj\" \"xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.rtti b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.rtti
new file mode 100644
index 0000000..19b7cff
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.rtti differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.svtype b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.svtype
new file mode 100644
index 0000000..afe268b
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.svtype differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.type b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.type
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index 0000000..99ec539
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.type differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.xdbg b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.xdbg
new file mode 100644
index 0000000..ef1a61e
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.xdbg differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsimSettings.ini b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsimSettings.ini
new file mode 100644
index 0000000..56ff420
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=75
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsimk.exe b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsimk.exe
new file mode 100644
index 0000000..b0b08da
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsimk.exe differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pulsewidthmodulator.vdb b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pulsewidthmodulator.vdb
new file mode 100644
index 0000000..174fd0f
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pulsewidthmodulator.vdb differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_pulsewidthmodulator.vdb b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_pulsewidthmodulator.vdb
new file mode 100644
index 0000000..9ecc080
Binary files /dev/null and b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_pulsewidthmodulator.vdb differ
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..14238be
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,6 @@
+0.7
+2020.2
+Nov 18 2020
+09:47:47
+C:/DESD/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd,1741363223,vhdl,,,,pulsewidthmodulator,,,,,,,,
+C:/Users/david/Downloads/tb_PulseWidthModulator.vhd,1741361906,vhdl,,,,tb_pulsewidthmodulator,,,,,,,,
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.ini b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..e8199b2
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd
new file mode 100644
index 0000000..bd7c9d5
--- /dev/null
+++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd
@@ -0,0 +1,83 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 07.03.2025 15:23:11
+-- Design Name: 
+-- Module Name: PulseWidthModulator - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PulseWidthModulator is
+    Generic(
+        BIT_LENGTH  : INTEGER RANGE 1 to 16 := 8;
+        T_ON_INIT   : POSITIVE := 64;   
+        PERIOD_INIT : POSITIVE := 128;             
+        PWM_INIT    : STD_LOGIC := '0'
+    );
+    Port (
+        reset   : IN STD_LOGIC;
+        clk     : IN STD_LOGIC;
+        
+        Ton     : IN std_logic_vector(BIT_LENGTH-1 downto 0);
+        Period  : IN std_logic_vector(BIT_LENGTH-1 downto 0);
+        PWM     : OUT std_logic
+    );
+ end PulseWidthModulator;
+
+architecture Behavioral of PulseWidthModulator is
+    signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0');
+    signal pwm_out : std_logic;
+begin
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            counter  <= (others => '0');
+            pwm_out  <= '0';  -- Assicura PWM spento al reset
+        elsif rising_edge(clk) then
+            if counter = unsigned(period) then
+                counter <= (others => '0');  -- Reset counter
+            else
+                counter <= counter + 1;  -- Incrementa il counter
+            end if;
+
+            -- Accendi il PWM all'inizio di ogni ciclo
+            if counter = 0 then
+                pwm_out <= '1';  
+            end if;
+
+            -- Spegni il PWM quando il contatore raggiunge Ton
+            if counter = unsigned(Ton) then
+                pwm_out <= '0';
+            end if;
+        end if;
+    end process;
+
+    PWM <= pwm_out; -- Output PWM
+
+end Behavioral;
+
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/gui_handlers.wdf b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/gui_handlers.wdf
new file mode 100644
index 0000000..028a2d6
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/gui_handlers.wdf
@@ -0,0 +1,23 @@
+version:1
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+eof:2034638031
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/java_command_handlers.wdf b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..31f7577
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/java_command_handlers.wdf
@@ -0,0 +1,8 @@
+version:1
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+eof:3524355110
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/project.wpc b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/project.wpc
new file mode 100644
index 0000000..6888ede
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:2
+eof:
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/synthesis.wdf b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/synthesis.wdf
new file mode 100644
index 0000000..2c80ca9
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/synthesis.wdf
@@ -0,0 +1,39 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/xsim.wdf b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/xsim.wdf
new file mode 100644
index 0000000..50afb2c
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
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+eof:241934075
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.hw/lab0_shift_register_v0.lpr b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.hw/lab0_shift_register_v0.lpr
new file mode 100644
index 0000000..fd04c85
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.hw/lab0_shift_register_v0.lpr
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.ip_user_files/README.txt b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/compile.bat b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/compile.bat
new file mode 100644
index 0000000..455631e
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/compile.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Mon Mar 03 14:57:07 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_ShiftRegister_v0_vhdl.prj"
+call xvhdl  --incr --relax -prj tb_ShiftRegister_v0_vhdl.prj -log xvhdl.log
+call type xvhdl.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/elaborate.bat b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/elaborate.bat
new file mode 100644
index 0000000..0984e33
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/elaborate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Mon Mar 03 14:57:09 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v0_behav xil_defaultlib.tb_ShiftRegister_v0 -log elaborate.log"
+call xelab  -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v0_behav xil_defaultlib.tb_ShiftRegister_v0 -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/shift_register_v0_v0_vhdl.prj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/shift_register_v0_v0_vhdl.prj
new file mode 100644
index 0000000..ee6a6c7
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/shift_register_v0_v0_vhdl.prj
@@ -0,0 +1,6 @@
+# compile vhdl design source files
+vhdl xil_defaultlib  \
+"../../../../lab_0_shift_register.srcs/sources_1/new/shift_register_v0.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/simulate.bat b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/simulate.bat
new file mode 100644
index 0000000..27960c4
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/simulate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Mon Mar 03 14:57:16 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim tb_ShiftRegister_v0_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v0} -tclbatch tb_ShiftRegister_v0.tcl -log simulate.log"
+call xsim  tb_ShiftRegister_v0_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v0} -tclbatch tb_ShiftRegister_v0.tcl -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/tb_ShiftRegister_v0_vhdl.prj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/tb_ShiftRegister_v0_vhdl.prj
new file mode 100644
index 0000000..22376f4
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/tb_ShiftRegister_v0_vhdl.prj
@@ -0,0 +1,7 @@
+# compile vhdl design source files
+vhdl xil_defaultlib  \
+"../../../../lab_0_shift_register.srcs/sources_1/new/ShiftRegister_v0.vhd" \
+"../../../../../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v0.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/Compile_Options.txt b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/Compile_Options.txt
new file mode 100644
index 0000000..2bfedcd
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/Compile_Options.txt
@@ -0,0 +1 @@
+-wto "79acb559a79942b0a66a9383c435cb5b" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "shift_register_v0_behav" "xil_defaultlib.shift_register_v0" -log "elaborate.log" 
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/TempBreakPointFile.txt b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_0.win64.obj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_0.win64.obj
new file mode 100644
index 0000000..77d3412
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_0.win64.obj differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.c b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.c
new file mode 100644
index 0000000..d5f6cba
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.c
@@ -0,0 +1,109 @@
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_8(char*, char *);
+IKI_DLLESPEC extern void execute_9(char*, char *);
+IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[4] = {(funcp)execute_8, (funcp)execute_9, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 4;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/shift_register_v0_behav/xsim.reloc",  (void **)funcTab, 4);
+	iki_vhdl_file_variable_register(dp + 2688);
+	iki_vhdl_file_variable_register(dp + 2744);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/shift_register_v0_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/shift_register_v0_behav/xsim.reloc");
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_sv_type_file_path_name("xsim.dir/shift_register_v0_behav/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/shift_register_v0_behav/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/shift_register_v0_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.win64.obj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.win64.obj
new file mode 100644
index 0000000..f0f536f
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.win64.obj differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/.xsim_webtallk.info b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/.xsim_webtallk.info
new file mode 100644
index 0000000..fe7ee2b
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/.xsim_webtallk.info
@@ -0,0 +1,5 @@
+1741009327
+0
+2
+1
+79acb559a79942b0a66a9383c435cb5b
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.html b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.html
new file mode 100644
index 0000000..8b83675
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.html
@@ -0,0 +1,63 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
+  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar  3 14:42:07 2025</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2020.2 (64-bit)</TD>
+  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>79acb559a79942b0a66a9383c435cb5b</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>1</TD>
+  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
+  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
+  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>command=xelab</TD>
+    <TD>debug=typical</TD>
+    <TD>dpi_used=false</TD>
+    <TD>file_counter=5</TD>
+</TR><TR ALIGN='LEFT'>    <TD>gendll=false</TD>
+    <TD>hwcosim=false</TD>
+    <TD>sdfmodeling=false</TD>
+    <TD>vhdl2008=false</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>compiler_memory=58596_KB</TD>
+    <TD>compiler_time=0.45_sec</TD>
+    <TD>simulation_image_code=62 KB</TD>
+    <TD>simulation_image_data=2 KB</TD>
+</TR><TR ALIGN='LEFT'>    <TD>total_instances=4</TD>
+    <TD>total_nets=0</TD>
+    <TD>total_processes=2</TD>
+    <TD>xilinx_hdl_libraries_used=secureip </TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+</BODY>
+</HTML>
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.wdm
new file mode 100644
index 0000000..0410530
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.wdm
@@ -0,0 +1,38 @@
+version = "1.0";
+clients =
+(
+    { client_name = "project"; 
+        rules = ( 
+            { 
+                context="software_version_and_target_device";
+                xml_map="software_version_and_target_device";
+                html_map="software_version_and_target_device";
+                html_format="UserEnvStyle";
+            },
+            { 
+                context="user_environment";
+                xml_map="user_environment";
+                html_map="user_environment";
+                html_format="UserEnvStyle";
+            }
+        );
+        },
+
+    { client_name = "xsim"; 
+        rules = ( 
+            { 
+                context="xsim\\command_line_options";
+                xml_map="xsim\\command_line_options";
+                html_map="xsim\\command_line_options";
+                html_format="UnisimStatsStyle";
+            },
+            { 
+                context="xsim\\usage";
+                xml_map="xsim\\usage";
+                html_map="xsim\\usage";
+                html_format="UnisimStatsStyle";
+            }
+        );
+        }
+);
+
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.dbg b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.dbg
new file mode 100644
index 0000000..8165756
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.dbg differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.reloc b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.reloc
new file mode 100644
index 0000000..ffce097
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.reloc differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.rlx b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.rlx
new file mode 100644
index 0000000..ee9ec9f
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{ 
+    crc :  14328939556394471054  , 
+    ccp_crc :  0  , 
+    cmdline : " -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot shift_register_v0_behav xil_defaultlib.shift_register_v0" , 
+    buildDate : "Nov 18 2020" , 
+    buildTime : "09:47:47" , 
+    linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/shift_register_v0_behav/xsimk.exe\"   \"xsim.dir/shift_register_v0_behav/obj/xsim_0.win64.obj\" \"xsim.dir/shift_register_v0_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.rtti b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.rtti
new file mode 100644
index 0000000..dd7b091
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.rtti differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.svtype b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.svtype
new file mode 100644
index 0000000..afe268b
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.svtype differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.type b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.type
new file mode 100644
index 0000000..580bb86
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.type differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.xdbg b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.xdbg
new file mode 100644
index 0000000..e5d529c
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.xdbg differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsimk.exe b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsimk.exe
new file mode 100644
index 0000000..886c5f7
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsimk.exe differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/Compile_Options.txt b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/Compile_Options.txt
new file mode 100644
index 0000000..b5a346f
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/Compile_Options.txt
@@ -0,0 +1 @@
+-wto "79acb559a79942b0a66a9383c435cb5b" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_ShiftRegister_v0_behav" "xil_defaultlib.tb_ShiftRegister_v0" -log "elaborate.log" 
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/TempBreakPointFile.txt b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_0.win64.obj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_0.win64.obj
new file mode 100644
index 0000000..cbc3d2a
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_0.win64.obj differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.c b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.c
new file mode 100644
index 0000000..962e137
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.c
@@ -0,0 +1,112 @@
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_13(char*, char *);
+IKI_DLLESPEC extern void execute_14(char*, char *);
+IKI_DLLESPEC extern void execute_15(char*, char *);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_12(char*, char *);
+IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[7] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_11, (funcp)execute_12, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 7;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc",  (void **)funcTab, 7);
+	iki_vhdl_file_variable_register(dp + 2864);
+	iki_vhdl_file_variable_register(dp + 2920);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc");
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_sv_type_file_path_name("xsim.dir/tb_ShiftRegister_v0_behav/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/tb_ShiftRegister_v0_behav/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/tb_ShiftRegister_v0_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.win64.obj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.win64.obj
new file mode 100644
index 0000000..148fbb1
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.win64.obj differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/webtalk/.xsim_webtallk.info b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/webtalk/.xsim_webtallk.info
new file mode 100644
index 0000000..cb0ce1b
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/webtalk/.xsim_webtallk.info
@@ -0,0 +1,5 @@
+1741010234
+1741010720
+3
+1
+79acb559a79942b0a66a9383c435cb5b
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/webtalk/usage_statistics_ext_xsim.html b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/webtalk/usage_statistics_ext_xsim.html
new file mode 100644
index 0000000..b984545
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/webtalk/usage_statistics_ext_xsim.html
@@ -0,0 +1,53 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
+  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar  3 15:05:20 2025</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2020.2 (64-bit)</TD>
+  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>79acb559a79942b0a66a9383c435cb5b</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
+  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
+  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
+  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>command=xsim</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>iteration=1</TD>
+    <TD>runtime=1 us</TD>
+    <TD>simulation_memory=8980_KB</TD>
+    <TD>simulation_time=0.01_sec</TD>
+</TR><TR ALIGN='LEFT'>    <TD>trace_waveform=true</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+</BODY>
+</HTML>
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.dbg b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.dbg
new file mode 100644
index 0000000..b41a0d9
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.dbg differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc
new file mode 100644
index 0000000..b6979ba
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.rlx b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.rlx
new file mode 100644
index 0000000..5aaa0ef
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{ 
+    crc :  9168915969947038954  , 
+    ccp_crc :  0  , 
+    cmdline : " -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v0_behav xil_defaultlib.tb_ShiftRegister_v0" , 
+    buildDate : "Nov 18 2020" , 
+    buildTime : "09:47:47" , 
+    linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/tb_ShiftRegister_v0_behav/xsimk.exe\"   \"xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_0.win64.obj\" \"xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.rtti b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.rtti
new file mode 100644
index 0000000..06f911b
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.rtti differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.svtype b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.svtype
new file mode 100644
index 0000000..afe268b
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.svtype differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.type b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.type
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index 0000000..a1776b8
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.type differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.xdbg b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.xdbg
new file mode 100644
index 0000000..5df6720
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsim.xdbg differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsimSettings.ini b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsimSettings.ini
new file mode 100644
index 0000000..56ff420
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=75
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsimk.exe b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsimk.exe
new file mode 100644
index 0000000..78ebb98
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/xsimk.exe differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shift_register_v0_v0.vdb b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shift_register_v0_v0.vdb
new file mode 100644
index 0000000..eca8d9d
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shift_register_v0_v0.vdb differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v0.vdb b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v0.vdb
new file mode 100644
index 0000000..5574fe0
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v0.vdb differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v0.vdb b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v0.vdb
new file mode 100644
index 0000000..3b9d678
Binary files /dev/null and b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v0.vdb differ
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..bc38957
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,7 @@
+0.7
+2020.2
+Nov 18 2020
+09:47:47
+C:/DESD/LAB0/lab_0_shift_register/lab_0_shift_register.srcs/sources_1/new/ShiftRegister_v0.vhd,1741010016,vhdl,,,,shiftregister_v0,,,,,,,,
+C:/DESD/LAB0/lab_0_shift_register/lab_0_shift_register.srcs/sources_1/new/shift_register_v0.vhd,1741009257,vhdl,,,,shift_register_v0,,,,,,,,
+C:/Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v0.vhd,1741009565,vhdl,,,,tb_shiftregister_v0,,,,,,,,
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.ini b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..e8199b2
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd
new file mode 100644
index 0000000..af89a1a
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03.03.2025 14:49:43
+-- Design Name: 
+-- Module Name: ShiftRegister_v0 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ShiftRegister_v0 is
+    Port ( reset : in STD_LOGIC;
+           clk : in STD_LOGIC;
+           din : in STD_LOGIC;
+           dout : out STD_LOGIC);
+end ShiftRegister_v0;
+
+architecture Behavioral of ShiftRegister_v0 is
+    signal sr : std_logic := '0';
+begin
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            sr <= '0';
+        elsif rising_edge(clk) then
+            sr <= din;
+        end if;
+    end process;
+    
+    dout <= sr;
+
+end Behavioral;
diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd
new file mode 100644
index 0000000..d2bff85
--- /dev/null
+++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03.03.2025 14:21:16
+-- Design Name: 
+-- Module Name: shift_register_v0 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity shift_register_v0 is
+    Port ( reset : in STD_LOGIC;
+           clk : in STD_LOGIC;
+           din : in STD_LOGIC;
+           dout : out STD_LOGIC);
+end shift_register_v0;
+
+architecture Behavioral of shift_register_v0 is
+    signal sr : std_logic := '0';
+begin
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            sr <= '0';
+        elsif rising_edge(clk) then
+            sr <= din;
+        end if;
+    end process;
+    
+    dout <= sr;
+
+end Behavioral;
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/gui_handlers.wdf b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/gui_handlers.wdf
new file mode 100644
index 0000000..c159b14
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/gui_handlers.wdf
@@ -0,0 +1,26 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:35:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f646566696e655f6d6f64756c65735f616e645f737065636966795f696f5f706f727473:38:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3232:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3130:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f73657268656c706572735f6a756d705f746f5f646f776e6c6f6164735f6469726563746f7279:31:00:00
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+eof:4291911915
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/java_command_handlers.wdf b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..e2745ad
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/java_command_handlers.wdf
@@ -0,0 +1,5 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:31:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65786974617070:32:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:39:00:00
+eof:1119620138
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/project.wpc b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/project.wpc
new file mode 100644
index 0000000..6888ede
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:2
+eof:
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/xsim.wdf b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/xsim.wdf
new file mode 100644
index 0000000..50afb2c
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:241934075
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.hw/lab0_shift_register_v1.lpr b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.hw/lab0_shift_register_v1.lpr
new file mode 100644
index 0000000..fd04c85
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.hw/lab0_shift_register_v1.lpr
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.ip_user_files/README.txt b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/compile.bat b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/compile.bat
new file mode 100644
index 0000000..9ea3eb2
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/compile.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Mon Mar 03 15:31:33 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_ShiftRegister_v1_vhdl.prj"
+call xvhdl  --incr --relax -prj tb_ShiftRegister_v1_vhdl.prj -log xvhdl.log
+call type xvhdl.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/elaborate.bat b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/elaborate.bat
new file mode 100644
index 0000000..7dce7f9
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/elaborate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Mon Mar 03 15:31:34 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab -wto b6c8e7e1e5944b109219f67e64ef5d5f --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v1_behav xil_defaultlib.tb_ShiftRegister_v1 -log elaborate.log"
+call xelab  -wto b6c8e7e1e5944b109219f67e64ef5d5f --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v1_behav xil_defaultlib.tb_ShiftRegister_v1 -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/simulate.bat b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/simulate.bat
new file mode 100644
index 0000000..77eaff5
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/simulate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Mon Mar 03 15:31:36 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim tb_ShiftRegister_v1_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v1} -tclbatch tb_ShiftRegister_v1.tcl -log simulate.log"
+call xsim  tb_ShiftRegister_v1_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v1} -tclbatch tb_ShiftRegister_v1.tcl -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/tb_ShiftRegister_v1_vhdl.prj b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/tb_ShiftRegister_v1_vhdl.prj
new file mode 100644
index 0000000..3519c04
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/tb_ShiftRegister_v1_vhdl.prj
@@ -0,0 +1,7 @@
+# compile vhdl design source files
+vhdl xil_defaultlib  \
+"../../../../lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd" \
+"../../../../../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v1.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/Compile_Options.txt b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/Compile_Options.txt
new file mode 100644
index 0000000..e771500
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/Compile_Options.txt
@@ -0,0 +1 @@
+-wto "b6c8e7e1e5944b109219f67e64ef5d5f" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_ShiftRegister_v1_behav" "xil_defaultlib.tb_ShiftRegister_v1" -log "elaborate.log" 
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/TempBreakPointFile.txt b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_0.win64.obj b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_0.win64.obj
new file mode 100644
index 0000000..3243144
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_0.win64.obj differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.c b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.c
new file mode 100644
index 0000000..8852e24
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.c
@@ -0,0 +1,112 @@
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_13(char*, char *);
+IKI_DLLESPEC extern void execute_14(char*, char *);
+IKI_DLLESPEC extern void execute_15(char*, char *);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_12(char*, char *);
+IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[7] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_11, (funcp)execute_12, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 7;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc",  (void **)funcTab, 7);
+	iki_vhdl_file_variable_register(dp + 2864);
+	iki_vhdl_file_variable_register(dp + 2920);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc");
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_sv_type_file_path_name("xsim.dir/tb_ShiftRegister_v1_behav/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/tb_ShiftRegister_v1_behav/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/tb_ShiftRegister_v1_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.win64.obj b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.win64.obj
new file mode 100644
index 0000000..0a524ac
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.win64.obj differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/.xsim_webtallk.info b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/.xsim_webtallk.info
new file mode 100644
index 0000000..b228b02
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/.xsim_webtallk.info
@@ -0,0 +1,5 @@
+1741012152
+1741012195
+5
+1
+b6c8e7e1e5944b109219f67e64ef5d5f
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.html b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.html
new file mode 100644
index 0000000..6a1fd81
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.html
@@ -0,0 +1,53 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
+  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar  3 15:29:55 2025</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2020.2 (64-bit)</TD>
+  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>b6c8e7e1e5944b109219f67e64ef5d5f</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
+  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
+  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
+  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>command=xsim</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>iteration=0</TD>
+    <TD>runtime=110 ns</TD>
+    <TD>simulation_memory=8996_KB</TD>
+    <TD>simulation_time=0.00_sec</TD>
+</TR><TR ALIGN='LEFT'>    <TD>trace_waveform=true</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+</BODY>
+</HTML>
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.wdm
new file mode 100644
index 0000000..0410530
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.wdm
@@ -0,0 +1,38 @@
+version = "1.0";
+clients =
+(
+    { client_name = "project"; 
+        rules = ( 
+            { 
+                context="software_version_and_target_device";
+                xml_map="software_version_and_target_device";
+                html_map="software_version_and_target_device";
+                html_format="UserEnvStyle";
+            },
+            { 
+                context="user_environment";
+                xml_map="user_environment";
+                html_map="user_environment";
+                html_format="UserEnvStyle";
+            }
+        );
+        },
+
+    { client_name = "xsim"; 
+        rules = ( 
+            { 
+                context="xsim\\command_line_options";
+                xml_map="xsim\\command_line_options";
+                html_map="xsim\\command_line_options";
+                html_format="UnisimStatsStyle";
+            },
+            { 
+                context="xsim\\usage";
+                xml_map="xsim\\usage";
+                html_map="xsim\\usage";
+                html_format="UnisimStatsStyle";
+            }
+        );
+        }
+);
+
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.dbg b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.dbg
new file mode 100644
index 0000000..4a660df
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.dbg differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc
new file mode 100644
index 0000000..d3f6789
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.rlx b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.rlx
new file mode 100644
index 0000000..e973624
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{ 
+    crc :  6635178229023496836  , 
+    ccp_crc :  0  , 
+    cmdline : " -wto b6c8e7e1e5944b109219f67e64ef5d5f --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v1_behav xil_defaultlib.tb_ShiftRegister_v1" , 
+    buildDate : "Nov 18 2020" , 
+    buildTime : "09:47:47" , 
+    linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/tb_ShiftRegister_v1_behav/xsimk.exe\"   \"xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_0.win64.obj\" \"xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.rtti b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.rtti
new file mode 100644
index 0000000..bb961d3
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.rtti differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.svtype b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.svtype
new file mode 100644
index 0000000..afe268b
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.svtype differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.type b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.type
new file mode 100644
index 0000000..95347e8
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.type differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.xdbg b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.xdbg
new file mode 100644
index 0000000..36ff033
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.xdbg differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsimSettings.ini b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsimSettings.ini
new file mode 100644
index 0000000..56ff420
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=75
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsimk.exe b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsimk.exe
new file mode 100644
index 0000000..fc4ab4b
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsimk.exe differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v1.vdb b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v1.vdb
new file mode 100644
index 0000000..95124f2
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v1.vdb differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v1.vdb b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v1.vdb
new file mode 100644
index 0000000..369c505
Binary files /dev/null and b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v1.vdb differ
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..bee1a7e
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,6 @@
+0.7
+2020.2
+Nov 18 2020
+09:47:47
+C:/DESD/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd,1741012279,vhdl,,,,shiftregister_v1,,,,,,,,
+C:/Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v1.vhd,1741012189,vhdl,,,,tb_shiftregister_v1,,,,,,,,
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.ini b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..e8199b2
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd
new file mode 100644
index 0000000..a831d87
--- /dev/null
+++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03.03.2025 15:06:26
+-- Design Name: 
+-- Module Name: ShiftRegister_v1 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ShiftRegister_v1 is
+    Generic (
+        SR_DEPTH : POSITIVE := 4;
+        SR_INIT : STD_LOGIC := '0'
+    );
+    Port (
+        reset : in STD_LOGIC;
+        clk : in STD_LOGIC;
+        din : in STD_LOGIC;
+        dout : out STD_LOGIC
+    );
+end ShiftRegister_v1;
+
+architecture Behavioral of ShiftRegister_v1 is
+    signal sr : STD_LOGIC_VECTOR(SR_DEPTH-1 DOWNTO 0) := (others => '0');
+begin
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            sr <= (others => SR_INIT);
+        elsif rising_edge(clk) then
+            sr <= sr(SR_DEPTH-2 DOWNTO 0) & din;
+        end if;
+    end process;
+    
+    dout <= sr(SR_DEPTH-1);
+
+end Behavioral;
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/gui_handlers.wdf b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/gui_handlers.wdf
new file mode 100644
index 0000000..54abf54
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/gui_handlers.wdf
@@ -0,0 +1,30 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626f61726463686f6f7365725f626f6172645f7461626c65:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f646566696e655f6d6f64756c65735f616e645f737065636966795f696f5f706f727473:37:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:38:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:33:00:00
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+eof:878667394
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/java_command_handlers.wdf b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..573180d
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/java_command_handlers.wdf
@@ -0,0 +1,6 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:31:00:00
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+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:33:00:00
+eof:169294600
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/project.wpc b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/project.wpc
new file mode 100644
index 0000000..6888ede
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:2
+eof:
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/xsim.wdf b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/xsim.wdf
new file mode 100644
index 0000000..50afb2c
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:241934075
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.hw/lab0_shift_register_v2.lpr b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.hw/lab0_shift_register_v2.lpr
new file mode 100644
index 0000000..fd04c85
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.hw/lab0_shift_register_v2.lpr
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.ip_user_files/README.txt b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/compile.bat b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/compile.bat
new file mode 100644
index 0000000..1760ec1
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/compile.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : compile.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Mon Mar 03 15:59:07 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_ShiftRegister_v2_vhdl.prj"
+call xvhdl  --incr --relax -prj tb_ShiftRegister_v2_vhdl.prj -log xvhdl.log
+call type xvhdl.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/elaborate.bat b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/elaborate.bat
new file mode 100644
index 0000000..c07e1f2
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/elaborate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : elaborate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Mon Mar 03 15:59:08 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab -wto 9314b9120ade4657994d00a93c65e94d --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v2_behav xil_defaultlib.tb_ShiftRegister_v2 -log elaborate.log"
+call xelab  -wto 9314b9120ade4657994d00a93c65e94d --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v2_behav xil_defaultlib.tb_ShiftRegister_v2 -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/simulate.bat b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/simulate.bat
new file mode 100644
index 0000000..e52f752
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/simulate.bat
@@ -0,0 +1,25 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2020.2 (64-bit)
+REM
+REM Filename    : simulate.bat
+REM Simulator   : Xilinx Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Mon Mar 03 15:59:09 +0100 2025
+REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+REM
+REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim tb_ShiftRegister_v2_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v2} -tclbatch tb_ShiftRegister_v2.tcl -log simulate.log"
+call xsim  tb_ShiftRegister_v2_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v2} -tclbatch tb_ShiftRegister_v2.tcl -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/tb_ShiftRegister_v2_vhdl.prj b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/tb_ShiftRegister_v2_vhdl.prj
new file mode 100644
index 0000000..90823f5
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/tb_ShiftRegister_v2_vhdl.prj
@@ -0,0 +1,7 @@
+# compile vhdl design source files
+vhdl xil_defaultlib  \
+"../../../../lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd" \
+"../../../../../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v2.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/Compile_Options.txt b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/Compile_Options.txt
new file mode 100644
index 0000000..d67b8f5
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/Compile_Options.txt
@@ -0,0 +1 @@
+-wto "9314b9120ade4657994d00a93c65e94d" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_ShiftRegister_v2_behav" "xil_defaultlib.tb_ShiftRegister_v2" -log "elaborate.log" 
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/TempBreakPointFile.txt b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_0.win64.obj b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_0.win64.obj
new file mode 100644
index 0000000..a734a22
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_0.win64.obj differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.c b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.c
new file mode 100644
index 0000000..af85117
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.c
@@ -0,0 +1,112 @@
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                         */
+/*  \   \        Copyright (c) 2003-2020 Xilinx, Inc.                 */
+/*  /   /        All Right Reserved.                                  */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                        */
+/*  \___\/\___\                                                       */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_13(char*, char *);
+IKI_DLLESPEC extern void execute_14(char*, char *);
+IKI_DLLESPEC extern void execute_15(char*, char *);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_12(char*, char *);
+IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[7] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_11, (funcp)execute_12, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 7;
+
+void relocate(char *dp)
+{
+	iki_relocate(dp, "xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc",  (void **)funcTab, 7);
+	iki_vhdl_file_variable_register(dp + 2888);
+	iki_vhdl_file_variable_register(dp + 2944);
+
+
+	/*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+	iki_sensitize(dp, "xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+		iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc");
+	// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+	iki_execute_processes();
+
+	// Schedule resolution functions for the multiply driven Verilog nets that have strength
+	// Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+    iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_sv_type_file_path_name("xsim.dir/tb_ShiftRegister_v2_behav/xsim.svtype");
+    iki_set_crvs_dump_file_path_name("xsim.dir/tb_ShiftRegister_v2_behav/xsim.crvsdump");
+    void* design_handle = iki_create_design("xsim.dir/tb_ShiftRegister_v2_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+     iki_set_rc_trial_count(100);
+    (void) design_handle;
+    return iki_simulate_design();
+}
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.win64.obj b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.win64.obj
new file mode 100644
index 0000000..d6fb64c
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.win64.obj differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/.xsim_webtallk.info b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/.xsim_webtallk.info
new file mode 100644
index 0000000..2ea83f8
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/.xsim_webtallk.info
@@ -0,0 +1,5 @@
+1741013839
+1741013945
+5
+1
+9314b9120ade4657994d00a93c65e94d
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.html b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.html
new file mode 100644
index 0000000..1764b4d
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.html
@@ -0,0 +1,53 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
+  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar  3 15:59:05 2025</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2020.2 (64-bit)</TD>
+  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>9314b9120ade4657994d00a93c65e94d</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
+  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
+  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
+  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
+<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
+  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
+  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
+</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
+  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>command=xsim</TD>
+</TR>   </TABLE>
+   </TD></TR>
+   <TR><TD>
+   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'>    <TD>iteration=1</TD>
+    <TD>runtime=1 us</TD>
+    <TD>simulation_memory=8980_KB</TD>
+    <TD>simulation_time=0.03_sec</TD>
+</TR><TR ALIGN='LEFT'>    <TD>trace_waveform=true</TD>
+</TR>   </TABLE>
+   </TD></TR>
+  </TABLE><BR>
+</BODY>
+</HTML>
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.wdm
new file mode 100644
index 0000000..0410530
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.wdm
@@ -0,0 +1,38 @@
+version = "1.0";
+clients =
+(
+    { client_name = "project"; 
+        rules = ( 
+            { 
+                context="software_version_and_target_device";
+                xml_map="software_version_and_target_device";
+                html_map="software_version_and_target_device";
+                html_format="UserEnvStyle";
+            },
+            { 
+                context="user_environment";
+                xml_map="user_environment";
+                html_map="user_environment";
+                html_format="UserEnvStyle";
+            }
+        );
+        },
+
+    { client_name = "xsim"; 
+        rules = ( 
+            { 
+                context="xsim\\command_line_options";
+                xml_map="xsim\\command_line_options";
+                html_map="xsim\\command_line_options";
+                html_format="UnisimStatsStyle";
+            },
+            { 
+                context="xsim\\usage";
+                xml_map="xsim\\usage";
+                html_map="xsim\\usage";
+                html_format="UnisimStatsStyle";
+            }
+        );
+        }
+);
+
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.dbg b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.dbg
new file mode 100644
index 0000000..d1bf59f
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.dbg differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc
new file mode 100644
index 0000000..3d7365f
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.rlx b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.rlx
new file mode 100644
index 0000000..848775e
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{ 
+    crc :  11105850378072742046  , 
+    ccp_crc :  0  , 
+    cmdline : " -wto 9314b9120ade4657994d00a93c65e94d --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v2_behav xil_defaultlib.tb_ShiftRegister_v2" , 
+    buildDate : "Nov 18 2020" , 
+    buildTime : "09:47:47" , 
+    linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/tb_ShiftRegister_v2_behav/xsimk.exe\"   \"xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_0.win64.obj\" \"xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 
\ No newline at end of file
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.rtti b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.rtti
new file mode 100644
index 0000000..b51fa7a
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.rtti differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.svtype b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.svtype
new file mode 100644
index 0000000..afe268b
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.svtype differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.type b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.type
new file mode 100644
index 0000000..16518ed
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.type differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.xdbg b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.xdbg
new file mode 100644
index 0000000..9e595c3
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.xdbg differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsimSettings.ini b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsimSettings.ini
new file mode 100644
index 0000000..56ff420
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=75
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsimk.exe b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsimk.exe
new file mode 100644
index 0000000..8de45c9
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsimk.exe differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v2.vdb b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v2.vdb
new file mode 100644
index 0000000..4495240
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v2.vdb differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v2.vdb b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v2.vdb
new file mode 100644
index 0000000..e95895e
Binary files /dev/null and b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v2.vdb differ
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..409bedf
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,6 @@
+0.7
+2020.2
+Nov 18 2020
+09:47:47
+C:/DESD/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd,1741013797,vhdl,,,,shiftregister_v2,,,,,,,,
+C:/Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v2.vhd,1741013934,vhdl,,,,tb_shiftregister_v2,,,,,,,,
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.ini b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..e8199b2
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd
new file mode 100644
index 0000000..8f3810e
--- /dev/null
+++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03.03.2025 15:35:08
+-- Design Name: 
+-- Module Name: ShiftRegister_v2 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ShiftRegister_v2 is
+    Generic (
+        SR_WIDTH : NATURAL := 8;
+        SR_DEPTH : POSITIVE := 4;
+        SR_INIT : STD_LOGIC := '0'
+    );
+    Port (
+        reset : in STD_LOGIC;
+        clk : in STD_LOGIC;
+        din : in STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0);
+        dout : out STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0)
+    );
+end ShiftRegister_v2;
+
+architecture Behavioral of ShiftRegister_v2 is
+    type sr_type is array (SR_DEPTH-1 downto 0) of std_logic_vector(SR_WIDTH-1 downto 0);
+
+    signal sr : sr_type := (others => (others => SR_INIT));
+begin
+
+    process(reset,clk)
+    begin
+        if reset = '1' then
+            sr <= (others => (others => SR_INIT));
+        elsif rising_edge(clk) then
+            sr <= sr(SR_DEPTH-2 downto 0) & din;
+        end if;
+    end process;
+    
+    dout <= sr(SR_DEPTH-1);
+
+end Behavioral;
diff --git a/LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd b/LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd
new file mode 100644
index 0000000..84a5beb
--- /dev/null
+++ b/LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd
@@ -0,0 +1,255 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 19.03.2019 18:55:36
+-- Design Name: 
+-- Module Name: tb_PulseWidthModulator - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+---------- DEFAULT LIBRARY ---------
+library IEEE;
+	use IEEE.STD_LOGIC_1164.all;
+	use IEEE.NUMERIC_STD.ALL;
+--	use IEEE.MATH_REAL.all;
+
+--	use STD.textio.all;
+--	use ieee.std_logic_textio.all;
+		
+------------------------------------
+	
+	
+---------- OTHERS LIBRARY ----------
+-- NONE
+------------------------------------
+
+entity tb_PulseWidthModulator is
+end tb_PulseWidthModulator;
+
+architecture Behavioral of tb_PulseWidthModulator is
+
+	------------------ CONSTANT DECLARATION -------------------------
+
+	--------- Timing -----------
+	constant	CLK_PERIOD 	:	TIME	:= 10 ns;
+	constant	RESET_WND	:	TIME	:= 10*CLK_PERIOD;
+	
+	constant	PWM_WND		:	TIME	:= 100 ns;
+	----------------------------
+
+	--- TB Initialiazzations ---
+	constant	TB_CLK_INIT		:	STD_LOGIC	:= '0';
+	constant	TB_RESET_INIT 	:	STD_LOGIC	:= '1';
+	----------------------------
+	
+	
+	------- DUT Generics -------
+	constant	DUT_BIT_LENGTH	:	INTEGER	RANGE	1 TO 16 := 3;	-- Leds used  over the 16 in Basys3
+		
+	constant	DUT_T_ON_INIT	:	POSITIVE	:= 8;				-- Init of Ton
+	constant	DUT_PERIOD_INIT	:	POSITIVE	:= 16;				-- Init of Periof
+		
+	constant	DUT_PWM_INIT	:	STD_LOGIC  := '1';				-- Init of PWM
+	----------------------------
+	
+	
+	-----------------------------------------------------------------
+
+	------ COMPONENT DECLARATION for the Device Under Test (DUT) ------
+
+	----------- DUT -----------
+	component PulseWidthModulator
+		Generic(
+							
+			BIT_LENGTH	:	INTEGER	RANGE	1 TO 16;	-- Leds used  over the 16 in Basys3
+			
+			T_ON_INIT	:	POSITIVE;					-- Init of Ton
+			PERIOD_INIT	:	POSITIVE;					-- Init of Periof
+			
+			PWM_INIT	:	STD_LOGIC					-- Init of PWM
+		);
+		Port ( 
+		
+			------- Reset/Clock --------
+			reset	:	IN	STD_LOGIC;
+			clk		:	IN	STD_LOGIC;
+			----------------------------		
+
+			-------- Duty Cycle ----------
+			Ton		:	IN	STD_LOGIC_VECTOR(BIT_LENGTH-1 downto 0);	-- clk at PWM = '1'
+			Period	:	IN	STD_LOGIC_VECTOR(BIT_LENGTH-1 downto 0);		-- clk per period of PWM
+			
+			PWM		:	OUT	STD_LOGIC		-- PWM signal
+			----------------------------		
+			
+		);
+	end component;
+
+	----------------------------	
+
+	
+	------------------------------------------------------------------
+
+
+
+
+	--------------------- SIGNALS DECLARATION -----------------------
+
+	
+	------- Clock/Reset  -------
+	signal	reset	:	STD_LOGIC	:= TB_RESET_INIT;
+	signal	clk		:	STD_LOGIC	:= TB_CLK_INIT;
+	----------------------------	
+	
+	
+		
+	-------- Duty Cycle ----------
+	signal	dut_Ton		:	STD_LOGIC_VECTOR(DUT_BIT_LENGTH-1 downto 0);	-- clk at PWM = '1'
+	signal	dut_Period	:	STD_LOGIC_VECTOR(DUT_BIT_LENGTH-1 downto 0);	-- clk per period of PWM
+		
+	signal	dut_PWM		:	STD_LOGIC;									-- PWM signal
+	----------------------------		
+	
+	----------------------------------------------------------------
+
+
+
+
+begin
+
+
+	--------------------- COMPONENTS DUT WRAPPING --------------------
+	
+	----------- DUT ------------
+	dut_PulseWidthModulator	:	PulseWidthModulator
+		Generic Map(
+					
+			BIT_LENGTH		=>	DUT_BIT_LENGTH,
+			
+			T_ON_INIT		=>	DUT_T_ON_INIT,
+			PERIOD_INIT		=>	DUT_PERIOD_INIT,
+			
+			PWM_INIT		=>	DUT_PWM_INIT
+		
+		)
+		Port Map( 
+		
+			------- Reset/Clock --------
+			reset	=> reset,
+			clk		=> clk,
+			----------------------------		
+
+
+			-------- Duty Cycle ----------
+			Ton		=>	dut_Ton,
+			Period	=>	dut_Period,
+			
+			PWM		=>	dut_PWM
+			----------------------------		
+						
+		);
+	----------------------------	
+
+	----------------------------	
+	
+	
+
+	-------------------------------------------------------------------
+
+
+	--------------------- TEST BENCH DATA FLOW  -----------------------
+	
+	---------- clock ----------
+	clk <= not clk after CLK_PERIOD/2;
+	----------------------------
+	
+	-------------------------------------------------------------------	
+	
+	
+	---------------------- TEST BENCH PROCESS -------------------------
+
+	
+	---- Clock Process --------
+	-- clk_wave :process
+	-- begin
+		-- clk <= CLK_PERIOD;
+		-- wait for CLK_PERIOD/2;
+		
+		-- clk <= not clk;
+		-- wait for CLK_PERIOD/2;
+    -- end process;	
+	--------------------------	
+
+	
+	----- Reset Process --------
+	reset_wave :process
+	begin
+		reset <= TB_RESET_INIT;
+		wait for RESET_WND;
+		
+		reset <= not reset;
+		wait;
+    end process;	
+	----------------------------
+	
+	
+   ------ Stimulus process -------
+	
+    stim_proc: process
+    begin		
+		
+		-- waiting the reset wave
+		
+		dut_Ton		<= std_logic_vector(to_unsigned(0,DUT_BIT_LENGTH));
+		dut_Period	<= std_logic_vector(to_unsigned(0,DUT_BIT_LENGTH));
+		wait for RESET_WND;	
+
+			
+		-- Start
+		for I in 0 to 2**DUT_BIT_LENGTH-1 loop
+		
+			dut_Period	<= std_logic_vector(to_unsigned(I,DUT_BIT_LENGTH));		
+		
+			for J in 0 to 2**DUT_BIT_LENGTH-1 loop 
+			
+				dut_Ton		<= std_logic_vector(to_unsigned(J,DUT_BIT_LENGTH));
+		
+			
+				wait for PWM_WND;
+			
+			end loop;
+		end loop;
+
+		
+		dut_Ton		<= std_logic_vector(to_unsigned(2**DUT_BIT_LENGTH-1,DUT_BIT_LENGTH));
+		dut_Period	<= std_logic_vector(to_unsigned(2**DUT_BIT_LENGTH-2,DUT_BIT_LENGTH));
+		wait for PWM_WND;
+		
+        -- Stop
+		wait;
+		
+		
+		--------------------------
+
+      wait;
+    end process;
+	----------------------------
+	
+	-------------------------------------------------------------------
+
+
+
+
+end Behavioral;
diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd
new file mode 100644
index 0000000..fced822
--- /dev/null
+++ b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd
@@ -0,0 +1,181 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 07.03.2019 12:46:18
+-- Design Name:
+-- Module Name: tb_ShiftRegister_v0 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+    use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+    use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity tb_ShiftRegister_v0 is
+end tb_ShiftRegister_v0;
+
+architecture Behavioral of tb_ShiftRegister_v0 is
+
+    ------------------------ Constant Declaration -------------------------
+
+    -- Constant For Test Bench (TB) --
+    constant    RESET_ON    :   STD_LOGIC := '1';
+
+    constant    CLK_PERIOD 	: time := 10 ns;
+    constant    RESET_WND 	: time := 100 ns;
+    ----------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+    ----------------- Device Under Test (DUT) Declaration ----------------
+
+    ------------ DUT v0 --------------
+    COMPONENT   ShiftRegister_v0
+        Port (
+
+            ---------- Reset/Clock ----------
+            reset   :   IN  STD_LOGIC;
+            clk     :   IN  STD_LOGIC;
+            ---------------------------------
+
+            ------------- Data --------------
+            din   :   IN    STD_LOGIC;
+            dout  :   OUT   STD_LOGIC
+            ---------------------------------
+
+        );
+    END COMPONENT;
+    ----------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+
+    ------------------------- Signal Declaration -------------------------
+
+    ---------- Reset/Clock ----------
+    signal  reset   :   STD_LOGIC := RESET_ON;
+    signal  clk     :   STD_LOGIC := '1';
+    ---------------------------------
+
+
+    -------- ShiftRegister_v0 -------
+    signal  dut0_din   :   STD_LOGIC := '0';
+    signal  dut0_dout  :   STD_LOGIC;
+    ---------------------------------
+
+    ----------------------------------------------------------------------
+
+
+
+begin
+
+
+
+
+
+
+    ------------------- Device Under Test (DUT) Wrapper ------------------
+
+    ------------ DUT v0 --------------
+    dut0_ShiftRegister_v0   :   ShiftRegister_v0
+        Port Map(
+
+            ---------- Reset/Clock ----------
+            reset  => reset,
+            clk    => clk,
+            ---------------------------------
+
+            ------------- Data --------------
+            din   => dut0_din,
+            dout  => dut0_dout
+            ---------------------------------
+
+        );
+    ----------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+
+
+    -------------------------- Signals Generation -------------------------
+
+
+    ------ TB Clk Generation -------
+
+    clk	<= not clk after CLK_PERIOD/2;
+    ---------------------------------
+
+
+    ----- TB Reset Generation ------
+    reset_wave : process
+    begin
+
+        reset <= '1';
+        wait for RESET_WND;
+
+        reset <= '0';
+        wait;
+
+    end process;
+    ---------------------------------
+
+
+
+    -- TB din pattern Generation ---
+    dut0_din_pattern : process
+    begin
+
+        -- wait the reset window
+        dut0_din <= '0';
+        wait for RESET_WND;
+
+        -- Start
+        dut0_din <= '0';
+        wait for CLK_PERIOD;
+
+        dut0_din <= '1';
+        wait for 4*CLK_PERIOD;
+
+        dut0_din <= '0';
+        wait for 8*CLK_PERIOD;
+
+        -- Etc...
+
+        -- Stop
+        wait;
+
+    end process;
+    ---------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+
+end Behavioral;
diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd
new file mode 100644
index 0000000..8ce09ce
--- /dev/null
+++ b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd
@@ -0,0 +1,195 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 07.03.2019 13:27:59
+-- Design Name:
+-- Module Name: tb_ShiftRegister_v1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+    use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+    use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity tb_ShiftRegister_v1 is
+end tb_ShiftRegister_v1;
+
+architecture Behavioral of tb_ShiftRegister_v1 is
+
+    ------------------------ Constant Declaration -------------------------
+
+    -- Constant For Test Bench (TB) --
+    constant    RESET_ON    :   STD_LOGIC := '1';
+
+    constant    CLK_PERIOD 	: time := 10 ns;
+    constant    RESET_WND 	: time := 100 ns;
+    ----------------------------------
+
+    ------ Constant For DUT v0 ------
+    constant    DUT1_SR_DEPTH   :   POSITIVE    := 4;
+    constant    DUT1_SR_INIT    :   STD_LOGIC   := '0';
+    ----------------------------------
+
+    ----------------------------------------------------------------------
+
+
+    ----------------- Device Under Test (DUT) Declaration ----------------
+
+    ------------ DUT v1 --------------
+    COMPONENT   ShiftRegister_v1
+        Generic(
+            SR_DEPTH   :   POSITIVE;
+            SR_INIT    :   STD_LOGIC
+        );
+        Port (
+
+            ---------- Reset/Clock ----------
+            reset   :   IN  STD_LOGIC;
+            clk     :   IN  STD_LOGIC;
+            ---------------------------------
+
+            ------------- Data --------------
+            din   :   IN    STD_LOGIC;
+            dout  :   OUT   STD_LOGIC
+            ---------------------------------
+
+        );
+    END COMPONENT;
+    ----------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+
+    ------------------------- Signal Declaration -------------------------
+
+    ---------- Reset/Clock ----------
+    signal  reset   :   STD_LOGIC := RESET_ON;
+    signal  clk     :   STD_LOGIC := '1';
+    ---------------------------------
+
+
+    -------- ShiftRegister_v1 -------
+    signal  dut1_din   :   STD_LOGIC := '0';
+    signal  dut1_dout  :   STD_LOGIC;
+    ---------------------------------
+
+    ----------------------------------------------------------------------
+
+
+
+begin
+
+
+
+
+
+
+    ------------------- Device Under Test (DUT) Wrapper ------------------
+
+    ------------ DUT v1 --------------
+    dut1_ShiftRegister_v1   :   ShiftRegister_v1
+
+        Generic Map(
+            SR_DEPTH   => DUT1_SR_DEPTH,
+            SR_INIT    => DUT1_SR_INIT
+        )
+        Port Map(
+
+            ---------- Reset/Clock ----------
+            reset  => reset,
+            clk    => clk,
+            ---------------------------------
+
+            ------------- Data --------------
+            din   => dut1_din,
+            dout  => dut1_dout
+            ---------------------------------
+
+        );
+    ----------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+
+
+    -------------------------- Signals Generation -------------------------
+
+
+    ------ TB Clk Generation -------
+
+	clk	<= not clk after CLK_PERIOD/2;
+    ---------------------------------
+
+
+    ----- TB Reset Generation ------
+    reset_wave : process
+    begin
+
+        reset <= '1';
+        wait for RESET_WND;
+
+        reset <= '0';
+        wait;
+
+    end process;
+    ---------------------------------
+
+
+
+    -- TB din pattern Generation ---
+    dut1_din_pattern : process
+    begin
+
+        -- wait the reset window
+        dut1_din <= '0';
+        wait for RESET_WND;
+
+
+        -- Start
+        dut1_din <= '0';
+        wait for CLK_PERIOD;
+
+        dut1_din <= '1';
+        wait for 4*CLK_PERIOD;
+
+        dut1_din <= '0';
+        wait for 8*CLK_PERIOD;
+
+        -- Etc...
+
+        -- Stop
+        wait;
+
+    end process;
+    ---------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+
+end Behavioral;
diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd
new file mode 100644
index 0000000..bc50b5b
--- /dev/null
+++ b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd
@@ -0,0 +1,198 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 07.03.2019 16:39:28
+-- Design Name:
+-- Module Name: tb_ShiftRegister_v2 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+
+library IEEE;
+    use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+    use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity tb_ShiftRegister_v2 is
+end tb_ShiftRegister_v2;
+
+architecture Behavioral of tb_ShiftRegister_v2 is
+
+    ------------------------ Constant Declaration -------------------------
+
+    -- Constant For Test Bench (TB) --
+    constant    RESET_ON    :   STD_LOGIC := '1';
+
+    constant    CLK_PERIOD 	: time := 10 ns;
+    constant    RESET_WND 	: time := 100 ns;
+    ----------------------------------
+
+    ------ Constant For DUT v2 ------
+    constant    DUT2_SR_WIDTH   :   NATURAL    := 8;
+    constant    DUT2_SR_DEPTH   :   POSITIVE   := 4;
+    constant    DUT2_SR_INIT    :   STD_LOGIC    := '0';
+    ----------------------------------
+
+    ----------------------------------------------------------------------
+
+
+    ----------------- Device Under Test (DUT) Declaration ----------------
+
+    ------------ DUT v2 --------------
+    COMPONENT   ShiftRegister_v2
+        Generic(
+            SR_WIDTH   :   NATURAL   := 7;
+            SR_DEPTH   :   POSITIVE  := 4;
+            SR_INIT    :   STD_LOGIC   := '0'
+        );
+        Port (
+
+            ---------- Reset/Clock ----------
+            reset   :   IN  STD_LOGIC;
+            clk     :   IN  STD_LOGIC;
+            ---------------------------------
+
+            ------------- Data --------------
+            din   :   IN    STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0);
+            dout  :   OUT   STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0)
+            ---------------------------------
+
+        );
+    END COMPONENT;
+    ----------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+
+    ------------------------- Signal Declaration -------------------------
+
+    ---------- Reset/Clock ----------
+    signal  reset   :   STD_LOGIC := RESET_ON;
+    signal  clk     :   STD_LOGIC := '1';
+    ---------------------------------
+
+
+    -------- ShiftRegister_v2 -------
+    signal  dut2_din   :   STD_LOGIC_VECTOR(DUT2_SR_WIDTH-1 downto 0) := (Others => '0');
+    signal  dut2_dout  :   STD_LOGIC_VECTOR(DUT2_SR_WIDTH-1 downto 0);
+    ---------------------------------
+
+    ----------------------------------------------------------------------
+
+
+
+begin
+
+
+
+
+
+
+    ------------------- Device Under Test (DUT) Wrapper ------------------
+
+    ------------ DUT v2 --------------
+    dut2_ShiftRegister_v2   :   ShiftRegister_v2
+
+        Generic Map(
+            SR_WIDTH   => DUT2_SR_WIDTH,
+            SR_DEPTH   => DUT2_SR_DEPTH,
+            SR_INIT    => DUT2_SR_INIT
+        )
+        Port Map(
+
+            ---------- Reset/Clock ----------
+            reset  => reset,
+            clk    => clk,
+            ---------------------------------
+
+            ------------- Data --------------
+            din   => dut2_din,
+            dout  => dut2_dout
+            ---------------------------------
+
+        );
+    ----------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+
+
+    -------------------------- Signals Generation -------------------------
+
+
+    ------ TB Clk Generation -------
+
+    clk	<= not clk after CLK_PERIOD/2;
+    ---------------------------------
+
+
+    ----- TB Reset Generation ------
+    reset_wave : process
+    begin
+
+        reset <= '1';
+        wait for RESET_WND;
+
+        reset <= '0';
+        wait;
+
+    end process;
+    ---------------------------------
+
+
+
+    -- TB din pattern Generation ---
+    dut2_din_pattern : process
+    begin
+
+        -- wait the reset window
+        dut2_din <= (Others => '0');
+        wait for RESET_WND;
+
+        -- Start
+        dut2_din <= (Others => '0');
+        wait for CLK_PERIOD;
+
+        dut2_din <= (Others => '1');
+        wait for 4*CLK_PERIOD;
+
+        dut2_din <= (Others => '0');
+        wait for 8*CLK_PERIOD;
+
+        -- Etc...
+
+        -- Stop
+        wait;
+
+    end process;
+    ---------------------------------
+
+
+    ----------------------------------------------------------------------
+
+
+
+end Behavioral;
diff --git a/LAB1/lab1_kit_car b/LAB1/lab1_kit_car
new file mode 160000
index 0000000..ec3447b
--- /dev/null
+++ b/LAB1/lab1_kit_car
@@ -0,0 +1 @@
+Subproject commit ec3447bd8cd0d2d809c93a686076bfcfaff174af