From a73750948cb5d1a6f55e53dc49c19d1724df28c6 Mon Sep 17 00:00:00 2001 From: Davide Date: Tue, 18 Mar 2025 00:08:53 +0100 Subject: [PATCH] second commit --- .gitignore | 66 +++++ .../wt/gui_handlers.wdf | 34 +++ .../wt/java_command_handlers.wdf | 10 + .../wt/project.wpc | 3 + .../wt/xsim.wdf | 4 + .../lab0_pulse_width_modulator.lpr | 6 + .../README.txt | 1 + .../sim_1/behav/xsim/compile.bat | 26 ++ .../sim_1/behav/xsim/elaborate.bat | 25 ++ .../sim_1/behav/xsim/simulate.bat | 25 ++ .../xsim/tb_PulseWidthModulator_vhdl.prj | 7 + .../Compile_Options.txt | 1 + .../TempBreakPointFile.txt | 1 + .../obj/xsim_0.win64.obj | Bin 0 -> 9539 bytes .../tb_PulseWidthModulator_behav/obj/xsim_1.c | 112 ++++++++ .../obj/xsim_1.win64.obj | Bin 0 -> 2750 bytes .../webtalk/.xsim_webtallk.info | 5 + .../webtalk/usage_statistics_ext_xsim.html | 53 ++++ .../tb_PulseWidthModulator_behav/xsim.dbg | Bin 0 -> 4920 bytes .../tb_PulseWidthModulator_behav/xsim.reloc | Bin 0 -> 324 bytes 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.../behav/xsim/shift_register_v0_v0_vhdl.prj | 6 + .../sim_1/behav/xsim/simulate.bat | 25 ++ .../behav/xsim/tb_ShiftRegister_v0_vhdl.prj | 7 + .../Compile_Options.txt | 1 + .../TempBreakPointFile.txt | 1 + .../obj/xsim_0.win64.obj | Bin 0 -> 2334 bytes .../shift_register_v0_v0_behav/obj/xsim_1.c | 109 ++++++++ .../obj/xsim_1.win64.obj | Bin 0 -> 2567 bytes .../webtalk/.xsim_webtallk.info | 5 + .../webtalk/usage_statistics_ext_xsim.html | 63 +++++ .../webtalk/usage_statistics_ext_xsim.wdm | 38 +++ .../shift_register_v0_v0_behav/xsim.dbg | Bin 0 -> 1896 bytes .../shift_register_v0_v0_behav/xsim.reloc | Bin 0 -> 205 bytes .../shift_register_v0_v0_behav/xsim.rlx | 12 + .../shift_register_v0_v0_behav/xsim.rtti | Bin 0 -> 122 bytes .../shift_register_v0_v0_behav/xsim.svtype | Bin 0 -> 12 bytes .../shift_register_v0_v0_behav/xsim.type | Bin 0 -> 6072 bytes .../shift_register_v0_v0_behav/xsim.xdbg | Bin 0 -> 192 bytes .../shift_register_v0_v0_behav/xsimk.exe | Bin 0 -> 63710 bytes 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create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/Compile_Options.txt create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/TempBreakPointFile.txt create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_0.win64.obj create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.c create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.win64.obj create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/.xsim_webtallk.info create mode 100644 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mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.type create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.xdbg create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsimSettings.ini create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsimk.exe create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/shiftregister_v1.vdb create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v1.vdb create mode 100644 LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx create mode 100644 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LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/.xsim_webtallk.info create mode 100644 LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.html create mode 100644 LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.wdm create mode 100644 LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.dbg create mode 100644 LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc create mode 100644 LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.rlx create mode 100644 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LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_shiftregister_v2.vdb create mode 100644 LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx create mode 100644 LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.ini create mode 100644 LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd create mode 100644 LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd create mode 100644 LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd create mode 100644 LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd create mode 100644 LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd create mode 160000 LAB1/lab1_kit_car diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..9167918 --- /dev/null +++ b/.gitignore @@ -0,0 +1,66 @@ +# Vivado-specific files and directories to ignore + +# Vivado temporary files +*.jou +*.log +*.str +*.pb +*.wdb +*.xpr +*.xpa +*.backup.* + +# Simulation and synthesis-generated files +*.bit +*.bin +*.elf +*.mcs +*.mem +*.prm +*.tsi +*.vcd +*.vdi +*.xml +*.tcl +*.ltx +*.xci +*.dcp +*.xdc +*.xsa +*.xise +*.ngc +*.ngd +*.ncd +*.bgn +*.blf +*.unroutes +*.rpx +*.par +*.twr +*.twx +*.ptwx +*.mrp +*.pcf +*.qpf +*.qsf +*.qws + +# Vivado project directories +.sim/ +.cache/ +.hw/ +.hwdbg/ +.ip_user_files/ +.webtalk/ +.xsim/ +.xil/ +.xilinx/ +.xtclsh_history +.fpga_editor.log +.fpga_editor.jou +vivado_pid*.str +vivado*.backup.jou +vivado*.backup.log + +# SDK workspace +.sdk/ diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/gui_handlers.wdf b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..dec3c32 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/gui_handlers.wdf @@ -0,0 +1,34 @@ +version:1 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b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/java_command_handlers.wdf @@ -0,0 +1,10 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65786974617070:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e627265616b:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e616c6c:39:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:35:00:00 +eof:2926609623 diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/project.wpc b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/project.wpc new file mode 100644 index 0000000..9b34209 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/xsim.wdf b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.hw/lab0_pulse_width_modulator.lpr b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.hw/lab0_pulse_width_modulator.lpr new file mode 100644 index 0000000..fd04c85 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.hw/lab0_pulse_width_modulator.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.ip_user_files/README.txt b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/compile.bat b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..c6d2067 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,26 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Fri Mar 07 17:00:35 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +REM compile VHDL design sources +echo "xvhdl --incr --relax -prj tb_PulseWidthModulator_vhdl.prj" +call xvhdl --incr --relax -prj tb_PulseWidthModulator_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/elaborate.bat b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..1809505 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Fri Mar 07 17:00:38 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +REM elaborate design +echo "xelab -wto 5e30cf21c5094cb99e69e33f328f026e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_PulseWidthModulator_behav xil_defaultlib.tb_PulseWidthModulator -log elaborate.log" +call xelab -wto 5e30cf21c5094cb99e69e33f328f026e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_PulseWidthModulator_behav xil_defaultlib.tb_PulseWidthModulator -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/simulate.bat b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..8317726 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/simulate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Fri Mar 07 17:00:41 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +REM simulate design +echo "xsim tb_PulseWidthModulator_behav -key {Behavioral:sim_1:Functional:tb_PulseWidthModulator} -tclbatch tb_PulseWidthModulator.tcl -log simulate.log" +call xsim tb_PulseWidthModulator_behav -key {Behavioral:sim_1:Functional:tb_PulseWidthModulator} -tclbatch tb_PulseWidthModulator.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/tb_PulseWidthModulator_vhdl.prj b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/tb_PulseWidthModulator_vhdl.prj new file mode 100644 index 0000000..91c4bda --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/tb_PulseWidthModulator_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd" \ +"../../../../../../../Users/david/Downloads/tb_PulseWidthModulator.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/Compile_Options.txt b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/Compile_Options.txt new file mode 100644 index 0000000..c92b5bd --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "5e30cf21c5094cb99e69e33f328f026e" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_PulseWidthModulator_behav" "xil_defaultlib.tb_PulseWidthModulator" -log "elaborate.log" diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/TempBreakPointFile.txt b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_0.win64.obj b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000000000000000000000000000000000000..466db14d94aec9499ab6d82274b6cdfbd66c5113 GIT binary patch literal 9539 zcmbVSe{@vUoqzKKh(dj~(n?!wv%BLqEQk|+2x;SXo}G|8?EvE`LiQAy8Ipmd=EpRd z$mpU56DGNNPLe(AiTvT|vOTWr=?~KOxR6m-Mv0jSN+Sw_t-H8(yHI2gdfHvkEwi8R zz3;twlbLvG-y!dQ-uHgL-}}AaU-!)nO{uvGU5_tTl&=b;D9aPEWWvBS^et2rw?k0| zJ}ZfF43$bKvb-sph)R-mKlgbH3gA<`+2z~2x{9f#Pd&ufS**|tHqy7~3zDBK^(j8z z@?{#e7LjUIt(Mi<0Y07>IB4mTzm5z6Q6}n+!R+S8BSCX*vtm z>7h+p?}vH*qUwJQz@hP%{i=VeX3DQ_II1mqp-vq;y57Zn7j~~tvxY$0$C!RS(|r{I z9*P9GuUXSW5ol@BcxWrMwyI;(8b1QDxBNA4J+zMPd7;o%?Su8zH+ zjtx_?)=a6x?_y;7DzUdh=mdh!kY67rNk4yisjvW&w4{2_UE#i3J7?ED>cMQ@^AbqV z5{~N|lYU)n!_Qw`@+wm2oW5mu{?w#8`g(O%FmB4IgWi_!oIcq8|uOO<^lIg-OwoYBo^t9k!~`TWK2^Z z{0Y-{#hGqeR_|kcBV&ysJD4q%UXqyNUAV~1~t9u!-RZ)$YvV+Qi-_uNdRTiJqr#|}91!wg|SiNV0 z)+fV{p!xYU&X|_-`N;rbMeh~o?#~M}!jI;&ubuDx(6#IL8u$5$)mF{eFV*v1Mn&&= zZy$67sd|rTdNPu(&uhGg3a+mD*L(At%Ki_}lptEJhiZ*3jgODekn5ppqdEi6K1rdn zpbI?vX~^|Z9ukkWSB)c3=Eeh7uaM=hAE3q4b&kCkt&VZI_YYV7>c+Ey#(Y7L@e~y@ zLLTHFSRqdjk-zx?y5~}q!gTrhljOc!ijtXZ8BFy64WzQT=TcL+)1{|qZJv4s_gv}? z+{wSam#_MHtH;B5&{L%jEpx&==HNrqf@=bIy3mdWZpIW#@Ai0Ey49033zG4K2Tds9 z@u~+?S+F9~NRf3ReTamY4v}}&u_5v$H4sdH553gf5>kk4hd{F_K(2iBVO$#I->m-JEckkN|k2bxwxiD@k3PkTbxziD)z zX9Q0lXLq0H?}&q+38wpmsIW!s7P=~mbTO&xW4071=ps>5S2@=}dlvgB*v5}89UTBg z9UC>gdOh4o(Ihu69V&I8qp%vOlB<>YRVIv{qPXcplqNM(i52>&NR??W=w{bahg?_l z`3nnkDM}Q&a$=qk)1QAz49F;^JD46o!(HcNd;{9rK@o2BEP1jr>Nz+dKMe3o!Ys3` z=|PXj>T9RbA*hm#)^@kq+>nGgwW|W?838@ifY+Q*oz9wbeorO1ktkVX8L&-Mi9S($ z-s8Yx9F6ms{+y==5_SBQ_35Vur%vY5WGx3oVUVX#bp4tjm_x(&?ER4^5jTl}Z?2q6?7)Y&vqlvfn`5V?@0M;GBq8+XAuhA%R;LUuA0!ixOdn#Op}yrMOI)cc8aTBV1ULz1h5f6r z3oVcFAA5R0(M3Ljd5WfapJ#x^9LgJ`5CJ0<2pvXV^jox7%Y?+b%-0Lc5B4|OofG|| zoO3=4-5IT*1xv?aH~!7sNS~*HHUx$UM$@)tVCpc`6^hJ5rTCGh)U;UoQIBvsCAt)B zMX9BOo=SOY8#_`Dxr}fQe#0rFjBw2sS9*t#MVYB9*gwPjXxC%_jLu>-jh+GqX&M7v zWPg&_X1KR1v#y|6=8wzFpY$l@k7>X+3w$#SC`}Qc%#_%=$3T)6H9; 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+extern int main(int, char**); +IKI_DLLESPEC extern void execute_27(char*, char *); +IKI_DLLESPEC extern void execute_28(char*, char *); +IKI_DLLESPEC extern void execute_29(char*, char *); +IKI_DLLESPEC extern void execute_25(char*, char *); +IKI_DLLESPEC extern void execute_26(char*, char *); +IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[7] = {(funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_25, (funcp)execute_26, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 7; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc", (void **)funcTab, 7); + iki_vhdl_file_variable_register(dp + 3376); + iki_vhdl_file_variable_register(dp + 3432); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_PulseWidthModulator_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_PulseWidthModulator_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_PulseWidthModulator_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.win64.obj b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000000000000000000000000000000000000..5bfb4b2bb6555bfa6dde287a3685c9546c0efe6c GIT binary patch literal 2750 zcmbtVO>7%Q6n-1KDM(l##83Gv3m8afvT;Hh0w*U8#1(B7encv@VzSvhV4qo|A2O{CHdWx z*iFsu_XW6>iMLXI=dH@tA7hp7&4nGB+No_Br?UMZx%Z^3Y+o)F04kS{OKuPQHSG8H zu2i;m$IiX`ql}WoRaGJ~5;6Q)hrl#;6>QtZ|H-$;$ zt=+RY$t$W*kpENKu@_jb7fp#OTWR_+U-ev3J6(61zAfqztMZ!Nnvzx#_v;RL=nw=D zB&Y2F{&7oOZ15!61Nb>nD|VYfLwX*-FW`Z?ANu+jqd6E|94Q%V07l+`{G!&9?hBJNcd$zBn@(Z}=ON5pPXTn2Sx% z7iRUMdD;t?S0`8JX3a)a-{6iIH|MMws|5FBjJvVs;SrR0oDn^V@?nW4Q67=#b(Bi` z1|qV}Lp9}Uh#r+(i1IOsK14|w=HU~R%J=gWeTC==sr@G9zDIOaa#vIC8Y0Rk54$K$ zi4No3RlEYCrzCd-(bEzgMf8kBD4>YdfV)sWE75%@pOc8@^}IwTO1d6~l;aZ7d-8%r zDCBFG!yNjE;@yiiC-;UPj2uv8g=mkImc~#Vt%O2ms-@f%N24n=k!r0Ap5H&Uw|fBV z2Ax4RZ8>O?6nQmlAzfho-oDe{{#ii8Fb?4 zcNi4?j~GEZXUwCdc?^pFKhU$AyF-Th-#}}eGj0t6BuM`k4oMqYv*Duu38SdW8MKRZ zdxi_0UMh0Mjk3hLxX=upw{1Gz05mVE>LmS!EoG>f8ASb}m{i z^>>44Gl}!lkPUTy%`o_^q(zN>EW@14Fm{G{Kf`>QGW~qM%rM_(n4Ju>n_+&=Fux2j ze_>CZk7B3OftZJ}C%g{V$urI1P5LA7NS}0pF)wH^Z_{Jx?HEw4n(H&VSgd77o?S%{ z@pUg2JklHoqYOM_r^fMf;tU^9hsQCGnJt*`0?s--s%zf7&7G#u3^iSi+n8I3Q?PxS zg%+O+7PlCERVu-TEov;ZgZ)PIEiw9+{>2P$_hRI^>zu7~vFcV=BX4+iPQ-Dgn9E~t zJ=~W;Ej;xnh-427;t-i*Fmf08pVK?>&w@Z|wKK7ex|B0G$2M|ky+O@rJGNzs*K Pyv0M|*uG!2olW=$?K#}O literal 0 HcmV?d00001 diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/.xsim_webtallk.info b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..dfa7fe5 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1741361410 +1741805296 +20 +1 +5e30cf21c5094cb99e69e33f328f026e diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/usage_statistics_ext_xsim.html b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..b61b1e7 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version3064766
date_generatedWed Mar 12 19:48:16 2025os_platformWIN64
product_versionXSIM v2020.2 (64-bit)project_id5e30cf21c5094cb99e69e33f328f026e
project_iteration19random_id206ae858-3376-4470-a498-c3cf687aa829
registration_id206ae858-3376-4470-a498-c3cf687aa829route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_name13th Gen Intel(R) Core(TM) i3-1315Ucpu_speed2496 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=2runtime=4 ussimulation_memory=8084_KBsimulation_time=0.08_sec
trace_waveform=true
+

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b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..14238be --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,6 @@ +0.7 +2020.2 +Nov 18 2020 +09:47:47 +C:/DESD/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd,1741363223,vhdl,,,,pulsewidthmodulator,,,,,,,, +C:/Users/david/Downloads/tb_PulseWidthModulator.vhd,1741361906,vhdl,,,,tb_pulsewidthmodulator,,,,,,,, diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.ini b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd new file mode 100644 index 0000000..bd7c9d5 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd @@ -0,0 +1,83 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07.03.2025 15:23:11 +-- Design Name: +-- Module Name: PulseWidthModulator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PulseWidthModulator is + Generic( + BIT_LENGTH : INTEGER RANGE 1 to 16 := 8; + T_ON_INIT : POSITIVE := 64; + PERIOD_INIT : POSITIVE := 128; + PWM_INIT : STD_LOGIC := '0' + ); + Port ( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + + Ton : IN std_logic_vector(BIT_LENGTH-1 downto 0); + Period : IN std_logic_vector(BIT_LENGTH-1 downto 0); + PWM : OUT std_logic + ); + end PulseWidthModulator; + +architecture Behavioral of PulseWidthModulator is + signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0'); + signal pwm_out : std_logic; +begin + + process(clk, reset) + begin + if reset = '1' then + counter <= (others => '0'); + pwm_out <= '0'; -- Assicura PWM spento al reset + elsif rising_edge(clk) then + if counter = unsigned(period) then + counter <= (others => '0'); -- Reset counter + else + counter <= counter + 1; -- Incrementa il counter + end if; + + -- Accendi il PWM all'inizio di ogni ciclo + if counter = 0 then + pwm_out <= '1'; + end if; + + -- Spegni il PWM quando il contatore raggiunge Ton + if counter = unsigned(Ton) then + pwm_out <= '0'; + end if; + end if; + end process; + + PWM <= pwm_out; -- Output PWM + +end Behavioral; + diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/gui_handlers.wdf b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..028a2d6 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/gui_handlers.wdf @@ -0,0 +1,23 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:34:00:00 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b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/java_command_handlers.wdf @@ -0,0 +1,8 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:626f61726473746f7265:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:31:00:00 +eof:3524355110 diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/project.wpc b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/project.wpc new file mode 100644 index 0000000..6888ede --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/synthesis.wdf b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/synthesis.wdf new file mode 100644 index 0000000..2c80ca9 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/synthesis.wdf @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:72746c5f31:00:00 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0000000..50afb2c --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.hw/lab0_shift_register_v0.lpr b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.hw/lab0_shift_register_v0.lpr new file mode 100644 index 0000000..fd04c85 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.hw/lab0_shift_register_v0.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.ip_user_files/README.txt b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/compile.bat b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..455631e --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,26 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Mon Mar 03 14:57:07 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +REM compile VHDL design sources +echo "xvhdl --incr --relax -prj tb_ShiftRegister_v0_vhdl.prj" +call xvhdl --incr --relax -prj tb_ShiftRegister_v0_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/elaborate.bat b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..0984e33 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Mon Mar 03 14:57:09 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +REM elaborate design +echo "xelab -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v0_behav xil_defaultlib.tb_ShiftRegister_v0 -log elaborate.log" +call xelab -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v0_behav xil_defaultlib.tb_ShiftRegister_v0 -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/shift_register_v0_v0_vhdl.prj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/shift_register_v0_v0_vhdl.prj new file mode 100644 index 0000000..ee6a6c7 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/shift_register_v0_v0_vhdl.prj @@ -0,0 +1,6 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../lab_0_shift_register.srcs/sources_1/new/shift_register_v0.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/simulate.bat b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..27960c4 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/simulate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Mon Mar 03 14:57:16 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +REM simulate design +echo "xsim tb_ShiftRegister_v0_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v0} -tclbatch tb_ShiftRegister_v0.tcl -log simulate.log" +call xsim tb_ShiftRegister_v0_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v0} -tclbatch tb_ShiftRegister_v0.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/tb_ShiftRegister_v0_vhdl.prj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/tb_ShiftRegister_v0_vhdl.prj new file mode 100644 index 0000000..22376f4 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/tb_ShiftRegister_v0_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../lab_0_shift_register.srcs/sources_1/new/ShiftRegister_v0.vhd" \ +"../../../../../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v0.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/Compile_Options.txt b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/Compile_Options.txt new file mode 100644 index 0000000..2bfedcd --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "79acb559a79942b0a66a9383c435cb5b" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "shift_register_v0_behav" "xil_defaultlib.shift_register_v0" -log "elaborate.log" diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/TempBreakPointFile.txt b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_0.win64.obj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000000000000000000000000000000000000..77d341219f2d4babe4fff67cf249f70d72e74415 GIT binary patch literal 2334 zcmaJ?QD_uL7@oa5Y&G=Wfd=$%Yx3@2)GVCvrHZZ(H@=aJhB zmr~k_642aBoQPslHrcLr?oB}`2uk!s1Px@uGI`$tDp zC1etrYZ)k&s_XxnM}@Ak-mnegP5k7R;(A>Kx*+Orw_734V~u^~-o9gWQBDTvcqJi~ z4^Ts9)L`9lBXOLL|MQg3hhpCYNR;1u~Lst_?X11+# z85J2h{rm^|R+7=s<>c|u)y}<4S`J;^bBInRld+B!y+N86hA@N6hx2qwI;osmn5hjk zLnWBX^3+6-V+T4ZQ;(px@5C`S_TU=Y@8%1PFL#+0Ir=cVLa#~S7=Q9~=NkZ|Q!1Ze zygyuI#ybh)-Q-jtI5`o%BJ#`_SpL^NOXe@{6SC&$N-cMaOvb{4Lf7o-d~)dGH}`$f zhx{HJyCL>J`5sEAeYBSzx2hU{&=lv(jQ_;=x5n4uQAlF^yKeKd?SorIwZBom<`j2+ zPFI*|kQWGXm~Qi{r8=Q{!uX>&U!`s%j4v|t`6se;?cQy^rmAlF{jJ3tsaSS;Sx^AnEo7Z@xxd?%$yFwj*TrYiHScF z^`3Iev{nmleFxXs?LdYxy&G@KZqf$>bNV*yVOJEZ4R(!?Zb#UM4~39=pa3}v)L?NL zm-`ZEhsE6h!taHQUx8k<&|@HRQv}FX?18Tp(MBMfdmG5srGQ?xq9ZPvcG0ImyR7IJ zF83$UZi^$hne5y)AcrGTeI2Qnc9B5DpYRo>l++L;4XxWE&n1Gzt*N@Xz+K;}w8clZ zv?Aurup=|#<&1gEqBk)v;Ry?X!SL*}5V7tVKl-bpAP_z)6eVt;kcEVYjl>DqQBh~3 z72V^aCLlX1c6tSmpESEj>}W^5cQX!{_$6^Wi!(j&c>f=Q!Ts&I9&uFAShVvJ3^blQ z83r3Pf`P_!AB!&iQk%sSqOBb~Di~-ycd@vB{Za&P(f`G5Q+owtj|ry+i8SFm5TgL* zHs%^r4`y{8vsVb6VQ0mwOUyQtLe?mrnosc=ja{ov+gakTt2%rnujSLlk?OkYe7;6F zdr85Wb;KOdp4_-(t}#2oYR!z(7CjR z|D3hZ@L(pVXv11TS4!D41vRG>)gd*n>DtgnRZcDG%CMR%YyT%L=@~`zo-caxGb05x zpG_Fv%HJ2Mu(`P-=lAhOCpm|s;XDD0B7S1SI=8Q(P zik2?xn$qE-c9PXJG_G{0hqTkt^ng+-4=Al0P23amR_GkaY0-B{(?v-UwEn&pC0 +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[4] = {(funcp)execute_8, (funcp)execute_9, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 4; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/shift_register_v0_behav/xsim.reloc", (void **)funcTab, 4); + iki_vhdl_file_variable_register(dp + 2688); + iki_vhdl_file_variable_register(dp + 2744); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/shift_register_v0_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/shift_register_v0_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/shift_register_v0_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/shift_register_v0_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/shift_register_v0_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.win64.obj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000000000000000000000000000000000000..f0f536facae86fdd37eab8cb651a79401b869c55 GIT binary patch literal 2567 zcma)7&2Jk;6n`7LDIhEm;-h?(1q`Gj**Iy40w*U8iYo#NA0m}nF`A;EYjjEmT*9k2m+}WPT|OfLl683sOG(yU1!X;C{LRAe)D^8-hAwv zS^ulkK(clUU`(MrIFfgy!djIqfN^Yp<#hi^G&ZcPIle1hBhE&AWdz_LuSqgxSUYg4 zajcp9>up#$aH8Razhn4kn9r0ltdyP3a2&0BIaym8TZU5EX%5Gg&?zzQPO`p-u}^W6 zGwCR8%V=(8@~xCV{;;z1_gJNOdw!oXEbro(0aSLMAk$a6vU_d&A>^*Tp|~UL?_s}x zbiJ~3IClAypH&8PgmPqQolZN|yq9{nE4`yTly-g})%N@zVVr$jnZkKA=^_eqW~V;r zB>tW(R(e;8W!XahpqMaH46`61%+Nf{ggrzsLv?$4r=Xv9}&gop*rBG zik?wii27NDzC=wc%){5H_1JF)=oX^qmG`>=_XDD{irX7-KOv&^9BOXy4oxb+cSdHi_ zXfI{a9PL#jd*G$nHAmM+Bf64$tg|i}stA#}+XtvwRE=!P@sLPFRk$lvm<2YB;O_1v zlyMQ8iUCa1YTziU8qEZ*piiS}NHgY3PDyhX)fBzo$6~(XBS_~g8#SHMv6wG7J&d_~ ztk8VDX>`u|?KnY#%$NI=ilH+b7W35}MOV(EcbmS@uuy%Hs1vu!3Y%)Z6?z}JRKEbU zFKW704$;yIH8V|gBAR(S?V{DpW`_A9!+bl$FqVD|qU|KlFGDfZ`7^`d!!Zy&`|BCz zVuo=u%;y>A#(+uJb2GzypJ9F+V*bFM{?f&6w+k^3VUx{-FX3>-q5uE@ literal 0 HcmV?d00001 diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/.xsim_webtallk.info b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..fe7ee2b --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1741009327 +0 +2 +1 +79acb559a79942b0a66a9383c435cb5b diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.html b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..8b83675 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,63 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version3064766
date_generatedMon Mar 3 14:42:07 2025os_platformWIN64
product_versionXSIM v2020.2 (64-bit)project_id79acb559a79942b0a66a9383c435cb5b
project_iteration1random_id206ae858-3376-4470-a498-c3cf687aa829
registration_id206ae858-3376-4470-a498-c3cf687aa829route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_name13th Gen Intel(R) Core(TM) i3-1315Ucpu_speed2496 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + + + + + + + + +
command_line_options
command=xelabdebug=typicaldpi_used=falsefile_counter=5
gendll=falsehwcosim=falsesdfmodeling=falsevhdl2008=false
+
+ + + + + + + + + + +
usage
compiler_memory=58596_KBcompiler_time=0.45_secsimulation_image_code=62 KBsimulation_image_data=2 KB
total_instances=4total_nets=0total_processes=2xilinx_hdl_libraries_used=secureip
+

+ + diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + 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b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 14328939556394471054 , + ccp_crc : 0 , + cmdline : " -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot shift_register_v0_behav xil_defaultlib.shift_register_v0" , + buildDate : "Nov 18 2020" , + buildTime : "09:47:47" , + linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/shift_register_v0_behav/xsimk.exe\" \"xsim.dir/shift_register_v0_behav/obj/xsim_0.win64.obj\" \"xsim.dir/shift_register_v0_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git 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zr=o-RA?vNOxD$6vaC@h{Qa)UZfvDB0sPgkcJeTtoaONQ9=6VoDUC$2Y_3ZJieqx|M zrx!85=rHVHzXrS-Et<)K8>yqsITD7R-K~mU1xfi|>DGC_R|X zRCPyv`zT@zZXua;F4vdN9QSz(=Afw$59QFK&njX@vW4u>G2Q4tW-y~@WJXOxkMFC% zy)0`OhMw0CruQ39#4~+*VYE-*Qz7iBNoc7MTGpqO^Q^I2PtcSKhDi;?FsQE^aptGR OYi5gAvehQU*na@(3Q^zy literal 0 HcmV?d00001 diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.c b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.c new file mode 100644 index 0000000..962e137 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.c @@ -0,0 +1,112 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_13(char*, char *); +IKI_DLLESPEC extern void execute_14(char*, char *); +IKI_DLLESPEC extern void execute_15(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_12(char*, char *); +IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[7] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_11, (funcp)execute_12, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 7; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc", (void **)funcTab, 7); + iki_vhdl_file_variable_register(dp + 2864); + iki_vhdl_file_variable_register(dp + 2920); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_ShiftRegister_v0_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_ShiftRegister_v0_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_ShiftRegister_v0_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.win64.obj b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000000000000000000000000000000000000..148fbb1a91cc123af779bb178d5ea7cdbd7b0fb8 GIT binary patch literal 2718 zcmbtV-D_M$6hAk+O%+`f@uPm#tFAS%$;~EBL-1*nMzX~!u`Q<1;^gkVlk6n--Yoad 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XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version3064766
date_generatedMon Mar 3 15:05:20 2025os_platformWIN64
product_versionXSIM v2020.2 (64-bit)project_id79acb559a79942b0a66a9383c435cb5b
project_iteration2random_id206ae858-3376-4470-a498-c3cf687aa829
registration_id206ae858-3376-4470-a498-c3cf687aa829route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_name13th Gen Intel(R) Core(TM) i3-1315Ucpu_speed2496 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=1runtime=1 ussimulation_memory=8980_KBsimulation_time=0.01_sec
trace_waveform=true
+

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b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..bc38957 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,7 @@ +0.7 +2020.2 +Nov 18 2020 +09:47:47 +C:/DESD/LAB0/lab_0_shift_register/lab_0_shift_register.srcs/sources_1/new/ShiftRegister_v0.vhd,1741010016,vhdl,,,,shiftregister_v0,,,,,,,, +C:/DESD/LAB0/lab_0_shift_register/lab_0_shift_register.srcs/sources_1/new/shift_register_v0.vhd,1741009257,vhdl,,,,shift_register_v0,,,,,,,, +C:/Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v0.vhd,1741009565,vhdl,,,,tb_shiftregister_v0,,,,,,,, diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.ini b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd new file mode 100644 index 0000000..af89a1a --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd @@ -0,0 +1,56 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03.03.2025 14:49:43 +-- Design Name: +-- Module Name: ShiftRegister_v0 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftRegister_v0 is + Port ( reset : in STD_LOGIC; + clk : in STD_LOGIC; + din : in STD_LOGIC; + dout : out STD_LOGIC); +end ShiftRegister_v0; + +architecture Behavioral of ShiftRegister_v0 is + signal sr : std_logic := '0'; +begin + + process(clk, reset) + begin + if reset = '1' then + sr <= '0'; + elsif rising_edge(clk) then + sr <= din; + end if; + end process; + + dout <= sr; + +end Behavioral; diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd new file mode 100644 index 0000000..d2bff85 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd @@ -0,0 +1,56 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03.03.2025 14:21:16 +-- Design Name: +-- Module Name: shift_register_v0 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity shift_register_v0 is + Port ( reset : in STD_LOGIC; + clk : in STD_LOGIC; + din : in STD_LOGIC; + dout : out STD_LOGIC); +end shift_register_v0; + +architecture Behavioral of shift_register_v0 is + signal sr : std_logic := '0'; +begin + + process(clk, reset) + begin + if reset = '1' then + sr <= '0'; + elsif rising_edge(clk) then + sr <= din; + end if; + end process; + + dout <= sr; + +end Behavioral; diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/gui_handlers.wdf b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..c159b14 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/gui_handlers.wdf @@ -0,0 +1,26 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:31:00:00 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+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:39:00:00 +eof:1119620138 diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/project.wpc b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/project.wpc new file mode 100644 index 0000000..6888ede --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/xsim.wdf b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.hw/lab0_shift_register_v1.lpr b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.hw/lab0_shift_register_v1.lpr new file mode 100644 index 0000000..fd04c85 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.hw/lab0_shift_register_v1.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.ip_user_files/README.txt b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/compile.bat b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..9ea3eb2 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,26 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Mon Mar 03 15:31:33 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +REM compile VHDL design sources +echo "xvhdl --incr --relax -prj tb_ShiftRegister_v1_vhdl.prj" +call xvhdl --incr --relax -prj tb_ShiftRegister_v1_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/elaborate.bat b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..7dce7f9 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Mon Mar 03 15:31:34 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +REM elaborate design +echo "xelab -wto b6c8e7e1e5944b109219f67e64ef5d5f --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v1_behav xil_defaultlib.tb_ShiftRegister_v1 -log elaborate.log" +call xelab -wto b6c8e7e1e5944b109219f67e64ef5d5f --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v1_behav xil_defaultlib.tb_ShiftRegister_v1 -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/simulate.bat b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..77eaff5 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/simulate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Mon Mar 03 15:31:36 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +REM simulate design +echo "xsim tb_ShiftRegister_v1_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v1} -tclbatch tb_ShiftRegister_v1.tcl -log simulate.log" +call xsim tb_ShiftRegister_v1_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v1} -tclbatch tb_ShiftRegister_v1.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/tb_ShiftRegister_v1_vhdl.prj b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/tb_ShiftRegister_v1_vhdl.prj new file mode 100644 index 0000000..3519c04 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/tb_ShiftRegister_v1_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd" \ +"../../../../../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v1.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/Compile_Options.txt b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/Compile_Options.txt new file mode 100644 index 0000000..e771500 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "b6c8e7e1e5944b109219f67e64ef5d5f" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_ShiftRegister_v1_behav" "xil_defaultlib.tb_ShiftRegister_v1" -log "elaborate.log" diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/TempBreakPointFile.txt b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_0.win64.obj b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000000000000000000000000000000000000..324314474a7502298d6de7a38e2e6cdfaa1c6f7c GIT binary patch literal 4101 zcmbVPeQX=$8Gp}q6VsMDV=&6-R>M3k6IErWDNUqI+zqFCqq&tO($o^67uPuwQ^zr} zQ`~*9ganhz&6$x<)r}%Wnl?b%)}mFF-EEa=SSW1kvVbU5`vdJmYSmVJ{6othgx~wV zcjt5BF=?-qdw=&lzvuIP?tB?6tRrl#-$2MWI3i?wPRr*^%(ik9A^*VsT(c0iVe^yd z!1lp-E-pm&b>2YPgQSTUjl@G_|A(SCSM`A#e;`U1=@g*z|( zcsHGVRsJd=CB=6-8l%Pbr#g`Q$w4qXo|D`g2Xs^46>{hO?XUDEhIs`m#n)Oavzd@nZZ@y<*KPBOb<7*hSC z%beyO-^OUIq2-$GESU)hh8eHb=DB3wbAP((3SHMP)5+IZ{D&VwY07@3PwC}ZOdT@^p6z%hMC;c)!Yaz8daQf#OUJrDk~QuDcy#S ztXzx~e}4l58_{o4{bNPHtk`8yeX*zblPxE?$B%pT8@!4JM8t!wMWB-l%puj^vmMf@ z*ZiymrC&LqsB|U3)9Bkzr>^CB5r3=fBqd^IOpV<^V{gYqm)AZ1oyz?+h4IWUa7udN zU9_JT=e%s2T&!YK${w@;@enDm9?#!X2WX|jcf6m>3aRnb4dxuP?OJ)C z7SArRJ7WtUtI9EgRNq=GWKf$M$KFbdN7?b2F)Kgg`ZMzdiN!RfWe-mMYCAO_k;?Oo zbWu2QHE?pA>&tBJs9xaNupxK8fgJf3&*WL7ji=_>W~OcB`;wXOW(*fX%^hP$Q#?v= zYo+{h!;}+v%&vR@cBR7f;$>7GMIl$-V?L|^zx&?-PKf{$9d$i9!(7cdU7d8eLT?-8 z`igKRA4dkY_AasZ?zU6srk3UPs_LJ{M^l7Ed}03v*9}>LN*~u7wHGu2;?D; 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+extern int main(int, char**); +IKI_DLLESPEC extern void execute_13(char*, char *); +IKI_DLLESPEC extern void execute_14(char*, char *); +IKI_DLLESPEC extern void execute_15(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_12(char*, char *); +IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[7] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_11, (funcp)execute_12, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 7; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc", (void **)funcTab, 7); + iki_vhdl_file_variable_register(dp + 2864); + iki_vhdl_file_variable_register(dp + 2920); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_ShiftRegister_v1_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_ShiftRegister_v1_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_ShiftRegister_v1_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.win64.obj b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000000000000000000000000000000000000..0a524ace61435c0108914d7b37fab0ec11c8c16b GIT binary patch literal 2718 zcmbtV-D_M$6hAk+Z53S<@uPm#tFAS%$<1z>hTzjCjbw{eVk@T5;^gkVlk6n--Yoad zuG>6lAtEd#&<8;uq=@<=g5X>8A_XHpRIpEZ6Mgi-zd)qxIWxO=XT1>u9+)$~`JFRo zzRt|}9~}ddn@0dnDU=6C^0ri1tC9sUjwPSh?Z>gQVQIzjUFjNr6~tFY0DkZJQRE7& z+;(b7Vz?a$uffu7Cms%X7d=12c&1cfsp7PU{YKFt$eCU=ZmHrlhW$$D@-h0I#I=$< zh=u$nr&Tjm6-0ZPcuSRcE>^ey9IbZl%%rvqnF?PK}9foC_|Rk;j~eWd#Q7$+S&hu!p`lYx;A%eMCkY;o|H9qu`X8S1->Q{$z#?kvl_3vtx4q)^I+2hf!<*V zVFHKkm$c;728ToYdvPoAn_;8BsKbsE@(?IttfM(NIzLjfRuJbc$j=)!*}l*=ioZY# zh3d;#C|9X&V|lb!kKvts2JzzAv#;8t?b#VNGd=O1h)z#UB|aeKZg0%_N- z+HZ(xad~2SX4-DVo9o<@WA=Kw>N3E@IAtK*A z)KZSJ>?y@XsGnBoL)0|GJbZ#$_q~~-uMj<}tly;EcZg0X?pDfukBH`zhdtD`LdS6J zI$iTKwIb3l0e<0=` zFoJZ>nng|P7>N1))3cg8V20+~PkWrR?hXR!PAF>1V8IhMJiox+j`>t>462GaDJ^gADWa5W`siG>Eo) zaef@~p~i0+2A`Ew^ysHD%()EXW|;Rg%%>^SpU;;W=GzRjn_>1c%r6<{*CFOFZ0Yb3QO8!Uhu?f~B`(K(*?A!02MJmKzJVh9K^JEJnw{ zD1)AfSLc2c{qX_yc#`mhxspi{a<;|eO`|t&bFV24N5fX2OJzsT}wNa6GVo*BUM08W97-6(NADK;Zk26Y;WqASOEi$~IP KgP`Vm8}JWf_ttIz literal 0 HcmV?d00001 diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/.xsim_webtallk.info b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..b228b02 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1741012152 +1741012195 +5 +1 +b6c8e7e1e5944b109219f67e64ef5d5f diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.html b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..6a1fd81 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version3064766
date_generatedMon Mar 3 15:29:55 2025os_platformWIN64
product_versionXSIM v2020.2 (64-bit)project_idb6c8e7e1e5944b109219f67e64ef5d5f
project_iteration2random_id206ae858-3376-4470-a498-c3cf687aa829
registration_id206ae858-3376-4470-a498-c3cf687aa829route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_name13th Gen Intel(R) Core(TM) i3-1315Ucpu_speed2496 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=0runtime=110 nssimulation_memory=8996_KBsimulation_time=0.00_sec
trace_waveform=true
+

+ + diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.dbg b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.dbg new file mode 100644 index 0000000000000000000000000000000000000000..4a660dfcb25ea932693461869e7b7feed485b9ec GIT binary patch literal 3792 zcmc&%zi%8x6dv<4{0st7P#{^6gZLHC?qNGtpaAENa7yG@_Bk;W413;vs+O0yg58+?*-3HxV zIrm`y0H4J?@(A*f_ZcGP0N#ct1%JCG58VkvK9FAu&Y8f+1V8kZ5Gb+7u=Ut$`UsTO z2h(B;8nnki&YLn8M#r%YafcbVjXeuXtp(R1nCAoVW^ff8ruh&tuK&si&8LX5-q%1| zCx&{DT#Ge51+u<3z+swa5W5}Z9K!Ywu77}QJp?kZ-S2UXnfDlY3bb+NqedFbc%Hr2 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xil_defaultlib.tb_ShiftRegister_v1" , + buildDate : "Nov 18 2020" , + buildTime : "09:47:47" , + linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/tb_ShiftRegister_v1_behav/xsimk.exe\" \"xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_0.win64.obj\" \"xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.rtti b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/xsim.rtti new file mode 100644 index 0000000000000000000000000000000000000000..bb961d339c6153b2e3c96df364def93cfd4be49d GIT binary patch literal 478 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+C:/DESD/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd,1741012279,vhdl,,,,shiftregister_v1,,,,,,,, +C:/Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v1.vhd,1741012189,vhdl,,,,tb_shiftregister_v1,,,,,,,, diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.ini b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd new file mode 100644 index 0000000..a831d87 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd @@ -0,0 +1,62 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03.03.2025 15:06:26 +-- Design Name: +-- Module Name: ShiftRegister_v1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftRegister_v1 is + Generic ( + SR_DEPTH : POSITIVE := 4; + SR_INIT : STD_LOGIC := '0' + ); + Port ( + reset : in STD_LOGIC; + clk : in STD_LOGIC; + din : in STD_LOGIC; + dout : out STD_LOGIC + ); +end ShiftRegister_v1; + +architecture Behavioral of ShiftRegister_v1 is + signal sr : STD_LOGIC_VECTOR(SR_DEPTH-1 DOWNTO 0) := (others => '0'); +begin + + process(clk, reset) + begin + if reset = '1' then + sr <= (others => SR_INIT); + elsif rising_edge(clk) then + sr <= sr(SR_DEPTH-2 DOWNTO 0) & din; + end if; + end process; + + dout <= sr(SR_DEPTH-1); + +end Behavioral; diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/gui_handlers.wdf b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..54abf54 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/gui_handlers.wdf @@ -0,0 +1,30 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00 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b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/java_command_handlers.wdf @@ -0,0 +1,6 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65786974617070:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:33:00:00 +eof:169294600 diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/project.wpc b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/project.wpc new file mode 100644 index 0000000..6888ede --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/xsim.wdf b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.hw/lab0_shift_register_v2.lpr b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.hw/lab0_shift_register_v2.lpr new file mode 100644 index 0000000..fd04c85 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.hw/lab0_shift_register_v2.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.ip_user_files/README.txt b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/compile.bat b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..1760ec1 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,26 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Mon Mar 03 15:59:07 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +REM compile VHDL design sources +echo "xvhdl --incr --relax -prj tb_ShiftRegister_v2_vhdl.prj" +call xvhdl --incr --relax -prj tb_ShiftRegister_v2_vhdl.prj -log xvhdl.log +call type xvhdl.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/elaborate.bat b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..c07e1f2 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Mon Mar 03 15:59:08 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +REM elaborate design +echo "xelab -wto 9314b9120ade4657994d00a93c65e94d --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v2_behav xil_defaultlib.tb_ShiftRegister_v2 -log elaborate.log" +call xelab -wto 9314b9120ade4657994d00a93c65e94d --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v2_behav xil_defaultlib.tb_ShiftRegister_v2 -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/simulate.bat b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..e52f752 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/simulate.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2020.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Mon Mar 03 15:59:09 +0100 2025 +REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +REM +REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +REM simulate design +echo "xsim tb_ShiftRegister_v2_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v2} -tclbatch tb_ShiftRegister_v2.tcl -log simulate.log" +call xsim tb_ShiftRegister_v2_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v2} -tclbatch tb_ShiftRegister_v2.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/tb_ShiftRegister_v2_vhdl.prj b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/tb_ShiftRegister_v2_vhdl.prj new file mode 100644 index 0000000..90823f5 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/tb_ShiftRegister_v2_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd" \ +"../../../../../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v2.vhd" \ + +# Do not sort compile order +nosort diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/Compile_Options.txt b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/Compile_Options.txt new file mode 100644 index 0000000..d67b8f5 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "9314b9120ade4657994d00a93c65e94d" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_ShiftRegister_v2_behav" "xil_defaultlib.tb_ShiftRegister_v2" -log "elaborate.log" diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/TempBreakPointFile.txt b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_0.win64.obj b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000000000000000000000000000000000000..a734a22fe2d719c7e3d610849ea384f5f293be13 GIT binary patch literal 4261 zcmbVPZERat89vu`8fWe54EE7MS-sVWz^Y=WDN7(?zN=H6XlZ1rZECa-+jZ_5Gbb^z z(|LT1X35gr-Z=|WRaK~CK_CrPpawP-yBky1l&syLD=DI7@S}nurAnuD4nlrDceK)hU~!x(5Q_zP}MSMqj&H-fmA&Di(g9dUyl zdv>a`!H7#8&V`l1EvgaZs=?b@jPNdX_>)Ebv?ugO07cc$g*>6NO=m-%_IK1TzSZJ6 z@y-q>4=#LfN1jJo^FhvyT5bg0t$H}tst0>iBOHU5ZdDI=!fVQN;)1Hr!0i1{)B8Wz z&WGL#e}=IM)pIf&;rWKSRwEaLO{acQeK^8Z&xyz`&&lQuTsiMKx&9G#ED{Md&1Kgr zr^z9l!OOF!)kDe?(XN?^(m*jPgVSK}(1`mdh@g%I)iMI<6-$47xxQo1?wx$-S^@28 z(`UGTzBQi<20jeTsRacxuHRa``||*-SsC2T^-f=!8{5Lhxy_t=PUitO?sNcE5B z1r5U4#V#5Ylzx<~C$cZsZquX#iI zAGrQ!uD@%%;X43Ii~jo^`PbGQ#pY|%KUVddW^&I@XM1_xC}5S_jAoIqx_AkaiBF*; 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+extern int main(int, char**); +IKI_DLLESPEC extern void execute_13(char*, char *); +IKI_DLLESPEC extern void execute_14(char*, char *); +IKI_DLLESPEC extern void execute_15(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_12(char*, char *); +IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[7] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_11, (funcp)execute_12, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 7; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc", (void **)funcTab, 7); + iki_vhdl_file_variable_register(dp + 2888); + iki_vhdl_file_variable_register(dp + 2944); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ShiftRegister_v2_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_ShiftRegister_v2_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_ShiftRegister_v2_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_ShiftRegister_v2_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.win64.obj b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000000000000000000000000000000000000..d6fb64ca7924193fb0e5fcae257be7e75c9761bb GIT binary patch literal 2718 zcmbtV&1)n@6n~wW%_=%5;>Y^6wmPnfn{+0#*$_NUvXS)SDsflL!Y)>Nx+|GZx;sO6 z%{ZHb1|q_+1oj~4K^9RjA_(3#7g=z`!wT*xH_@X9{{oR6->aJGsj(vjd{D1`^?R>g zeZ8vkJ~|F0H;)0FmM9OF;4LAsQY8am0!u!x+K*#p!t$!+Il|HWDu}O+0Q}zbqsSFl zy=_&KL~}b7?!fYGD;^Gb7d=12c)C6z23s zEp7DdZBew_SBsUO7K`Kvc6+f{!Uk<5*a%Dl7xoIg+wI~qm$1Tt{=P?5;d8X9K>J<_ zdy#iLmvNCdl%Vl{Nh|R~%k$$YQDv8E{+hVR*ZoBBm^I6+%4<$@O1i{6*mA)~?=XZg zfur_In&MiW!;$^nxS4p3u-;$PQO5~+2$V3!XbwgfMoPvi;=BR*1+6CA7s^KQ7fGQ| zeFY2UD%CA4kM`<{P-KPZjFgqeP#o=qLS|~ExhalDS7;)&T5EoQ2`c4Y7hv6>oMY3L z+as}(+3yJHW`GGJxc0+@X0wPz`T&M$1lWsmN-?41)4|CMQ;hx(P|%z~8Aq@GK=eOg z1nHbHhnm(g5dHn9XEk@o4E494_BdzU9R%nh{oOw%eQ3{yMSt^0(Uddj6zTR13uP~f z+;O8Kv98t{k^8no*$qJJqM|bCXRK+4iYXJ_6UDsNZ(^;O%?$HFhWUDkVXS`|M4P=h zKMwg&r{%=;PU)0FAY=gSQ9ZHC#;Fr5tZONRM%i1`a!DnE+b z+uM-vDDj2A&2{q4MtG6F0Zi%h9x&#Ib>?sSEWI5As#)^_Mi+}Uo!ED(2;$zyqIDdM zGU%DOHSRUgA0JScCkaoOBbe|*&bE2HrS;}5?ly$xsM%`V!MR1a1Sg2OJzsTt`kiwY(JUf8X16T$TJ5l1e!rzM6G|1DC6kR#Sn>-S( L69iSq-GqMtKQY## literal 0 HcmV?d00001 diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/.xsim_webtallk.info b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..2ea83f8 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1741013839 +1741013945 +5 +1 +9314b9120ade4657994d00a93c65e94d diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.html b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..1764b4d --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

    XSIM Usage Report


    + + + + + + + + + + + + + + + + + +
    software_version_and_target_device
    betaFALSEbuild_version3064766
    date_generatedMon Mar 3 15:59:05 2025os_platformWIN64
    product_versionXSIM v2020.2 (64-bit)project_id9314b9120ade4657994d00a93c65e94d
    project_iteration2random_id206ae858-3376-4470-a498-c3cf687aa829
    registration_id206ae858-3376-4470-a498-c3cf687aa829route_designFALSE
    target_devicenot_applicabletarget_familynot_applicable
    target_packagenot_applicabletarget_speednot_applicable
    tool_flowxsim_vivado

    + + + + + + + + +
    user_environment
    cpu_name13th Gen Intel(R) Core(TM) i3-1315Ucpu_speed2496 MHz
    os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
    system_ram8.000 GBtotal_processors1

    + + +
    vivado_usage

    + + + + +
    xsim
    + + + +
    command_line_options
    command=xsim
    +
    + + + + + + + +
    usage
    iteration=1runtime=1 ussimulation_memory=8980_KBsimulation_time=0.03_sec
    trace_waveform=true
    +

    + + diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.wdm b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + 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b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.rlx new file mode 100644 index 0000000..848775e --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v2_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 11105850378072742046 , + ccp_crc : 0 , + cmdline : " -wto 9314b9120ade4657994d00a93c65e94d --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v2_behav xil_defaultlib.tb_ShiftRegister_v2" , + buildDate : "Nov 18 2020" , + buildTime : "09:47:47" , + linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/tb_ShiftRegister_v2_behav/xsimk.exe\" \"xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_0.win64.obj\" \"xsim.dir/tb_ShiftRegister_v2_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel 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Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +---------- DEFAULT LIBRARY --------- +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.NUMERIC_STD.ALL; +-- use IEEE.MATH_REAL.all; + +-- use STD.textio.all; +-- use ieee.std_logic_textio.all; + +------------------------------------ + + +---------- OTHERS LIBRARY ---------- +-- NONE +------------------------------------ + +entity tb_PulseWidthModulator is +end tb_PulseWidthModulator; + +architecture Behavioral of tb_PulseWidthModulator is + + ------------------ CONSTANT DECLARATION ------------------------- + + --------- Timing ----------- + constant CLK_PERIOD : TIME := 10 ns; + constant RESET_WND : TIME := 10*CLK_PERIOD; + + constant PWM_WND : TIME := 100 ns; + ---------------------------- + + --- TB Initialiazzations --- + constant TB_CLK_INIT : STD_LOGIC := '0'; + constant TB_RESET_INIT : STD_LOGIC := '1'; + ---------------------------- + + + ------- DUT Generics ------- + constant DUT_BIT_LENGTH : INTEGER RANGE 1 TO 16 := 3; -- Leds used over the 16 in Basys3 + + constant DUT_T_ON_INIT : POSITIVE := 8; -- Init of Ton + constant DUT_PERIOD_INIT : POSITIVE := 16; -- Init of Periof + + constant DUT_PWM_INIT : STD_LOGIC := '1'; -- Init of PWM + ---------------------------- + + + ----------------------------------------------------------------- + + ------ COMPONENT DECLARATION for the Device Under Test (DUT) ------ + + ----------- DUT ----------- + component PulseWidthModulator + Generic( + + BIT_LENGTH : INTEGER RANGE 1 TO 16; -- Leds used over the 16 in Basys3 + + T_ON_INIT : POSITIVE; -- Init of Ton + PERIOD_INIT : POSITIVE; -- Init of Periof + + PWM_INIT : STD_LOGIC -- Init of PWM + ); + Port ( + + ------- Reset/Clock -------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + ---------------------------- + + -------- Duty Cycle ---------- + Ton : IN STD_LOGIC_VECTOR(BIT_LENGTH-1 downto 0); -- clk at PWM = '1' + Period : IN STD_LOGIC_VECTOR(BIT_LENGTH-1 downto 0); -- clk per period of PWM + + PWM : OUT STD_LOGIC -- PWM signal + ---------------------------- + + ); + end component; + + ---------------------------- + + + ------------------------------------------------------------------ + + + + + --------------------- SIGNALS DECLARATION ----------------------- + + + ------- Clock/Reset ------- + signal reset : STD_LOGIC := TB_RESET_INIT; + signal clk : STD_LOGIC := TB_CLK_INIT; + ---------------------------- + + + + -------- Duty Cycle ---------- + signal dut_Ton : STD_LOGIC_VECTOR(DUT_BIT_LENGTH-1 downto 0); -- clk at PWM = '1' + signal dut_Period : STD_LOGIC_VECTOR(DUT_BIT_LENGTH-1 downto 0); -- clk per period of PWM + + signal dut_PWM : STD_LOGIC; -- PWM signal + ---------------------------- + + ---------------------------------------------------------------- + + + + +begin + + + --------------------- COMPONENTS DUT WRAPPING -------------------- + + ----------- DUT ------------ + dut_PulseWidthModulator : PulseWidthModulator + Generic Map( + + BIT_LENGTH => DUT_BIT_LENGTH, + + T_ON_INIT => DUT_T_ON_INIT, + PERIOD_INIT => DUT_PERIOD_INIT, + + PWM_INIT => DUT_PWM_INIT + + ) + Port Map( + + ------- Reset/Clock -------- + reset => reset, + clk => clk, + ---------------------------- + + + -------- Duty Cycle ---------- + Ton => dut_Ton, + Period => dut_Period, + + PWM => dut_PWM + ---------------------------- + + ); + ---------------------------- + + ---------------------------- + + + + ------------------------------------------------------------------- + + + --------------------- TEST BENCH DATA FLOW ----------------------- + + ---------- clock ---------- + clk <= not clk after CLK_PERIOD/2; + ---------------------------- + + ------------------------------------------------------------------- + + + ---------------------- TEST BENCH PROCESS ------------------------- + + + ---- Clock Process -------- + -- clk_wave :process + -- begin + -- clk <= CLK_PERIOD; + -- wait for CLK_PERIOD/2; + + -- clk <= not clk; + -- wait for CLK_PERIOD/2; + -- end process; + -------------------------- + + + ----- Reset Process -------- + reset_wave :process + begin + reset <= TB_RESET_INIT; + wait for RESET_WND; + + reset <= not reset; + wait; + end process; + ---------------------------- + + + ------ Stimulus process ------- + + stim_proc: process + begin + + -- waiting the reset wave + + dut_Ton <= std_logic_vector(to_unsigned(0,DUT_BIT_LENGTH)); + dut_Period <= std_logic_vector(to_unsigned(0,DUT_BIT_LENGTH)); + wait for RESET_WND; + + + -- Start + for I in 0 to 2**DUT_BIT_LENGTH-1 loop + + dut_Period <= std_logic_vector(to_unsigned(I,DUT_BIT_LENGTH)); + + for J in 0 to 2**DUT_BIT_LENGTH-1 loop + + dut_Ton <= std_logic_vector(to_unsigned(J,DUT_BIT_LENGTH)); + + + wait for PWM_WND; + + end loop; + end loop; + + + dut_Ton <= std_logic_vector(to_unsigned(2**DUT_BIT_LENGTH-1,DUT_BIT_LENGTH)); + dut_Period <= std_logic_vector(to_unsigned(2**DUT_BIT_LENGTH-2,DUT_BIT_LENGTH)); + wait for PWM_WND; + + -- Stop + wait; + + + -------------------------- + + wait; + end process; + ---------------------------- + + ------------------------------------------------------------------- + + + + +end Behavioral; diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd new file mode 100644 index 0000000..fced822 --- /dev/null +++ b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd @@ -0,0 +1,181 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07.03.2019 12:46:18 +-- Design Name: +-- Module Name: tb_ShiftRegister_v0 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values + use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity tb_ShiftRegister_v0 is +end tb_ShiftRegister_v0; + +architecture Behavioral of tb_ShiftRegister_v0 is + + ------------------------ Constant Declaration ------------------------- + + -- Constant For Test Bench (TB) -- + constant RESET_ON : STD_LOGIC := '1'; + + constant CLK_PERIOD : time := 10 ns; + constant RESET_WND : time := 100 ns; + ---------------------------------- + + + ---------------------------------------------------------------------- + + + ----------------- Device Under Test (DUT) Declaration ---------------- + + ------------ DUT v0 -------------- + COMPONENT ShiftRegister_v0 + Port ( + + ---------- Reset/Clock ---------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + --------------------------------- + + ------------- Data -------------- + din : IN STD_LOGIC; + dout : OUT STD_LOGIC + --------------------------------- + + ); + END COMPONENT; + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + ------------------------- Signal Declaration ------------------------- + + ---------- Reset/Clock ---------- + signal reset : STD_LOGIC := RESET_ON; + signal clk : STD_LOGIC := '1'; + --------------------------------- + + + -------- ShiftRegister_v0 ------- + signal dut0_din : STD_LOGIC := '0'; + signal dut0_dout : STD_LOGIC; + --------------------------------- + + ---------------------------------------------------------------------- + + + +begin + + + + + + + ------------------- Device Under Test (DUT) Wrapper ------------------ + + ------------ DUT v0 -------------- + dut0_ShiftRegister_v0 : ShiftRegister_v0 + Port Map( + + ---------- Reset/Clock ---------- + reset => reset, + clk => clk, + --------------------------------- + + ------------- Data -------------- + din => dut0_din, + dout => dut0_dout + --------------------------------- + + ); + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + + -------------------------- Signals Generation ------------------------- + + + ------ TB Clk Generation ------- + + clk <= not clk after CLK_PERIOD/2; + --------------------------------- + + + ----- TB Reset Generation ------ + reset_wave : process + begin + + reset <= '1'; + wait for RESET_WND; + + reset <= '0'; + wait; + + end process; + --------------------------------- + + + + -- TB din pattern Generation --- + dut0_din_pattern : process + begin + + -- wait the reset window + dut0_din <= '0'; + wait for RESET_WND; + + -- Start + dut0_din <= '0'; + wait for CLK_PERIOD; + + dut0_din <= '1'; + wait for 4*CLK_PERIOD; + + dut0_din <= '0'; + wait for 8*CLK_PERIOD; + + -- Etc... + + -- Stop + wait; + + end process; + --------------------------------- + + + ---------------------------------------------------------------------- + + + +end Behavioral; diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd new file mode 100644 index 0000000..8ce09ce --- /dev/null +++ b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd @@ -0,0 +1,195 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07.03.2019 13:27:59 +-- Design Name: +-- Module Name: tb_ShiftRegister_v1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values + use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity tb_ShiftRegister_v1 is +end tb_ShiftRegister_v1; + +architecture Behavioral of tb_ShiftRegister_v1 is + + ------------------------ Constant Declaration ------------------------- + + -- Constant For Test Bench (TB) -- + constant RESET_ON : STD_LOGIC := '1'; + + constant CLK_PERIOD : time := 10 ns; + constant RESET_WND : time := 100 ns; + ---------------------------------- + + ------ Constant For DUT v0 ------ + constant DUT1_SR_DEPTH : POSITIVE := 4; + constant DUT1_SR_INIT : STD_LOGIC := '0'; + ---------------------------------- + + ---------------------------------------------------------------------- + + + ----------------- Device Under Test (DUT) Declaration ---------------- + + ------------ DUT v1 -------------- + COMPONENT ShiftRegister_v1 + Generic( + SR_DEPTH : POSITIVE; + SR_INIT : STD_LOGIC + ); + Port ( + + ---------- Reset/Clock ---------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + --------------------------------- + + ------------- Data -------------- + din : IN STD_LOGIC; + dout : OUT STD_LOGIC + --------------------------------- + + ); + END COMPONENT; + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + ------------------------- Signal Declaration ------------------------- + + ---------- Reset/Clock ---------- + signal reset : STD_LOGIC := RESET_ON; + signal clk : STD_LOGIC := '1'; + --------------------------------- + + + -------- ShiftRegister_v1 ------- + signal dut1_din : STD_LOGIC := '0'; + signal dut1_dout : STD_LOGIC; + --------------------------------- + + ---------------------------------------------------------------------- + + + +begin + + + + + + + ------------------- Device Under Test (DUT) Wrapper ------------------ + + ------------ DUT v1 -------------- + dut1_ShiftRegister_v1 : ShiftRegister_v1 + + Generic Map( + SR_DEPTH => DUT1_SR_DEPTH, + SR_INIT => DUT1_SR_INIT + ) + Port Map( + + ---------- Reset/Clock ---------- + reset => reset, + clk => clk, + --------------------------------- + + ------------- Data -------------- + din => dut1_din, + dout => dut1_dout + --------------------------------- + + ); + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + + -------------------------- Signals Generation ------------------------- + + + ------ TB Clk Generation ------- + + clk <= not clk after CLK_PERIOD/2; + --------------------------------- + + + ----- TB Reset Generation ------ + reset_wave : process + begin + + reset <= '1'; + wait for RESET_WND; + + reset <= '0'; + wait; + + end process; + --------------------------------- + + + + -- TB din pattern Generation --- + dut1_din_pattern : process + begin + + -- wait the reset window + dut1_din <= '0'; + wait for RESET_WND; + + + -- Start + dut1_din <= '0'; + wait for CLK_PERIOD; + + dut1_din <= '1'; + wait for 4*CLK_PERIOD; + + dut1_din <= '0'; + wait for 8*CLK_PERIOD; + + -- Etc... + + -- Stop + wait; + + end process; + --------------------------------- + + + ---------------------------------------------------------------------- + + + +end Behavioral; diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd new file mode 100644 index 0000000..bc50b5b --- /dev/null +++ b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd @@ -0,0 +1,198 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07.03.2019 16:39:28 +-- Design Name: +-- Module Name: tb_ShiftRegister_v2 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + + +library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values + use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity tb_ShiftRegister_v2 is +end tb_ShiftRegister_v2; + +architecture Behavioral of tb_ShiftRegister_v2 is + + ------------------------ Constant Declaration ------------------------- + + -- Constant For Test Bench (TB) -- + constant RESET_ON : STD_LOGIC := '1'; + + constant CLK_PERIOD : time := 10 ns; + constant RESET_WND : time := 100 ns; + ---------------------------------- + + ------ Constant For DUT v2 ------ + constant DUT2_SR_WIDTH : NATURAL := 8; + constant DUT2_SR_DEPTH : POSITIVE := 4; + constant DUT2_SR_INIT : STD_LOGIC := '0'; + ---------------------------------- + + ---------------------------------------------------------------------- + + + ----------------- Device Under Test (DUT) Declaration ---------------- + + ------------ DUT v2 -------------- + COMPONENT ShiftRegister_v2 + Generic( + SR_WIDTH : NATURAL := 7; + SR_DEPTH : POSITIVE := 4; + SR_INIT : STD_LOGIC := '0' + ); + Port ( + + ---------- Reset/Clock ---------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + --------------------------------- + + ------------- Data -------------- + din : IN STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0); + dout : OUT STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0) + --------------------------------- + + ); + END COMPONENT; + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + ------------------------- Signal Declaration ------------------------- + + ---------- Reset/Clock ---------- + signal reset : STD_LOGIC := RESET_ON; + signal clk : STD_LOGIC := '1'; + --------------------------------- + + + -------- ShiftRegister_v2 ------- + signal dut2_din : STD_LOGIC_VECTOR(DUT2_SR_WIDTH-1 downto 0) := (Others => '0'); + signal dut2_dout : STD_LOGIC_VECTOR(DUT2_SR_WIDTH-1 downto 0); + --------------------------------- + + ---------------------------------------------------------------------- + + + +begin + + + + + + + ------------------- Device Under Test (DUT) Wrapper ------------------ + + ------------ DUT v2 -------------- + dut2_ShiftRegister_v2 : ShiftRegister_v2 + + Generic Map( + SR_WIDTH => DUT2_SR_WIDTH, + SR_DEPTH => DUT2_SR_DEPTH, + SR_INIT => DUT2_SR_INIT + ) + Port Map( + + ---------- Reset/Clock ---------- + reset => reset, + clk => clk, + --------------------------------- + + ------------- Data -------------- + din => dut2_din, + dout => dut2_dout + --------------------------------- + + ); + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + + -------------------------- Signals Generation ------------------------- + + + ------ TB Clk Generation ------- + + clk <= not clk after CLK_PERIOD/2; + --------------------------------- + + + ----- TB Reset Generation ------ + reset_wave : process + begin + + reset <= '1'; + wait for RESET_WND; + + reset <= '0'; + wait; + + end process; + --------------------------------- + + + + -- TB din pattern Generation --- + dut2_din_pattern : process + begin + + -- wait the reset window + dut2_din <= (Others => '0'); + wait for RESET_WND; + + -- Start + dut2_din <= (Others => '0'); + wait for CLK_PERIOD; + + dut2_din <= (Others => '1'); + wait for 4*CLK_PERIOD; + + dut2_din <= (Others => '0'); + wait for 8*CLK_PERIOD; + + -- Etc... + + -- Stop + wait; + + end process; + --------------------------------- + + + ---------------------------------------------------------------------- + + + +end Behavioral; diff --git a/LAB1/lab1_kit_car b/LAB1/lab1_kit_car new file mode 160000 index 0000000..ec3447b --- /dev/null +++ b/LAB1/lab1_kit_car @@ -0,0 +1 @@ +Subproject commit ec3447bd8cd0d2d809c93a686076bfcfaff174af