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Refactor design files for LAB3: update diligent_jstk and add testbench for digilent_jstk2

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Davide Cavagnola
2025-05-14 14:34:22 +02:00
parent b11c65043f
commit aa8d8f3c7c
7 changed files with 650 additions and 282 deletions
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8
LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
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@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Mon May 12 15:44:44 2025
--Date : Wed May 14 13:59:17 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper
@@ -29,8 +29,6 @@ architecture STRUCTURE of diligent_jstk_wrapper is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
SPI_M_0_sck_t : out STD_LOGIC;
SPI_M_0_io1_o : out STD_LOGIC;
SPI_M_0_ss_t : out STD_LOGIC;
@@ -42,7 +40,9 @@ architecture STRUCTURE of diligent_jstk_wrapper is
SPI_M_0_sck_o : out STD_LOGIC;
SPI_M_0_ss_i : in STD_LOGIC;
SPI_M_0_io1_i : in STD_LOGIC;
SPI_M_0_io0_i : in STD_LOGIC
SPI_M_0_io0_i : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC
);
end component diligent_jstk;
component IOBUF is