diff --git a/LAB3/design/diligent_jstk/diligent_jstk.bd b/LAB3/design/diligent_jstk/diligent_jstk.bd new file mode 100644 index 0000000..ced2b7f --- /dev/null +++ b/LAB3/design/diligent_jstk/diligent_jstk.bd @@ -0,0 +1,673 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x7CDC72F2E486A675", + "device": "xc7a35tcpg236-1", + "name": "diligent_jstk", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "None", + "tool_version": "2020.2", + "validated": "true" + }, + "design_tree": { + "proc_sys_reset_0": "", + "clk_wiz_0": "", + "AXI4Stream_UART_0": "", + "digilent_jstk2_0": "", + "jstk_uart_bridge_0": "", + "axi4stream_spi_master_0": "" + }, + "interface_ports": { + "usb_uart": { + "mode": "Master", + "vlnv": "xilinx.com:interface:uart_rtl:1.0" + }, + "SPI_M_0": { + "mode": "Master", + "vlnv": "xilinx.com:interface:spi_rtl:1.0" + } + }, + "ports": { + "reset": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_HIGH" + } + } + }, + "sys_clock": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "diligent_jstk_sys_clock", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000" + } + } + } + }, + "components": { + "proc_sys_reset_0": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "diligent_jstk_proc_sys_reset_0_0", + "xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0\\diligent_jstk_proc_sys_reset_0_0.xci", + "inst_hier_path": "proc_sys_reset_0", + "parameters": { + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "clk_wiz_0": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "xci_name": "diligent_jstk_clk_wiz_0_1", + "xci_path": "ip\\diligent_jstk_clk_wiz_0_1\\diligent_jstk_clk_wiz_0_1.xci", + "inst_hier_path": "clk_wiz_0", + "parameters": { + "CLK_IN1_BOARD_INTERFACE": { + "value": "sys_clock" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "AXI4Stream_UART_0": { + "vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1", + "xci_name": "diligent_jstk_AXI4Stream_UART_0_0", + "xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0\\diligent_jstk_AXI4Stream_UART_0_0.xci", + "inst_hier_path": "AXI4Stream_UART_0", + "parameters": { + "UART_BOARD_INTERFACE": { + "value": "usb_uart" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "digilent_jstk2_0": { + "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0", + "xci_name": "diligent_jstk_digilent_jstk2_0_0", + "xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0\\diligent_jstk_digilent_jstk2_0_0.xci", + "inst_hier_path": "digilent_jstk2_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "digilent_jstk2", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "0", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + } + } + } + }, + "ports": { + "aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "jstk_x": { + "direction": "O", + "left": "9", + "right": "0" + }, + "jstk_y": { + "direction": "O", + "left": "9", + "right": "0" + }, + "btn_jstk": { + "direction": "O" + }, + "btn_trigger": { + "direction": "O" + }, + "led_r": { + "direction": "I", + "left": "7", + "right": "0" + }, + "led_g": { + "direction": "I", + "left": "7", + "right": "0" + }, + "led_b": { + "direction": "I", + "left": "7", + "right": "0" + } + } + }, + "jstk_uart_bridge_0": { + "vlnv": "xilinx.com:module_ref:jstk_uart_bridge:1.0", + "xci_name": "diligent_jstk_jstk_uart_bridge_0_0", + "xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0\\diligent_jstk_jstk_uart_bridge_0_0.xci", + "inst_hier_path": "jstk_uart_bridge_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "jstk_uart_bridge", + "boundary_crc": "0x0" + }, + "interface_ports": { + "m_axis": { + "mode": "Master", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "m_axis_tdata", + "direction": "O", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "m_axis_tvalid", + "direction": "O" + }, + "TREADY": { + "physical_name": "m_axis_tready", + "direction": "I" + } + } + }, + "s_axis": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:axis_rtl:1.0", + "parameters": { + "TDATA_NUM_BYTES": { + "value": "1", + "value_src": "constant" + }, + "TDEST_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TID_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "TUSER_WIDTH": { + "value": "0", + "value_src": "constant" + }, + "HAS_TREADY": { + "value": "1", + "value_src": "constant" + }, + "HAS_TSTRB": { + "value": "0", + "value_src": "constant" + }, + "HAS_TKEEP": { + "value": "0", + "value_src": "constant" + }, + "HAS_TLAST": { + "value": "0", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + }, + "port_maps": { + "TDATA": { + "physical_name": "s_axis_tdata", + "direction": "I", + "left": "7", + "right": "0" + }, + "TVALID": { + "physical_name": "s_axis_tvalid", + "direction": "I" + }, + "TREADY": { + "physical_name": "s_axis_tready", + "direction": "O" + } + } + } + }, + "ports": { + "aclk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "m_axis:s_axis", + "value_src": "constant" + }, + "ASSOCIATED_RESET": { + "value": "aresetn", + "value_src": "constant" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "/clk_wiz_0_clk_out1", + "value_src": "ip_prop" + } + } + }, + "aresetn": { + "type": "rst", + "direction": "I", + "parameters": { + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "constant" + } + } + }, + "jstk_x": { + "direction": "I", + "left": "9", + "right": "0" + }, + "jstk_y": { + "direction": "I", + "left": "9", + "right": "0" + }, + "btn_jstk": { + "direction": "I" + }, + "btn_trigger": { + "direction": "I" + }, + "led_r": { + "direction": "O", + "left": "7", + "right": "0" + }, + "led_g": { + "direction": "O", + "left": "7", + "right": "0" + }, + "led_b": { + "direction": "O", + "left": "7", + "right": "0" + } + } + }, + "axi4stream_spi_master_0": { + "vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0", + "xci_name": "diligent_jstk_axi4stream_spi_master_0_0", + "xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0\\diligent_jstk_axi4stream_spi_master_0_0.xci", + "inst_hier_path": "axi4stream_spi_master_0" + } + }, + "interface_nets": { + "jstk_uart_bridge_0_m_axis": { + "interface_ports": [ + "AXI4Stream_UART_0/S00_AXIS_TX", + "jstk_uart_bridge_0/m_axis" + ] + }, + "axi4stream_spi_master_0_M_AXIS": { + "interface_ports": [ + "axi4stream_spi_master_0/M_AXIS", + "digilent_jstk2_0/s_axis" + ] + }, + "digilent_jstk2_0_m_axis": { + "interface_ports": [ + "digilent_jstk2_0/m_axis", + "axi4stream_spi_master_0/S_AXIS" + ] + }, + "AXI4Stream_UART_0_UART": { + "interface_ports": [ + "usb_uart", + "AXI4Stream_UART_0/UART" + ] + }, + "AXI4Stream_UART_0_M00_AXIS_RX": { + "interface_ports": [ + "AXI4Stream_UART_0/M00_AXIS_RX", + "jstk_uart_bridge_0/s_axis" + ] + }, + "axi4stream_spi_master_0_SPI_M": { + "interface_ports": [ + "SPI_M_0", + "axi4stream_spi_master_0/SPI_M" + ] + } + }, + "nets": { + "reset_1": { + "ports": [ + "reset", + "proc_sys_reset_0/ext_reset_in", + "clk_wiz_0/reset" + ] + }, + "sys_clock_1": { + "ports": [ + "sys_clock", + "clk_wiz_0/clk_in1" + ] + }, + "clk_wiz_0_locked": { + "ports": [ + "clk_wiz_0/locked", + "proc_sys_reset_0/dcm_locked" + ] + }, + "clk_wiz_0_clk_out1": { + "ports": [ + "clk_wiz_0/clk_out1", + "proc_sys_reset_0/slowest_sync_clk", + "axi4stream_spi_master_0/aclk", + "digilent_jstk2_0/aclk", + "AXI4Stream_UART_0/clk_uart", + "AXI4Stream_UART_0/m00_axis_rx_aclk", + "jstk_uart_bridge_0/aclk", + "AXI4Stream_UART_0/s00_axis_tx_aclk" + ] + }, + "digilent_jstk2_0_btn_trigger": { + "ports": [ + "digilent_jstk2_0/btn_trigger", + "jstk_uart_bridge_0/btn_trigger" + ] + }, + "digilent_jstk2_0_btn_jstk": { + "ports": [ + "digilent_jstk2_0/btn_jstk", + "jstk_uart_bridge_0/btn_jstk" + ] + }, + "digilent_jstk2_0_jstk_y": { + "ports": [ + "digilent_jstk2_0/jstk_y", + "jstk_uart_bridge_0/jstk_y" + ] + }, + "digilent_jstk2_0_jstk_x": { + "ports": [ + "digilent_jstk2_0/jstk_x", + "jstk_uart_bridge_0/jstk_x" + ] + }, + "jstk_uart_bridge_0_led_r": { + "ports": [ + "jstk_uart_bridge_0/led_r", + "digilent_jstk2_0/led_r" + ] + }, + "jstk_uart_bridge_0_led_g": { + "ports": [ + "jstk_uart_bridge_0/led_g", + "digilent_jstk2_0/led_g" + ] + }, + "jstk_uart_bridge_0_led_b": { + "ports": [ + "jstk_uart_bridge_0/led_b", + "digilent_jstk2_0/led_b" + ] + }, + "proc_sys_reset_0_peripheral_aresetn": { + "ports": [ + "proc_sys_reset_0/peripheral_aresetn", + "digilent_jstk2_0/aresetn", + "AXI4Stream_UART_0/m00_axis_rx_aresetn", + "jstk_uart_bridge_0/aresetn", + "AXI4Stream_UART_0/s00_axis_tx_aresetn", + "axi4stream_spi_master_0/aresetn" + ] + }, + "proc_sys_reset_0_peripheral_reset": { + "ports": [ + "proc_sys_reset_0/peripheral_reset", + "AXI4Stream_UART_0/rst" + ] + } + } + } +} \ No newline at end of file diff --git a/LAB3/design/diligent_jstk/diligent_jstk.bda b/LAB3/design/diligent_jstk/diligent_jstk.bda new file mode 100644 index 0000000..0f3d98f --- /dev/null +++ b/LAB3/design/diligent_jstk/diligent_jstk.bda @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + 2 + diligent_jstk + VR + + + active + 2 + PM + + + diligent_jstk + BC + + + + + + + diff --git a/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd b/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd new file mode 100644 index 0000000..9c30c60 --- /dev/null +++ b/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd @@ -0,0 +1,116 @@ +--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +--Date : Mon May 12 15:44:44 2025 +--Host : Davide-Samsung running 64-bit major release (build 9200) +--Command : generate_target diligent_jstk_wrapper.bd +--Design : diligent_jstk_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity diligent_jstk_wrapper is + port ( + SPI_M_0_io0_io : inout STD_LOGIC; + SPI_M_0_io1_io : inout STD_LOGIC; + SPI_M_0_sck_io : inout STD_LOGIC; + SPI_M_0_ss_io : inout STD_LOGIC; + reset : in STD_LOGIC; + sys_clock : in STD_LOGIC; + usb_uart_rxd : in STD_LOGIC; + usb_uart_txd : out STD_LOGIC + ); +end diligent_jstk_wrapper; + +architecture STRUCTURE of diligent_jstk_wrapper is + component diligent_jstk is + port ( + reset : in STD_LOGIC; + sys_clock : in STD_LOGIC; + usb_uart_txd : out STD_LOGIC; + usb_uart_rxd : in STD_LOGIC; + SPI_M_0_sck_t : out STD_LOGIC; + SPI_M_0_io1_o : out STD_LOGIC; + SPI_M_0_ss_t : out STD_LOGIC; + SPI_M_0_io0_o : out STD_LOGIC; + SPI_M_0_sck_i : in STD_LOGIC; + SPI_M_0_ss_o : out STD_LOGIC; + SPI_M_0_io0_t : out STD_LOGIC; + SPI_M_0_io1_t : out STD_LOGIC; + SPI_M_0_sck_o : out STD_LOGIC; + SPI_M_0_ss_i : in STD_LOGIC; + SPI_M_0_io1_i : in STD_LOGIC; + SPI_M_0_io0_i : in STD_LOGIC + ); + end component diligent_jstk; + component IOBUF is + port ( + I : in STD_LOGIC; + O : out STD_LOGIC; + T : in STD_LOGIC; + IO : inout STD_LOGIC + ); + end component IOBUF; + signal SPI_M_0_io0_i : STD_LOGIC; + signal SPI_M_0_io0_o : STD_LOGIC; + signal SPI_M_0_io0_t : STD_LOGIC; + signal SPI_M_0_io1_i : STD_LOGIC; + signal SPI_M_0_io1_o : STD_LOGIC; + signal SPI_M_0_io1_t : STD_LOGIC; + signal SPI_M_0_sck_i : STD_LOGIC; + signal SPI_M_0_sck_o : STD_LOGIC; + signal SPI_M_0_sck_t : STD_LOGIC; + signal SPI_M_0_ss_i : STD_LOGIC; + signal SPI_M_0_ss_o : STD_LOGIC; + signal SPI_M_0_ss_t : STD_LOGIC; +begin +SPI_M_0_io0_iobuf: component IOBUF + port map ( + I => SPI_M_0_io0_o, + IO => SPI_M_0_io0_io, + O => SPI_M_0_io0_i, + T => SPI_M_0_io0_t + ); +SPI_M_0_io1_iobuf: component IOBUF + port map ( + I => SPI_M_0_io1_o, + IO => SPI_M_0_io1_io, + O => SPI_M_0_io1_i, + T => SPI_M_0_io1_t + ); +SPI_M_0_sck_iobuf: component IOBUF + port map ( + I => SPI_M_0_sck_o, + IO => SPI_M_0_sck_io, + O => SPI_M_0_sck_i, + T => SPI_M_0_sck_t + ); +SPI_M_0_ss_iobuf: component IOBUF + port map ( + I => SPI_M_0_ss_o, + IO => SPI_M_0_ss_io, + O => SPI_M_0_ss_i, + T => SPI_M_0_ss_t + ); +diligent_jstk_i: component diligent_jstk + port map ( + SPI_M_0_io0_i => SPI_M_0_io0_i, + SPI_M_0_io0_o => SPI_M_0_io0_o, + SPI_M_0_io0_t => SPI_M_0_io0_t, + SPI_M_0_io1_i => SPI_M_0_io1_i, + SPI_M_0_io1_o => SPI_M_0_io1_o, + SPI_M_0_io1_t => SPI_M_0_io1_t, + SPI_M_0_sck_i => SPI_M_0_sck_i, + SPI_M_0_sck_o => SPI_M_0_sck_o, + SPI_M_0_sck_t => SPI_M_0_sck_t, + SPI_M_0_ss_i => SPI_M_0_ss_i, + SPI_M_0_ss_o => SPI_M_0_ss_o, + SPI_M_0_ss_t => SPI_M_0_ss_t, + reset => reset, + sys_clock => sys_clock, + usb_uart_rxd => usb_uart_rxd, + usb_uart_txd => usb_uart_txd + ); +end STRUCTURE; diff --git a/LAB3/design/lab_3/lab_3.bda b/LAB3/design/lab_3/lab_3.bda index c595aff..3fa1797 100644 --- a/LAB3/design/lab_3/lab_3.bda +++ b/LAB3/design/lab_3/lab_3.bda @@ -26,17 +26,17 @@ VR - lab_3 - BC - - active 2 PM - + + lab_3 + BC + + - + diff --git a/LAB3/design/loopback_I2S/hdl/loopback_I2S_wrapper.vhd b/LAB3/design/loopback_I2S/hdl/loopback_I2S_wrapper.vhd new file mode 100644 index 0000000..1de23b4 --- /dev/null +++ b/LAB3/design/loopback_I2S/hdl/loopback_I2S_wrapper.vhd @@ -0,0 +1,58 @@ +--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +--Date : Mon May 12 18:14:19 2025 +--Host : Davide-Samsung running 64-bit major release (build 9200) +--Command : generate_target loopback_I2S_wrapper.bd +--Design : loopback_I2S_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity loopback_I2S_wrapper is + port ( + reset : in STD_LOGIC; + rx_lrck_0 : out STD_LOGIC; + rx_mclk_0 : out STD_LOGIC; + rx_sclk_0 : out STD_LOGIC; + rx_sdin_0 : in STD_LOGIC; + sys_clock : in STD_LOGIC; + tx_lrck_0 : out STD_LOGIC; + tx_mclk_0 : out STD_LOGIC; + tx_sclk_0 : out STD_LOGIC; + tx_sdout_0 : out STD_LOGIC + ); +end loopback_I2S_wrapper; + +architecture STRUCTURE of loopback_I2S_wrapper is + component loopback_I2S is + port ( + reset : in STD_LOGIC; + sys_clock : in STD_LOGIC; + rx_sdin_0 : in STD_LOGIC; + tx_mclk_0 : out STD_LOGIC; + tx_lrck_0 : out STD_LOGIC; + tx_sclk_0 : out STD_LOGIC; + tx_sdout_0 : out STD_LOGIC; + rx_mclk_0 : out STD_LOGIC; + rx_lrck_0 : out STD_LOGIC; + rx_sclk_0 : out STD_LOGIC + ); + end component loopback_I2S; +begin +loopback_I2S_i: component loopback_I2S + port map ( + reset => reset, + rx_lrck_0 => rx_lrck_0, + rx_mclk_0 => rx_mclk_0, + rx_sclk_0 => rx_sclk_0, + rx_sdin_0 => rx_sdin_0, + sys_clock => sys_clock, + tx_lrck_0 => tx_lrck_0, + tx_mclk_0 => tx_mclk_0, + tx_sclk_0 => tx_sclk_0, + tx_sdout_0 => tx_sdout_0 + ); +end STRUCTURE; diff --git a/LAB3/design/loopback_I2S/loopback_I2S.bd b/LAB3/design/loopback_I2S/loopback_I2S.bd new file mode 100644 index 0000000..5ec0828 --- /dev/null +++ b/LAB3/design/loopback_I2S/loopback_I2S.bd @@ -0,0 +1,288 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x82F7CD001DE2BC1E", + "device": "xc7a35tcpg236-1", + "name": "loopback_I2S", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "None", + "tool_version": "2020.2", + "validated": "true" + }, + "design_tree": { + "proc_sys_reset_0": "", + "clk_wiz_0": "", + "proc_sys_reset_1": "", + "axis_dual_i2s_0": "", + "system_ila_0": "" + }, + "ports": { + "reset": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_HIGH" + } + } + }, + "sys_clock": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "loopback_I2S_sys_clock", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000" + } + } + }, + "rx_sdin_0": { + "direction": "I" + }, + "tx_mclk_0": { + "direction": "O" + }, + "tx_lrck_0": { + "direction": "O" + }, + "tx_sclk_0": { + "direction": "O" + }, + "tx_sdout_0": { + "direction": "O" + }, + "rx_mclk_0": { + "direction": "O" + }, + "rx_lrck_0": { + "direction": "O" + }, + "rx_sclk_0": { + "direction": "O" + } + }, + "components": { + "proc_sys_reset_0": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "loopback_I2S_proc_sys_reset_0_0", + "xci_path": "ip\\loopback_I2S_proc_sys_reset_0_0\\loopback_I2S_proc_sys_reset_0_0.xci", + "inst_hier_path": "proc_sys_reset_0", + "parameters": { + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "clk_wiz_0": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "xci_name": "loopback_I2S_clk_wiz_0_0", + "xci_path": "ip\\loopback_I2S_clk_wiz_0_0\\loopback_I2S_clk_wiz_0_0.xci", + "inst_hier_path": "clk_wiz_0", + "parameters": { + "CLKOUT1_JITTER": { + "value": "149.337" + }, + "CLKOUT1_PHASE_ERROR": { + "value": "122.577" + }, + "CLKOUT2_JITTER": { + "value": "201.826" + }, + "CLKOUT2_PHASE_ERROR": { + "value": "122.577" + }, + "CLKOUT2_REQUESTED_OUT_FREQ": { + "value": "22.579" + }, + "CLKOUT2_USED": { + "value": "true" + }, + "CLK_IN1_BOARD_INTERFACE": { + "value": "sys_clock" + }, + "MMCM_CLKFBOUT_MULT_F": { + "value": "7.000" + }, + "MMCM_CLKOUT0_DIVIDE_F": { + "value": "7.000" + }, + "MMCM_CLKOUT1_DIVIDE": { + "value": "31" + }, + "NUM_OUT_CLKS": { + "value": "2" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "proc_sys_reset_1": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "loopback_I2S_proc_sys_reset_0_1", + "xci_path": "ip\\loopback_I2S_proc_sys_reset_0_1\\loopback_I2S_proc_sys_reset_0_1.xci", + "inst_hier_path": "proc_sys_reset_1", + "parameters": { + "RESET_BOARD_INTERFACE": { + "value": "reset" + }, + "USE_BOARD_FLOW": { + "value": "true" + } + } + }, + "axis_dual_i2s_0": { + "vlnv": "DigiLAB:ip:axis_dual_i2s:1.0", + "xci_name": "loopback_I2S_axis_dual_i2s_0_0", + "xci_path": "ip\\loopback_I2S_axis_dual_i2s_0_0\\loopback_I2S_axis_dual_i2s_0_0.xci", + "inst_hier_path": "axis_dual_i2s_0" + }, + "system_ila_0": { + "vlnv": "xilinx.com:ip:system_ila:1.1", + "xci_name": "loopback_I2S_system_ila_0_0", + "xci_path": "ip\\loopback_I2S_system_ila_0_0\\loopback_I2S_system_ila_0_0.xci", + "inst_hier_path": "system_ila_0", + "parameters": { + "C_SLOT_0_INTF_TYPE": { + "value": "xilinx.com:interface:axis_rtl:1.0" + } + }, + "interface_ports": { + "SLOT_0_AXIS": { + "mode": "Monitor", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + } + } + } + }, + "interface_nets": { + "axis_dual_i2s_0_m_axis": { + "interface_ports": [ + "axis_dual_i2s_0/s_axis", + "axis_dual_i2s_0/m_axis", + "system_ila_0/SLOT_0_AXIS" + ] + } + }, + "nets": { + "reset_1": { + "ports": [ + "reset", + "proc_sys_reset_0/ext_reset_in", + "clk_wiz_0/reset", + "proc_sys_reset_1/ext_reset_in" + ] + }, + "sys_clock_1": { + "ports": [ + "sys_clock", + "clk_wiz_0/clk_in1" + ] + }, + "clk_wiz_0_locked": { + "ports": [ + "clk_wiz_0/locked", + "proc_sys_reset_0/dcm_locked", + "proc_sys_reset_1/dcm_locked" + ] + }, + "clk_wiz_0_clk_out1": { + "ports": [ + "clk_wiz_0/clk_out1", + "system_ila_0/clk", + "axis_dual_i2s_0/aclk", + "proc_sys_reset_0/slowest_sync_clk" + ] + }, + "clk_wiz_0_clk_out2": { + "ports": [ + "clk_wiz_0/clk_out2", + "proc_sys_reset_1/slowest_sync_clk", + "axis_dual_i2s_0/i2s_clk" + ] + }, + "proc_sys_reset_0_peripheral_aresetn": { + "ports": [ + "proc_sys_reset_0/peripheral_aresetn", + "system_ila_0/resetn", + "axis_dual_i2s_0/aresetn" + ] + }, + "proc_sys_reset_1_peripheral_aresetn": { + "ports": [ + "proc_sys_reset_1/peripheral_aresetn", + "axis_dual_i2s_0/i2s_resetn" + ] + }, + "rx_sdin_0_1": { + "ports": [ + "rx_sdin_0", + "axis_dual_i2s_0/rx_sdin" + ] + }, + "axis_dual_i2s_0_tx_mclk": { + "ports": [ + "axis_dual_i2s_0/tx_mclk", + "tx_mclk_0" + ] + }, + "axis_dual_i2s_0_tx_lrck": { + "ports": [ + "axis_dual_i2s_0/tx_lrck", + "tx_lrck_0" + ] + }, + "axis_dual_i2s_0_tx_sclk": { + "ports": [ + "axis_dual_i2s_0/tx_sclk", + "tx_sclk_0" + ] + }, + "axis_dual_i2s_0_tx_sdout": { + "ports": [ + "axis_dual_i2s_0/tx_sdout", + "tx_sdout_0" + ] + }, + "axis_dual_i2s_0_rx_mclk": { + "ports": [ + "axis_dual_i2s_0/rx_mclk", + "rx_mclk_0" + ] + }, + "axis_dual_i2s_0_rx_lrck": { + "ports": [ + "axis_dual_i2s_0/rx_lrck", + "rx_lrck_0" + ] + }, + "axis_dual_i2s_0_rx_sclk": { + "ports": [ + "axis_dual_i2s_0/rx_sclk", + "rx_sclk_0" + ] + } + } + } +} \ No newline at end of file diff --git a/LAB3/design/loopback_I2S/loopback_I2S.bda b/LAB3/design/loopback_I2S/loopback_I2S.bda new file mode 100644 index 0000000..0954fbe --- /dev/null +++ b/LAB3/design/loopback_I2S/loopback_I2S.bda @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + active + 2 + PM + + + 2 + loopback_I2S + VR + + + loopback_I2S + BC + + + + + + + diff --git a/LAB3/ip/AXI4-Stream_UART/bd/bd.tcl b/LAB3/ip/AXI4-Stream_UART/bd/bd.tcl new file mode 100644 index 0000000..75d3124 --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/bd/bd.tcl @@ -0,0 +1,89 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + # Set module clock frequency reference to be equal to the input clock. + set_property CONFIG.UART_CLOCK_FREQUENCY [format %d [get_property CONFIG.FREQ_HZ [get_bd_pins $cellpath/clk_uart]]] $cell_handle + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/LAB3/ip/AXI4-Stream_UART/component.xml b/LAB3/ip/AXI4-Stream_UART/component.xml new file mode 100644 index 0000000..2f28849 --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/component.xml @@ -0,0 +1,765 @@ + + + DigiLAB + ip + AXI4Stream_UART + 1.1 + + + M00_AXIS_RX + + + + + + + TDATA + + + m00_axis_rx_tdata + + + + + TVALID + + + m00_axis_rx_tvalid + + + + + TREADY + + + m00_axis_rx_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + + + S00_AXIS_TX + + + + + + + TDATA + + + s00_axis_tx_tdata + + + + + TVALID + + + s00_axis_tx_tvalid + + + + + TREADY + + + s00_axis_tx_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + + + M00_AXIS_RX_RST + + + + + + + RST + + + m00_axis_rx_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + M00_AXIS_RX_CLK + + + + + + + CLK + + + m00_axis_rx_aclk + + + + + + ASSOCIATED_BUSIF + M00_AXIS_RX + + + ASSOCIATED_RESET + m00_axis_rx_aresetn + + + + + S00_AXIS_TX_RST + + + + + + + RST + + + s00_axis_tx_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S00_AXIS_TX_CLK + + + + + + + CLK + + + s00_axis_tx_aclk + + + + + + ASSOCIATED_BUSIF + S00_AXIS_TX + + + ASSOCIATED_RESET + s00_axis_tx_aresetn + + + + + reset + + + + + + + RST + + + rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + ClockUART + Clock used to calculate the delay for UART + + + + + + + CLK + + + clk_uart + + + + + + ASSOCIATED_BUSIF + UART + + + ASSOCIATED_RESET + rst + + + + + UART + UART + + + + + + + TxD + + + UART_TX + + + + + RxD + + + UART_RX + + + + + + BOARD.ASSOCIATED_PARAM + UART_BOARD_INTERFACE + + + + required + + + + + + + + + + + xilinx_vhdlsynthesis + Synthesis + :vivado.xilinx.com:synthesis + vhdl + AXI4Stream_UART_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 47fd635e + + + + + xilinx_vhdlbehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + vhdl + AXI4Stream_UART_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 47fd635e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 5514ca69 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + c55a27a0 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + + viewChecksum + 16e75233 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + viewChecksum + 5c730a16 + + + + + + + clk_uart + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + rst + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + UART_TX + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + UART_RX + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m00_axis_rx_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m00_axis_rx_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m00_axis_rx_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m00_axis_rx_tdata + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m00_axis_rx_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tx_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tx_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tx_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tx_tdata + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tx_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + UART_BAUD_RATE + Rs232 Baud Rate + 115200 + + + UART_CLOCK_FREQUENCY + Rs232 Clock Frequency + 100000000 + + + C_M00_AXIS_RX_TDATA_WIDTH + C M00 Axis Rx Tdata Width + 8 + + + C_S00_AXIS_TX_TDATA_WIDTH + C S00 Axis Tx Tdata Width + 8 + + + + + + choice_list_23c37a81 + 2400 + 4800 + 9600 + 19200 + 38400 + 57600 + 115200 + 230400 + 460800 + 921600 + 1000000 + 1500000 + 2000000 + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_d8920bdd + 8 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd + vhdlSource + + + hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd + vhdlSource + + + hdl/UART_Engine.vhd + vhdlSource + + + hdl/UART_Manager.vhd + vhdlSource + + + hdl/AXI4Stream_UART_v1_0.vhd + vhdlSource + CHECKSUM_dad462a3 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd + vhdlSource + + + hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd + vhdlSource + + + hdl/UART_Engine.vhd + vhdlSource + + + hdl/UART_Manager.vhd + vhdlSource + + + hdl/AXI4Stream_UART_v1_0.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/AXI4Stream_UART_v1_1.tcl + tclSource + CHECKSUM_5514ca69 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_implementation_view_fileset + + utils/board/board.xit + xit + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output + + + Component_Name + AXI4Stream_UART_v1_0 + + + UART_BAUD_RATE + Baud Rate + 115200 + + + UART_CLOCK_FREQUENCY + Rs232 Clock Frequency + 100000000 + + + C_M00_AXIS_RX_TDATA_WIDTH + C M00 Axis Rx Tdata Width + 8 + + + + false + + + + + + C_S00_AXIS_TX_TDATA_WIDTH + C S00 Axis Tx Tdata Width + 8 + + + USE_BOARD_FLOW + false + + + UART_BOARD_INTERFACE + Custom + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + virtexuplus + kintexuplus + zynquplus + kintexu + + + /AXI_Peripheral + + AXI4-Stream UART + + XPM_FIFO + + 1 + + TimeEngineers:ip:AXI4Stream_UART:1.0 + + 2021-01-15T12:00:01Z + + + 2020.2 + + + + + + + + diff --git a/LAB3/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0.vhd b/LAB3/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0.vhd new file mode 100644 index 0000000..2561dec --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0.vhd @@ -0,0 +1,398 @@ + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ---- * ) ---- + ----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ---- + ---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ---- + ----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ---- + ----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ---- + ---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ---- + ---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ---- + ---- |___/ |___/ ---- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +---- _____ _ ___ __ _ _ _ __ _ ---- +---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ---- +---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ---- +---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ---- +---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ---- +----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ---- +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ + +-------------------------------------DESCRIPTION------------------------------------------ +------------------------------------------------------------------------------------------ +-- Bridge FT245Async to AXI4-Stream. -- +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library xpm; + use xpm.vcomponents.all; + +entity AXI4Stream_UART_v1_0 is + generic ( + ------------------UART PARAMETER------------------- + UART_BAUD_RATE : positive := 115_200; + UART_CLOCK_FREQUENCY : positive := 100_000_000; --The associated clock frequency + ---------------------------------------------------- + + -- Parameters of Axi Master Bus Interface M00_AXIS_RX + C_M00_AXIS_RX_TDATA_WIDTH : integer := 8; + -- Parameters of Axi Slave Bus Interface S00_AXIS_TX + C_S00_AXIS_TX_TDATA_WIDTH : integer := 8 + ); + port ( + ---------Global--------- + clk_uart : IN STD_LOGIC; + rst : IN STD_LOGIC; + ------------------------ + + ---------Connessioni comunicazione UART----------- + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + --------------------------------------------------- + + ---Ports of Axi Master Bus Interface M00_AXIS_RX--- + m00_axis_rx_aclk : IN STD_LOGIC; + m00_axis_rx_aresetn : IN STD_LOGIC; + m00_axis_rx_tvalid : OUT STD_LOGIC; + m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(C_M00_AXIS_RX_TDATA_WIDTH-1 DOWNTO 0); + m00_axis_rx_tready : IN STD_LOGIC; + -------------------------------------------------- + ---Ports of Axi Slave Bus Interface S00_AXIS_TX--- + s00_axis_tx_aclk : IN STD_LOGIC; + s00_axis_tx_aresetn : IN STD_LOGIC; + s00_axis_tx_tready : OUT STD_LOGIC; + s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(C_S00_AXIS_TX_TDATA_WIDTH-1 DOWNTO 0); + s00_axis_tx_tvalid : IN STD_LOGIC + -------------------------------------------------- + ); +end AXI4Stream_UART_v1_0; + +architecture arch_imp of AXI4Stream_UART_v1_0 is + + --------------------------------COMPONENTS DECLARATION----------------------------------- + component UART_Manager is + generic( + UART_BAUD_RATE : positive; + UART_CLOCK_FREQUENCY : positive --The associated clock frequency + ); + Port ( + ---------Global--------- + clk_uart : IN STD_LOGIC; + reset : IN STD_LOGIC; + ------------------------ + + ---------Connessioni comunicazione UART----------- + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + --------------------------------------------------- + + ------------FIFO_DATA_RX (8bit)------------- + FIFO_DATA_RX_rst : OUT STD_LOGIC; + FIFO_DATA_RX_clk : OUT STD_LOGIC; + FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_RX_wr_en : OUT STD_LOGIC; + FIFO_DATA_RX_full : IN STD_LOGIC; + FIFO_DATA_RX_almost_full : IN STD_LOGIC; + -------------------------------------------- + + ------------FIFO_DATA_TX (8bit)------------- + --FIFO_DATA_RX_rst : OUT STD_LOGIC; + FIFO_DATA_TX_clk : OUT STD_LOGIC; + FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_TX_rd_en : OUT STD_LOGIC; + FIFO_DATA_TX_empty : IN STD_LOGIC; + FIFO_DATA_TX_almost_empty : IN STD_LOGIC + -------------------------------------------- + ); + end component UART_Manager; + + component AXI4Stream_UART_v1_0_M00_AXIS_RX is + generic ( + -- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + C_M_AXIS_TDATA_WIDTH : integer := 8 + ); + port ( + --------------FIFO_DATA (8bit)-------------- + --FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO + FIFO_DATA_clk : OUT STD_LOGIC; + FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_rd_en : OUT STD_LOGIC; + FIFO_DATA_empty : IN STD_LOGIC; + FIFO_DATA_almost_empty : IN STD_LOGIC; + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream Clock + M_AXIS_ACLK : IN STD_LOGIC; + -- AXI4Stream Reset + M_AXIS_ARESETN : IN STD_LOGIC; + -- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + M_AXIS_TVALID : OUT STD_LOGIC; + -- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0); + -- TREADY indicates that the slave can accept a transfer in the current cycle. + M_AXIS_TREADY : IN STD_LOGIC + -------------------------------------------- + ); + end component AXI4Stream_UART_v1_0_M00_AXIS_RX; + + component AXI4Stream_UART_v1_0_S00_AXIS_TX is + generic ( + -- AXI4Stream sink: Data Width + C_S_AXIS_TDATA_WIDTH : integer := 8 + ); + port ( + + --------------FIFO_DATA------------- + FIFO_DATA_rst : OUT STD_LOGIC; + FIFO_DATA_clk : OUT STD_LOGIC; + FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0); + FIFO_DATA_wr_en : OUT STD_LOGIC; + FIFO_DATA_full : IN STD_LOGIC; + FIFO_DATA_almost_full : IN STD_LOGIC; + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream sink: Clock + S_AXIS_ACLK : IN STD_LOGIC; + -- AXI4Stream sink: Reset + S_AXIS_ARESETN : IN STD_LOGIC; + -- Ready to accept data in + S_AXIS_TREADY : OUT STD_LOGIC; + -- Data in + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0); + -- Data is in valid + S_AXIS_TVALID : IN STD_LOGIC + -------------------------------------------- + ); + end component AXI4Stream_UART_v1_0_S00_AXIS_TX; + ----------------------------------------------------------------------------------------- + + ---------------------------------------SIGNALS------------------------------------------- + -----------------FIFO_DATA_RX----------------- + signal FIFO_DATA_RX_rst : STD_LOGIC; + signal FIFO_DATA_RX_wr_clk : STD_LOGIC; + signal FIFO_DATA_RX_rd_clk : STD_LOGIC; + signal FIFO_DATA_RX_din : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal FIFO_DATA_RX_wr_en : STD_LOGIC; + signal FIFO_DATA_RX_rd_en : STD_LOGIC; + signal FIFO_DATA_RX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal FIFO_DATA_RX_full : STD_LOGIC; + signal FIFO_DATA_RX_almost_full : STD_LOGIC; + signal FIFO_DATA_RX_empty : STD_LOGIC; + signal FIFO_DATA_RX_almost_empty : STD_LOGIC; + ---------------------------------------------- + + -----------------FIFO_DATA_TX----------------- + signal FIFO_DATA_TX_rst : STD_LOGIC; + signal FIFO_DATA_TX_wr_clk : STD_LOGIC; + signal FIFO_DATA_TX_rd_clk : STD_LOGIC; + signal FIFO_DATA_TX_din : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal FIFO_DATA_TX_wr_en : STD_LOGIC; + signal FIFO_DATA_TX_rd_en : STD_LOGIC; + signal FIFO_DATA_TX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal FIFO_DATA_TX_full : STD_LOGIC; + signal FIFO_DATA_TX_almost_full : STD_LOGIC; + signal FIFO_DATA_TX_empty : STD_LOGIC; + signal FIFO_DATA_TX_almost_empty : STD_LOGIC; + ---------------------------------------------- + + ----------------------------------------------------------------------------------------- + +begin + + -----------------------MODULE INSTANTIATION------------------------- + AXI4Stream_UART_v1_0_S00_AXIS_TX_inst : AXI4Stream_UART_v1_0_S00_AXIS_TX + generic map( + -- AXI4Stream sink: Data Width + C_S_AXIS_TDATA_WIDTH => C_S00_AXIS_TX_TDATA_WIDTH + ) + port map( + + --------------FIFO_DATA------------- + FIFO_DATA_rst => FIFO_DATA_TX_rst, + FIFO_DATA_clk => FIFO_DATA_TX_wr_clk, + FIFO_DATA_din => FIFO_DATA_TX_din, + FIFO_DATA_wr_en => FIFO_DATA_TX_wr_en, + FIFO_DATA_full => FIFO_DATA_TX_full, + FIFO_DATA_almost_full => FIFO_DATA_TX_almost_full, + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream sink: Clock + S_AXIS_ACLK => s00_axis_tx_aclk, + -- AXI4Stream sink: Reset + S_AXIS_ARESETN => s00_axis_tx_aresetn, + -- Ready to accept data in + S_AXIS_TREADY => s00_axis_tx_tready, + -- Data in + S_AXIS_TDATA => s00_axis_tx_tdata, + -- Data is in valid + S_AXIS_TVALID => s00_axis_tx_tvalid + -------------------------------------------- + ); + + -- xpm_fifo_async: Asynchronous FIFO + -- Xilinx Parameterized Macro, Version 2017.3 + FIFO_DATA_TX : xpm_fifo_async + generic map ( + FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra"; + FIFO_WRITE_DEPTH => 2048, --positive integer; + RELATED_CLOCKS => 0, --positive integer; 0 or 1; + WRITE_DATA_WIDTH => 8, --positive integer; + WR_DATA_COUNT_WIDTH => 1, --positive integer; + READ_MODE => "fwft", --string; "std" or "fwft"; + FIFO_READ_LATENCY => 0, --positive integer; + --FULL_RESET_VALUE => 0, --positive integer; 0 or 1; + READ_DATA_WIDTH => 8, --positive integer; + RD_DATA_COUNT_WIDTH => 1, --positive integer; + CDC_SYNC_STAGES => 2, --positive integer; + ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; + --PROG_FULL_THRESH => 10, --positive integer + --PROG_EMPTY_THRESH => 10, --positive integer + --DOUT_RESET_VALUE => "0", --string + WAKEUP_TIME => 0, --positive integer; 0 or 2; + USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty + ) + port map ( + wr_clk => FIFO_DATA_TX_wr_clk, + wr_en => FIFO_DATA_TX_wr_en, + din => FIFO_DATA_TX_din, + full => FIFO_DATA_TX_full, + overflow => open, + wr_rst_busy => open, + sleep => '0', + rst => FIFO_DATA_TX_rst, + rd_clk => FIFO_DATA_TX_rd_clk, + rd_en => FIFO_DATA_TX_rd_en, + dout => FIFO_DATA_TX_dout, + empty => FIFO_DATA_TX_empty, + underflow => open, + rd_rst_busy => open, + injectsbiterr => '0', + injectdbiterr => '0', + almost_full => FIFO_DATA_TX_almost_full, + almost_empty => FIFO_DATA_TX_almost_empty + ); + + UART_Manager_inst : UART_Manager + Generic map( + UART_BAUD_RATE => UART_BAUD_RATE, + UART_CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY + ) + Port map( + ---------Global--------- + clk_uart => clk_uart, + reset => rst, + ------------------------ + + ---------Connessioni comunicazione UART----------- + UART_TX => UART_TX, + UART_RX => UART_RX, + --------------------------------------------------- + + ------------FIFO_DATA_RX (8bit)------------- + FIFO_DATA_RX_rst => FIFO_DATA_RX_rst, + FIFO_DATA_RX_clk => FIFO_DATA_RX_wr_clk, + FIFO_DATA_RX_din => FIFO_DATA_RX_din, + FIFO_DATA_RX_wr_en => FIFO_DATA_RX_wr_en, + FIFO_DATA_RX_full => FIFO_DATA_RX_full, + FIFO_DATA_RX_almost_full => FIFO_DATA_RX_almost_full, + -------------------------------------------- + + ------------FIFO_DATA_TX (8bit)------------- + FIFO_DATA_TX_clk => FIFO_DATA_TX_rd_clk, + FIFO_DATA_TX_dout => FIFO_DATA_TX_dout, + FIFO_DATA_TX_rd_en => FIFO_DATA_TX_rd_en, + FIFO_DATA_TX_empty => FIFO_DATA_TX_empty, + FIFO_DATA_TX_almost_empty => FIFO_DATA_TX_almost_empty + -------------------------------------------- + ); + + -- xpm_fifo_async: Asynchronous FIFO + -- Xilinx Parameterized Macro, Version 2017.3 + FIFO_DATA_RX : xpm_fifo_async + generic map ( + FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra"; + FIFO_WRITE_DEPTH => 2048, --positive integer; + RELATED_CLOCKS => 0, --positive integer; 0 or 1; + WRITE_DATA_WIDTH => 8, --positive integer; + WR_DATA_COUNT_WIDTH => 1, --positive integer; + READ_MODE => "fwft", --string; "std" or "fwft"; + FIFO_READ_LATENCY => 0, --positive integer; + --FULL_RESET_VALUE => 0, --positive integer; 0 or 1; + READ_DATA_WIDTH => 8, --positive integer; + RD_DATA_COUNT_WIDTH => 1, --positive integer; + CDC_SYNC_STAGES => 2, --positive integer; + ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; + --PROG_FULL_THRESH => 10, --positive integer + --PROG_EMPTY_THRESH => 10, --positive integer + --DOUT_RESET_VALUE => "0", --string + WAKEUP_TIME => 0, --positive integer; 0 or 2; + USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty + ) + port map ( + wr_clk => FIFO_DATA_RX_wr_clk, + wr_en => FIFO_DATA_RX_wr_en, + din => FIFO_DATA_RX_din, + full => FIFO_DATA_RX_full, + overflow => open, + wr_rst_busy => open, + sleep => '0', + rst => FIFO_DATA_RX_rst, + rd_clk => FIFO_DATA_RX_rd_clk, + rd_en => FIFO_DATA_RX_rd_en, + dout => FIFO_DATA_RX_dout, + empty => FIFO_DATA_RX_empty, + underflow => open, + rd_rst_busy => open, + injectsbiterr => '0', + injectdbiterr => '0', + almost_full => FIFO_DATA_RX_almost_full, + almost_empty => FIFO_DATA_RX_almost_empty + ); + + AXI4Stream_UART_v1_0_M00_AXIS_RX_inst : AXI4Stream_UART_v1_0_M00_AXIS_RX + generic map( + -- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + C_M_AXIS_TDATA_WIDTH => C_M00_AXIS_RX_TDATA_WIDTH + + ) + port map( + --------------FIFO_DATA (8bit)-------------- + FIFO_DATA_clk => FIFO_DATA_RX_rd_clk, + FIFO_DATA_dout => FIFO_DATA_RX_dout, + FIFO_DATA_rd_en => FIFO_DATA_RX_rd_en, + FIFO_DATA_empty => FIFO_DATA_RX_empty, + FIFO_DATA_almost_empty => FIFO_DATA_RX_almost_empty, + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream Clock + M_AXIS_ACLK => m00_axis_rx_aclk, + -- AXI4Stream Reset + M_AXIS_ARESETN => m00_axis_rx_aresetn, + -- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + M_AXIS_TVALID => m00_axis_rx_tvalid, + -- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + M_AXIS_TDATA => m00_axis_rx_tdata, + -- TREADY indicates that the slave can accept a transfer in the current cycle. + M_AXIS_TREADY => m00_axis_rx_tready + -------------------------------------------- + ); + + -------------------------------------------------------------------- + +end arch_imp; diff --git a/LAB3/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd b/LAB3/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd new file mode 100644 index 0000000..5353ffd --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd @@ -0,0 +1,91 @@ + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ---- * ) ---- + ----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ---- + ---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ---- + ----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ---- + ----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ---- + ---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ---- + ---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ---- + ---- |___/ |___/ ---- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +---- _____ _ ___ __ _ _ _ __ _ ---- +---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ---- +---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ---- +---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ---- +---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ---- +----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ---- +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ + +-------------------------------------DESCRIPTION------------------------------------------ +------------------------------------------------------------------------------------------ +-- Bridge da FIFO 8bit to AXI4 Stream. -- +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity AXI4Stream_UART_v1_0_M00_AXIS_RX is + generic ( + -- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + C_M_AXIS_TDATA_WIDTH : integer := 8 + ); + port ( + --------------FIFO_DATA (8bit)-------------- + --FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO + FIFO_DATA_clk : OUT STD_LOGIC; + FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_rd_en : OUT STD_LOGIC; + FIFO_DATA_empty : IN STD_LOGIC; + FIFO_DATA_almost_empty : IN STD_LOGIC; + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream Clock + M_AXIS_ACLK : IN STD_LOGIC; + -- AXI4Stream Reset + M_AXIS_ARESETN : IN STD_LOGIC; + -- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + M_AXIS_TVALID : OUT STD_LOGIC; + -- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0); + -- TREADY indicates that the slave can accept a transfer in the current cycle. + M_AXIS_TREADY : IN STD_LOGIC + -------------------------------------------- + ); +end AXI4Stream_UART_v1_0_M00_AXIS_RX; + +architecture implementation of AXI4Stream_UART_v1_0_M00_AXIS_RX is + + ----------------------------SIGNALS----------------------------- + signal M_AXIS_TVALID_int : STD_LOGIC; + ---------------------------------------------------------------- + +begin + + ---------DIRECT ASSIGNMENT---------- + FIFO_DATA_clk <= M_AXIS_ACLK; + --FIFO_DATA_rst <= not M_AXIS_ARESETN; + + M_AXIS_TDATA <= FIFO_DATA_dout; + + FIFO_DATA_rd_en <= M_AXIS_TREADY and M_AXIS_TVALID_int; + + M_AXIS_TVALID_int <= not FIFO_DATA_empty and M_AXIS_ARESETN; + M_AXIS_TVALID <= M_AXIS_TVALID_int; + + ------------------------------------ + +end implementation; \ No newline at end of file diff --git a/LAB3/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd b/LAB3/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd new file mode 100644 index 0000000..4ff7986 --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd @@ -0,0 +1,90 @@ + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ---- * ) ---- + ----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ---- + ---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ---- + ----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ---- + ----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ---- + ---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ---- + ---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ---- + ---- |___/ |___/ ---- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +---- _____ _ ___ __ _ _ _ __ _ ---- +---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ---- +---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ---- +---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ---- +---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ---- +----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ---- +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ + +-------------------------------------DESCRIPTION------------------------------------------ +------------------------------------------------------------------------------------------ +-- Bridge da FIFO 8bit to AXI4 Stream. -- +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity AXI4Stream_UART_v1_0_S00_AXIS_TX is + generic ( + -- AXI4Stream sink: Data Width + C_S_AXIS_TDATA_WIDTH : integer := 8 + ); + port ( + + --------------FIFO_DATA (32bit)------------- + FIFO_DATA_rst : OUT STD_LOGIC; + FIFO_DATA_clk : OUT STD_LOGIC; + FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0); + FIFO_DATA_wr_en : OUT STD_LOGIC; + FIFO_DATA_full : IN STD_LOGIC; + FIFO_DATA_almost_full : IN STD_LOGIC; + -------------------------------------------- + + ----------------AXI4-Stream----------------- + -- AXI4Stream sink: Clock + S_AXIS_ACLK : IN STD_LOGIC; + -- AXI4Stream sink: Reset + S_AXIS_ARESETN : IN STD_LOGIC; + -- Ready to accept data in + S_AXIS_TREADY : OUT STD_LOGIC; + -- Data in + S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0); + -- Data is in valid + S_AXIS_TVALID : IN STD_LOGIC + -------------------------------------------- + ); +end AXI4Stream_UART_v1_0_S00_AXIS_TX; + +architecture arch_imp of AXI4Stream_UART_v1_0_S00_AXIS_TX is + + -----------------------------SIGNALS---------------------------- + signal S_AXIS_TREADY_int : STD_LOGIC; + ---------------------------------------------------------------- + +begin + + ---------DIRECT ASSIGNMENT---------- + FIFO_DATA_clk <= S_AXIS_ACLK; + FIFO_DATA_rst <= not S_AXIS_ARESETN; + + FIFO_DATA_din <= S_AXIS_TDATA; + + FIFO_DATA_wr_en <= S_AXIS_TREADY_int and S_AXIS_TVALID; + + S_AXIS_TREADY_int <= not FIFO_DATA_almost_full and S_AXIS_ARESETN; + S_AXIS_TREADY <= S_AXIS_TREADY_int; + ------------------------------------ + +end arch_imp; diff --git a/LAB3/ip/AXI4-Stream_UART/hdl/UART_Engine.vhd b/LAB3/ip/AXI4-Stream_UART/hdl/UART_Engine.vhd new file mode 100644 index 0000000..6ccdf10 --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/hdl/UART_Engine.vhd @@ -0,0 +1,343 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:02:15 01/23/2016 +-- Design Name: +-- Module Name: uart - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +------------------------------------------------------------------------------ +-- UART +-- Implements a universal asynchronous receiver transmitter +------------------------------------------------------------------------------- +-- clock +-- Input clock, must match frequency value given on clock_frequency +-- generic input. +-- reset +-- Synchronous reset. +-- data_stream_in +-- Input data bus for bytes to transmit. +-- data_stream_in_stb +-- Input strobe to qualify the input data bus. +-- data_stream_in_ack +-- Output acknowledge to indicate the UART has begun sending the byte +-- provided on the data_stream_in port. +-- data_stream_in_done +-- Output pulse che arriva quando fine tx +-- data_stream_out +-- Data output port for received bytes. +-- data_stream_out_stb +-- Output strobe to qualify the received byte. Will be valid for one clock +-- cycle only. +-- tx +-- Serial transmit. +-- rx +-- Serial receive +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity UART_Engine is + generic ( + BAUD_RATE : integer range 110 to 2000000; + CLOCK_FREQUENCY : positive + ); + port ( + clock : in std_logic; + reset : in std_logic; + data_stream_in : in std_logic_vector(7 downto 0); + data_stream_in_stb : in std_logic; + data_stream_in_ack : out std_logic; + data_stream_in_done : out std_logic; + data_stream_out : out std_logic_vector(7 downto 0); + data_stream_out_stb : out std_logic; + tx : out std_logic; + rx : in std_logic + ); +end UART_Engine; + +architecture rtl of UART_Engine is + --------------------------------------------------------------------------- + -- Baud generation constants + --------------------------------------------------------------------------- + constant c_tx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE))); + constant c_rx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE * 16))); + --------------------------------------------------------------------------- + -- Baud generation signals + --------------------------------------------------------------------------- + signal tx_baud_counter : integer range 0 to c_tx_div-1 := 0; + signal tx_baud_tick : std_logic := '0'; + signal rx_baud_counter : integer range 0 to c_rx_div-1 := 0; + signal rx_baud_tick : std_logic := '0'; + --------------------------------------------------------------------------- + -- Transmitter signals + --------------------------------------------------------------------------- + type uart_tx_states is ( + tx_send_start_bit, + tx_send_data, + tx_send_stop_bit + ); + signal uart_tx_state : uart_tx_states := tx_send_start_bit; + signal uart_tx_data_vec : std_logic_vector(7 downto 0) := (others => '0'); + signal uart_tx_data : std_logic := '1'; + signal uart_tx_count : unsigned(2 downto 0) := (others => '0'); + signal uart_rx_data_in_ack : std_logic := '0'; + signal uart_rx_data_in_done : std_logic := '0'; + --------------------------------------------------------------------------- + -- Receiver signals + --------------------------------------------------------------------------- + type uart_rx_states is ( + rx_get_start_bit, + rx_get_data, + rx_get_stop_bit + ); + signal uart_rx_state : uart_rx_states := rx_get_start_bit; + signal uart_rx_bit : std_logic := '1'; + signal uart_rx_data_vec : std_logic_vector(7 downto 0) := (others => '0'); + signal uart_rx_data_sr : std_logic_vector(1 downto 0) := (others => '1'); + signal uart_rx_filter : unsigned(1 downto 0) := (others => '1'); + signal uart_rx_count : unsigned(2 downto 0) := (others => '0'); + signal uart_rx_data_out_stb : std_logic := '0'; + signal uart_rx_bit_spacing : unsigned (3 downto 0) := (others => '0'); + signal uart_rx_bit_tick : std_logic := '0'; +begin + -- Connect IO + data_stream_in_ack <= uart_rx_data_in_ack; + data_stream_in_done <= uart_rx_data_in_done; + data_stream_out <= uart_rx_data_vec; + data_stream_out_stb <= uart_rx_data_out_stb; + tx <= uart_tx_data; + --------------------------------------------------------------------------- + -- OVERSAMPLE_CLOCK_DIVIDER + -- generate an oversampled tick (baud * 16) + --------------------------------------------------------------------------- + oversample_clock_divider : process (clock) + begin + if rising_edge (clock) then + if reset = '1' then + rx_baud_counter <= 0; + rx_baud_tick <= '0'; + else + if rx_baud_counter = c_rx_div - 1 then + rx_baud_counter <= 0; + rx_baud_tick <= '1'; + else + rx_baud_counter <= rx_baud_counter + 1; + rx_baud_tick <= '0'; + end if; + end if; + end if; + end process oversample_clock_divider; + --------------------------------------------------------------------------- + -- RXD_SYNCHRONISE + -- Synchronise rxd to the oversampled baud + --------------------------------------------------------------------------- + rxd_synchronise : process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + uart_rx_data_sr <= (others => '1'); + else + if rx_baud_tick = '1' then + uart_rx_data_sr(0) <= rx; + uart_rx_data_sr(1) <= uart_rx_data_sr(0); + end if; + end if; + end if; + end process rxd_synchronise; + --------------------------------------------------------------------------- + -- RXD_FILTER + -- Filter rxd with a 2 bit counter. + --------------------------------------------------------------------------- + rxd_filter : process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + uart_rx_filter <= (others => '1'); + uart_rx_bit <= '1'; + else + if rx_baud_tick = '1' then + -- filter rxd. + if uart_rx_data_sr(1) = '1' and uart_rx_filter < 3 then + uart_rx_filter <= uart_rx_filter + 1; + elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then + uart_rx_filter <= uart_rx_filter - 1; + end if; + -- set the rx bit. + if uart_rx_filter = 3 then + uart_rx_bit <= '1'; + elsif uart_rx_filter = 0 then + uart_rx_bit <= '0'; + end if; + end if; + end if; + end if; + end process rxd_filter; + --------------------------------------------------------------------------- + -- RX_BIT_SPACING + --------------------------------------------------------------------------- + rx_bit_spacing : process (clock) + begin + if rising_edge(clock) then + uart_rx_bit_tick <= '0'; + if rx_baud_tick = '1' then + if uart_rx_bit_spacing = 15 then + uart_rx_bit_tick <= '1'; + uart_rx_bit_spacing <= (others => '0'); + else + uart_rx_bit_spacing <= uart_rx_bit_spacing + 1; + end if; + if uart_rx_state = rx_get_start_bit then + uart_rx_bit_spacing <= (others => '0'); + end if; + end if; + end if; + end process rx_bit_spacing; + --------------------------------------------------------------------------- + -- UART_RECEIVE_DATA + --------------------------------------------------------------------------- + uart_receive_data : process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + uart_rx_state <= rx_get_start_bit; + uart_rx_data_vec <= (others => '0'); + uart_rx_count <= (others => '0'); + uart_rx_data_out_stb <= '0'; + else + uart_rx_data_out_stb <= '0'; + case uart_rx_state is + when rx_get_start_bit => + if rx_baud_tick = '1' and uart_rx_bit = '0' then + uart_rx_state <= rx_get_data; + end if; + when rx_get_data => + if uart_rx_bit_tick = '1' then + uart_rx_data_vec(uart_rx_data_vec'high) + <= uart_rx_bit; + uart_rx_data_vec( + uart_rx_data_vec'high-1 downto 0 + ) <= uart_rx_data_vec( + uart_rx_data_vec'high downto 1 + ); + if uart_rx_count < 7 then + uart_rx_count <= uart_rx_count + 1; + else + uart_rx_count <= (others => '0'); + uart_rx_state <= rx_get_stop_bit; + end if; + end if; + when rx_get_stop_bit => + if uart_rx_bit_tick = '1' then + if uart_rx_bit = '1' then + uart_rx_state <= rx_get_start_bit; + uart_rx_data_out_stb <= '1'; + end if; + end if; + when others => + uart_rx_state <= rx_get_start_bit; + end case; + end if; + end if; + end process uart_receive_data; + --------------------------------------------------------------------------- + -- TX_CLOCK_DIVIDER + -- Generate baud ticks at the required rate based on the input clock + -- frequency and baud rate + --------------------------------------------------------------------------- + tx_clock_divider : process (clock) + begin + if rising_edge (clock) then + if reset = '1' then + tx_baud_counter <= 0; + tx_baud_tick <= '0'; + else + if tx_baud_counter = c_tx_div - 1 then + tx_baud_counter <= 0; + tx_baud_tick <= '1'; + else + tx_baud_counter <= tx_baud_counter + 1; + tx_baud_tick <= '0'; + end if; + end if; + end if; + end process tx_clock_divider; + --------------------------------------------------------------------------- + -- UART_SEND_DATA + -- Get data from data_stream_in and send it one bit at a time upon each + -- baud tick. Send data lsb first. + -- wait 1 tick, send start bit (0), send data 0-7, send stop bit (1) + --------------------------------------------------------------------------- + uart_send_data : process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + uart_tx_data <= '1'; + uart_tx_data_vec <= (others => '0'); + uart_tx_count <= (others => '0'); + uart_tx_state <= tx_send_start_bit; + uart_rx_data_in_ack <= '0'; + uart_rx_data_in_done <= '0'; + else + uart_rx_data_in_ack <= '0'; + uart_rx_data_in_done <= '0'; --new + case uart_tx_state is + when tx_send_start_bit => + if tx_baud_tick = '1' and data_stream_in_stb = '1' then + uart_tx_data <= '0'; + uart_tx_state <= tx_send_data; + uart_tx_count <= (others => '0'); + uart_rx_data_in_ack <= '1'; + uart_tx_data_vec <= data_stream_in; + end if; + when tx_send_data => + if tx_baud_tick = '1' then + uart_tx_data <= uart_tx_data_vec(0); + uart_tx_data_vec( + uart_tx_data_vec'high-1 downto 0 + ) <= uart_tx_data_vec( + uart_tx_data_vec'high downto 1 + ); + if uart_tx_count < 7 then + uart_tx_count <= uart_tx_count + 1; + else + uart_tx_count <= (others => '0'); + uart_tx_state <= tx_send_stop_bit; + end if; + end if; + when tx_send_stop_bit => + if tx_baud_tick = '1' then + uart_tx_data <= '1'; + uart_tx_state <= tx_send_start_bit; + uart_rx_data_in_done <= '1'; --new + end if; + when others => + uart_tx_data <= '1'; + uart_tx_state <= tx_send_start_bit; + end case; + end if; + end if; + end process uart_send_data; +end rtl; diff --git a/LAB3/ip/AXI4-Stream_UART/hdl/UART_Manager.vhd b/LAB3/ip/AXI4-Stream_UART/hdl/UART_Manager.vhd new file mode 100644 index 0000000..5ab7704 --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/hdl/UART_Manager.vhd @@ -0,0 +1,238 @@ + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ---- * ) ---- + ----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ---- + ---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ---- + ----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ---- + ----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ---- + ---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ---- + ---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ---- + ---- |___/ |___/ ---- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +---- _____ _ ___ __ _ _ _ __ _ ---- +---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ---- +---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ---- +---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ---- +---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ---- +----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ---- +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------ + +-------------------------------------DESCRIPTION------------------------------------------ +------------------------------------------------------------------------------------------ +-- Modulo di più basso livello per la gestione dei dati tra FIFO in e FIFO out ed il -- +-- modulo FTDI 2232H in modalita FT245 Asynchronous. La priorità è data ai dati in -- +-- arrivo dal PC verso FPGA. -- +-- Il clock in ingresso deve avere un periodo di 10 ns per garantire i tempi -- +-- rischiesti dal 2232H -- +------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------ + +library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + +entity UART_Manager is + generic( + UART_BAUD_RATE : positive; + UART_CLOCK_FREQUENCY : positive --The associated clock frequency + ); + Port ( + ---------Global--------- + clk_uart : IN STD_LOGIC; + reset : IN STD_LOGIC; + ------------------------ + + ---------Connessioni comunicazione UART----------- + UART_TX : OUT STD_LOGIC; + UART_RX : IN STD_LOGIC; + --------------------------------------------------- + + ------------FIFO_DATA_RX (8bit)------------- + FIFO_DATA_RX_rst : OUT STD_LOGIC; + FIFO_DATA_RX_clk : OUT STD_LOGIC; + FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_RX_wr_en : OUT STD_LOGIC; + FIFO_DATA_RX_full : IN STD_LOGIC; + FIFO_DATA_RX_almost_full : IN STD_LOGIC; + -------------------------------------------- + + ------------FIFO_DATA_TX (8bit)------------- + --FIFO_DATA_RX_rst : OUT STD_LOGIC; + FIFO_DATA_TX_clk : OUT STD_LOGIC; + FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0); + FIFO_DATA_TX_rd_en : OUT STD_LOGIC; + FIFO_DATA_TX_empty : IN STD_LOGIC; + FIFO_DATA_TX_almost_empty : IN STD_LOGIC + -------------------------------------------- + ); +end UART_Manager; + +architecture Behavioral of UART_Manager is + + -------------------COMPONENT------------------ + COMPONENT UART_engine + GENERIC( + BAUD_RATE : positive; + CLOCK_FREQUENCY : positive + ); + PORT( + --SYSTEM UART + clock : IN std_logic; + reset : IN std_logic; + + -- FPGA-->PC + data_stream_in : IN std_logic_vector(7 downto 0); + data_stream_in_stb : IN std_logic; + data_stream_in_ack : OUT std_logic; + data_stream_in_done : OUT std_logic; + tx : OUT std_logic; + + -- PC-->FPGA + data_stream_out : OUT std_logic_vector(7 downto 0); + data_stream_out_stb : OUT std_logic; + rx : IN std_logic + + ); + END COMPONENT; + ---------------------------------------------- + + --------------------SIGNALS------------------- + signal state : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"00"; + + --TX:fromFPGAtoPC + signal data_stream_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0'); + signal data_stream_in_stb : STD_LOGIC := '0'; + signal data_stream_in_ack : STD_LOGIC := '0'; + signal data_stream_in_done : STD_LOGIC := '0'; + + signal state_TX : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF"; + + --RX:fromPCtoFPGA + signal data_stream_out : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0'); + signal data_stream_out_stb : STD_LOGIC := '0'; + ---------------------------------------------- + +begin + + Inst_uart: UART_engine + GENERIC MAP ( + BAUD_RATE => UART_BAUD_RATE, + CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY + ) + PORT MAP( + clock => clk_uart, + reset => reset, + + -- FPGA-->PC + data_stream_in => data_stream_in, --byte FPGA->PC, (in) + data_stream_in_stb => data_stream_in_stb, --'1' per 1 clock inizia la fase di trasmisisone a PC di data_stream_in (in) + data_stream_in_ack => data_stream_in_ack, --'1' per 1 clock vuol dire che START TX (data_stream_in_stb='1') è stata capita (in) + data_stream_in_done => data_stream_in_done, --'1' indica la fine della trasmisione (out) + tx => UART_TX, + + -- PC-->FPGA + data_stream_out => data_stream_out, --byte PC->FPGA, (out) + data_stream_out_stb => data_stream_out_stb, --'1' per 1 clock indica che su data_stream_out c'è un nuovo dato (out) +-- data_stream_out => FIFO_RX_din, +-- data_stream_out_stb => FIFO_RX_wr_en, + rx => UART_RX + + ); + + fromFPGAtoPC : process(clk_uart, reset) + begin + if (reset = '1') then + state_TX <= x"00"; + --UART + data_stream_in <= (others => '0'); + data_stream_in_stb <= '0'; + --FIFO_TX + FIFO_DATA_TX_rd_en <= '0'; + + elsif rising_edge(clk_uart) then + case state_TX is + + when x"FF" => + if(reset = '0') then + state_TX <= x"00"; + else + state_TX <= x"FF"; + end if; + --UART + data_stream_in <= (others => '0'); + data_stream_in_stb <= '0'; + --FIFO_TX + FIFO_DATA_TX_rd_en <= '0'; + + + when x"00" => + FIFO_DATA_TX_rd_en <= '0'; + data_stream_in_stb <= '0'; + + if (FIFO_DATA_TX_empty = '0') then --nessun dato da trasmettere al PC + state_TX <= x"01"; --si hanno dati in FIFO TX da passare al PC + FIFO_DATA_TX_rd_en <= '1'; --abilita lettura FIFO + data_stream_in <= FIFO_DATA_TX_dout; --dai alla UART il byte in uscita dalla fifo già pronto + data_stream_in_stb <= '1'; --abilita TX della UART + end if; + + + when x"01" => + FIFO_DATA_TX_rd_en <= '0'; --blocca la lettura FIFO + --tieni data_stream_in_stb attivo finche la UART non inizia a trasferire data_stream_in_ack='0' + if (data_stream_in_ack = '1') then + state_TX <= x"02"; + data_stream_in_stb <= '0'; + end if; + + + when x"02" => + -- data_stream_in_done = '1' significa fin trasmisisone UART + if (data_stream_in_done = '1') then + state_TX <= x"00"; + end if; + + + when others => + state_TX <= x"00"; + + + end case; + end if; + end process; + + + + fromPCtoFPGA : process(clk_uart, reset) + begin + if (reset = '1') then + FIFO_DATA_RX_din <= (others => '0'); + FIFO_DATA_RX_wr_en <= '0'; + + elsif rising_edge(clk_uart) then + FIFO_DATA_RX_wr_en <= '0'; + if (data_stream_out_stb = '1') then --arrivato nuovo dato sulla UART, caricalo in FIGO RX + FIFO_DATA_RX_wr_en <= '1'; + FIFO_DATA_RX_din <= data_stream_out; + end if; + end if; + + end process; + + --------------------ASSIGMENT------------------ + FIFO_DATA_RX_clk <= clk_uart; + FIFO_DATA_TX_clk <= clk_uart; + + FIFO_DATA_RX_rst <= reset; + ----------------------------------------------- + +end Behavioral; + diff --git a/LAB3/ip/AXI4-Stream_UART/utils/board/board.xit b/LAB3/ip/AXI4-Stream_UART/utils/board/board.xit new file mode 100644 index 0000000..1301341 --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/utils/board/board.xit @@ -0,0 +1,17 @@ +package require xilinx::board 1.0 +namespace import ::xilinx::board::* + +set instname [current_inst] +set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc] +puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n" +if { [get_project_property BOARD] == "" } { + close_ipfile $f_xdc + return +} + +set board_if [get_property PARAM_VALUE.UART_BOARD_INTERFACE] +if { $board_if ne "Custom"} { + board_add_port_constraints $f_xdc $board_if TxD UART_TX + board_add_port_constraints $f_xdc $board_if RxD UART_RX +} +close_ipfile $f_xdc diff --git a/LAB3/ip/AXI4-Stream_UART/vv_index.xml b/LAB3/ip/AXI4-Stream_UART/vv_index.xml new file mode 100644 index 0000000..c5fdae8 --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/vv_index.xml @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/LAB3/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_0.tcl b/LAB3/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_0.tcl new file mode 100644 index 0000000..2dbc0c8 --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_0.tcl @@ -0,0 +1,85 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Settings [ipgui::add_page $IPINST -name "Settings"] + ipgui::add_param $IPINST -name "UART_BAUD_RATE" -parent ${Settings} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } { + # Procedure called to update C_M00_AXIS_RX_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } { + # Procedure called to validate C_M00_AXIS_RX_TDATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } { + # Procedure called to update C_S00_AXIS_TX_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } { + # Procedure called to validate C_S00_AXIS_TX_TDATA_WIDTH + return true +} + +proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } { + # Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } { + # Procedure called to validate UART_BAUD_RATE + return true +} + +proc update_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } { + # Procedure called to update UART_CLOCK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } { + # Procedure called to validate UART_CLOCK_FREQUENCY + return true +} + +proc update_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } { + # Procedure called to update USE_BOARD_FLOW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } { + # Procedure called to validate USE_BOARD_FLOW + return true +} + +proc update_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } { + # Procedure called to update UART_BOARD_INTERFACE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } { + # Procedure called to validate UART_BOARD_INTERFACE + return true +} + + +proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE} +} + +proc update_MODELPARAM_VALUE.UART_CLOCK_FREQUENCY { MODELPARAM_VALUE.UART_CLOCK_FREQUENCY PARAM_VALUE.UART_CLOCK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.UART_CLOCK_FREQUENCY}] ${MODELPARAM_VALUE.UART_CLOCK_FREQUENCY} +} + +proc update_MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH} +} + diff --git a/LAB3/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_1.tcl b/LAB3/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_1.tcl new file mode 100644 index 0000000..2dbc0c8 --- /dev/null +++ b/LAB3/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_1.tcl @@ -0,0 +1,85 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Settings [ipgui::add_page $IPINST -name "Settings"] + ipgui::add_param $IPINST -name "UART_BAUD_RATE" -parent ${Settings} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } { + # Procedure called to update C_M00_AXIS_RX_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } { + # Procedure called to validate C_M00_AXIS_RX_TDATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } { + # Procedure called to update C_S00_AXIS_TX_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } { + # Procedure called to validate C_S00_AXIS_TX_TDATA_WIDTH + return true +} + +proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } { + # Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } { + # Procedure called to validate UART_BAUD_RATE + return true +} + +proc update_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } { + # Procedure called to update UART_CLOCK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } { + # Procedure called to validate UART_CLOCK_FREQUENCY + return true +} + +proc update_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } { + # Procedure called to update USE_BOARD_FLOW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } { + # Procedure called to validate USE_BOARD_FLOW + return true +} + +proc update_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } { + # Procedure called to update UART_BOARD_INTERFACE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } { + # Procedure called to validate UART_BOARD_INTERFACE + return true +} + + +proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE} +} + +proc update_MODELPARAM_VALUE.UART_CLOCK_FREQUENCY { MODELPARAM_VALUE.UART_CLOCK_FREQUENCY PARAM_VALUE.UART_CLOCK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.UART_CLOCK_FREQUENCY}] ${MODELPARAM_VALUE.UART_CLOCK_FREQUENCY} +} + +proc update_MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH} +} + diff --git a/LAB3/vivado/diligent_jstk/diligent_jstk.xpr b/LAB3/vivado/diligent_jstk/diligent_jstk.xpr new file mode 100644 index 0000000..68f7553 --- /dev/null +++ b/LAB3/vivado/diligent_jstk/diligent_jstk.xpr @@ -0,0 +1,228 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/LAB3/vivado/loopback_I2S/loopback_I2S.xpr b/LAB3/vivado/loopback_I2S/loopback_I2S.xpr new file mode 100644 index 0000000..93bfee1 --- /dev/null +++ b/LAB3/vivado/loopback_I2S/loopback_I2S.xpr @@ -0,0 +1,216 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + +