diff --git a/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd new file mode 100644 index 0000000..bd7c9d5 --- /dev/null +++ b/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd @@ -0,0 +1,83 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07.03.2025 15:23:11 +-- Design Name: +-- Module Name: PulseWidthModulator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PulseWidthModulator is + Generic( + BIT_LENGTH : INTEGER RANGE 1 to 16 := 8; + T_ON_INIT : POSITIVE := 64; + PERIOD_INIT : POSITIVE := 128; + PWM_INIT : STD_LOGIC := '0' + ); + Port ( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + + Ton : IN std_logic_vector(BIT_LENGTH-1 downto 0); + Period : IN std_logic_vector(BIT_LENGTH-1 downto 0); + PWM : OUT std_logic + ); + end PulseWidthModulator; + +architecture Behavioral of PulseWidthModulator is + signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0'); + signal pwm_out : std_logic; +begin + + process(clk, reset) + begin + if reset = '1' then + counter <= (others => '0'); + pwm_out <= '0'; -- Assicura PWM spento al reset + elsif rising_edge(clk) then + if counter = unsigned(period) then + counter <= (others => '0'); -- Reset counter + else + counter <= counter + 1; -- Incrementa il counter + end if; + + -- Accendi il PWM all'inizio di ogni ciclo + if counter = 0 then + pwm_out <= '1'; + end if; + + -- Spegni il PWM quando il contatore raggiunge Ton + if counter = unsigned(Ton) then + pwm_out <= '0'; + end if; + end if; + end process; + + PWM <= pwm_out; -- Output PWM + +end Behavioral; + diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd new file mode 100644 index 0000000..af89a1a --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd @@ -0,0 +1,56 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03.03.2025 14:49:43 +-- Design Name: +-- Module Name: ShiftRegister_v0 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftRegister_v0 is + Port ( reset : in STD_LOGIC; + clk : in STD_LOGIC; + din : in STD_LOGIC; + dout : out STD_LOGIC); +end ShiftRegister_v0; + +architecture Behavioral of ShiftRegister_v0 is + signal sr : std_logic := '0'; +begin + + process(clk, reset) + begin + if reset = '1' then + sr <= '0'; + elsif rising_edge(clk) then + sr <= din; + end if; + end process; + + dout <= sr; + +end Behavioral; diff --git a/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd new file mode 100644 index 0000000..d2bff85 --- /dev/null +++ b/LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd @@ -0,0 +1,56 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03.03.2025 14:21:16 +-- Design Name: +-- Module Name: shift_register_v0 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity shift_register_v0 is + Port ( reset : in STD_LOGIC; + clk : in STD_LOGIC; + din : in STD_LOGIC; + dout : out STD_LOGIC); +end shift_register_v0; + +architecture Behavioral of shift_register_v0 is + signal sr : std_logic := '0'; +begin + + process(clk, reset) + begin + if reset = '1' then + sr <= '0'; + elsif rising_edge(clk) then + sr <= din; + end if; + end process; + + dout <= sr; + +end Behavioral; diff --git a/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd new file mode 100644 index 0000000..a831d87 --- /dev/null +++ b/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd @@ -0,0 +1,62 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03.03.2025 15:06:26 +-- Design Name: +-- Module Name: ShiftRegister_v1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftRegister_v1 is + Generic ( + SR_DEPTH : POSITIVE := 4; + SR_INIT : STD_LOGIC := '0' + ); + Port ( + reset : in STD_LOGIC; + clk : in STD_LOGIC; + din : in STD_LOGIC; + dout : out STD_LOGIC + ); +end ShiftRegister_v1; + +architecture Behavioral of ShiftRegister_v1 is + signal sr : STD_LOGIC_VECTOR(SR_DEPTH-1 DOWNTO 0) := (others => '0'); +begin + + process(clk, reset) + begin + if reset = '1' then + sr <= (others => SR_INIT); + elsif rising_edge(clk) then + sr <= sr(SR_DEPTH-2 DOWNTO 0) & din; + end if; + end process; + + dout <= sr(SR_DEPTH-1); + +end Behavioral; diff --git a/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd new file mode 100644 index 0000000..8f3810e --- /dev/null +++ b/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd @@ -0,0 +1,65 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03.03.2025 15:35:08 +-- Design Name: +-- Module Name: ShiftRegister_v2 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ShiftRegister_v2 is + Generic ( + SR_WIDTH : NATURAL := 8; + SR_DEPTH : POSITIVE := 4; + SR_INIT : STD_LOGIC := '0' + ); + Port ( + reset : in STD_LOGIC; + clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0); + dout : out STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0) + ); +end ShiftRegister_v2; + +architecture Behavioral of ShiftRegister_v2 is + type sr_type is array (SR_DEPTH-1 downto 0) of std_logic_vector(SR_WIDTH-1 downto 0); + + signal sr : sr_type := (others => (others => SR_INIT)); +begin + + process(reset,clk) + begin + if reset = '1' then + sr <= (others => (others => SR_INIT)); + elsif rising_edge(clk) then + sr <= sr(SR_DEPTH-2 downto 0) & din; + end if; + end process; + + dout <= sr(SR_DEPTH-1); + +end Behavioral; diff --git a/LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd b/LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd new file mode 100644 index 0000000..84a5beb --- /dev/null +++ b/LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd @@ -0,0 +1,255 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19.03.2019 18:55:36 +-- Design Name: +-- Module Name: tb_PulseWidthModulator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +---------- DEFAULT LIBRARY --------- +library IEEE; + use IEEE.STD_LOGIC_1164.all; + use IEEE.NUMERIC_STD.ALL; +-- use IEEE.MATH_REAL.all; + +-- use STD.textio.all; +-- use ieee.std_logic_textio.all; + +------------------------------------ + + +---------- OTHERS LIBRARY ---------- +-- NONE +------------------------------------ + +entity tb_PulseWidthModulator is +end tb_PulseWidthModulator; + +architecture Behavioral of tb_PulseWidthModulator is + + ------------------ CONSTANT DECLARATION ------------------------- + + --------- Timing ----------- + constant CLK_PERIOD : TIME := 10 ns; + constant RESET_WND : TIME := 10*CLK_PERIOD; + + constant PWM_WND : TIME := 100 ns; + ---------------------------- + + --- TB Initialiazzations --- + constant TB_CLK_INIT : STD_LOGIC := '0'; + constant TB_RESET_INIT : STD_LOGIC := '1'; + ---------------------------- + + + ------- DUT Generics ------- + constant DUT_BIT_LENGTH : INTEGER RANGE 1 TO 16 := 3; -- Leds used over the 16 in Basys3 + + constant DUT_T_ON_INIT : POSITIVE := 8; -- Init of Ton + constant DUT_PERIOD_INIT : POSITIVE := 16; -- Init of Periof + + constant DUT_PWM_INIT : STD_LOGIC := '1'; -- Init of PWM + ---------------------------- + + + ----------------------------------------------------------------- + + ------ COMPONENT DECLARATION for the Device Under Test (DUT) ------ + + ----------- DUT ----------- + component PulseWidthModulator + Generic( + + BIT_LENGTH : INTEGER RANGE 1 TO 16; -- Leds used over the 16 in Basys3 + + T_ON_INIT : POSITIVE; -- Init of Ton + PERIOD_INIT : POSITIVE; -- Init of Periof + + PWM_INIT : STD_LOGIC -- Init of PWM + ); + Port ( + + ------- Reset/Clock -------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + ---------------------------- + + -------- Duty Cycle ---------- + Ton : IN STD_LOGIC_VECTOR(BIT_LENGTH-1 downto 0); -- clk at PWM = '1' + Period : IN STD_LOGIC_VECTOR(BIT_LENGTH-1 downto 0); -- clk per period of PWM + + PWM : OUT STD_LOGIC -- PWM signal + ---------------------------- + + ); + end component; + + ---------------------------- + + + ------------------------------------------------------------------ + + + + + --------------------- SIGNALS DECLARATION ----------------------- + + + ------- Clock/Reset ------- + signal reset : STD_LOGIC := TB_RESET_INIT; + signal clk : STD_LOGIC := TB_CLK_INIT; + ---------------------------- + + + + -------- Duty Cycle ---------- + signal dut_Ton : STD_LOGIC_VECTOR(DUT_BIT_LENGTH-1 downto 0); -- clk at PWM = '1' + signal dut_Period : STD_LOGIC_VECTOR(DUT_BIT_LENGTH-1 downto 0); -- clk per period of PWM + + signal dut_PWM : STD_LOGIC; -- PWM signal + ---------------------------- + + ---------------------------------------------------------------- + + + + +begin + + + --------------------- COMPONENTS DUT WRAPPING -------------------- + + ----------- DUT ------------ + dut_PulseWidthModulator : PulseWidthModulator + Generic Map( + + BIT_LENGTH => DUT_BIT_LENGTH, + + T_ON_INIT => DUT_T_ON_INIT, + PERIOD_INIT => DUT_PERIOD_INIT, + + PWM_INIT => DUT_PWM_INIT + + ) + Port Map( + + ------- Reset/Clock -------- + reset => reset, + clk => clk, + ---------------------------- + + + -------- Duty Cycle ---------- + Ton => dut_Ton, + Period => dut_Period, + + PWM => dut_PWM + ---------------------------- + + ); + ---------------------------- + + ---------------------------- + + + + ------------------------------------------------------------------- + + + --------------------- TEST BENCH DATA FLOW ----------------------- + + ---------- clock ---------- + clk <= not clk after CLK_PERIOD/2; + ---------------------------- + + ------------------------------------------------------------------- + + + ---------------------- TEST BENCH PROCESS ------------------------- + + + ---- Clock Process -------- + -- clk_wave :process + -- begin + -- clk <= CLK_PERIOD; + -- wait for CLK_PERIOD/2; + + -- clk <= not clk; + -- wait for CLK_PERIOD/2; + -- end process; + -------------------------- + + + ----- Reset Process -------- + reset_wave :process + begin + reset <= TB_RESET_INIT; + wait for RESET_WND; + + reset <= not reset; + wait; + end process; + ---------------------------- + + + ------ Stimulus process ------- + + stim_proc: process + begin + + -- waiting the reset wave + + dut_Ton <= std_logic_vector(to_unsigned(0,DUT_BIT_LENGTH)); + dut_Period <= std_logic_vector(to_unsigned(0,DUT_BIT_LENGTH)); + wait for RESET_WND; + + + -- Start + for I in 0 to 2**DUT_BIT_LENGTH-1 loop + + dut_Period <= std_logic_vector(to_unsigned(I,DUT_BIT_LENGTH)); + + for J in 0 to 2**DUT_BIT_LENGTH-1 loop + + dut_Ton <= std_logic_vector(to_unsigned(J,DUT_BIT_LENGTH)); + + + wait for PWM_WND; + + end loop; + end loop; + + + dut_Ton <= std_logic_vector(to_unsigned(2**DUT_BIT_LENGTH-1,DUT_BIT_LENGTH)); + dut_Period <= std_logic_vector(to_unsigned(2**DUT_BIT_LENGTH-2,DUT_BIT_LENGTH)); + wait for PWM_WND; + + -- Stop + wait; + + + -------------------------- + + wait; + end process; + ---------------------------- + + ------------------------------------------------------------------- + + + + +end Behavioral; diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd new file mode 100644 index 0000000..fced822 --- /dev/null +++ b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd @@ -0,0 +1,181 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07.03.2019 12:46:18 +-- Design Name: +-- Module Name: tb_ShiftRegister_v0 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values + use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity tb_ShiftRegister_v0 is +end tb_ShiftRegister_v0; + +architecture Behavioral of tb_ShiftRegister_v0 is + + ------------------------ Constant Declaration ------------------------- + + -- Constant For Test Bench (TB) -- + constant RESET_ON : STD_LOGIC := '1'; + + constant CLK_PERIOD : time := 10 ns; + constant RESET_WND : time := 100 ns; + ---------------------------------- + + + ---------------------------------------------------------------------- + + + ----------------- Device Under Test (DUT) Declaration ---------------- + + ------------ DUT v0 -------------- + COMPONENT ShiftRegister_v0 + Port ( + + ---------- Reset/Clock ---------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + --------------------------------- + + ------------- Data -------------- + din : IN STD_LOGIC; + dout : OUT STD_LOGIC + --------------------------------- + + ); + END COMPONENT; + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + ------------------------- Signal Declaration ------------------------- + + ---------- Reset/Clock ---------- + signal reset : STD_LOGIC := RESET_ON; + signal clk : STD_LOGIC := '1'; + --------------------------------- + + + -------- ShiftRegister_v0 ------- + signal dut0_din : STD_LOGIC := '0'; + signal dut0_dout : STD_LOGIC; + --------------------------------- + + ---------------------------------------------------------------------- + + + +begin + + + + + + + ------------------- Device Under Test (DUT) Wrapper ------------------ + + ------------ DUT v0 -------------- + dut0_ShiftRegister_v0 : ShiftRegister_v0 + Port Map( + + ---------- Reset/Clock ---------- + reset => reset, + clk => clk, + --------------------------------- + + ------------- Data -------------- + din => dut0_din, + dout => dut0_dout + --------------------------------- + + ); + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + + -------------------------- Signals Generation ------------------------- + + + ------ TB Clk Generation ------- + + clk <= not clk after CLK_PERIOD/2; + --------------------------------- + + + ----- TB Reset Generation ------ + reset_wave : process + begin + + reset <= '1'; + wait for RESET_WND; + + reset <= '0'; + wait; + + end process; + --------------------------------- + + + + -- TB din pattern Generation --- + dut0_din_pattern : process + begin + + -- wait the reset window + dut0_din <= '0'; + wait for RESET_WND; + + -- Start + dut0_din <= '0'; + wait for CLK_PERIOD; + + dut0_din <= '1'; + wait for 4*CLK_PERIOD; + + dut0_din <= '0'; + wait for 8*CLK_PERIOD; + + -- Etc... + + -- Stop + wait; + + end process; + --------------------------------- + + + ---------------------------------------------------------------------- + + + +end Behavioral; diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd new file mode 100644 index 0000000..8ce09ce --- /dev/null +++ b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd @@ -0,0 +1,195 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07.03.2019 13:27:59 +-- Design Name: +-- Module Name: tb_ShiftRegister_v1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values + use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity tb_ShiftRegister_v1 is +end tb_ShiftRegister_v1; + +architecture Behavioral of tb_ShiftRegister_v1 is + + ------------------------ Constant Declaration ------------------------- + + -- Constant For Test Bench (TB) -- + constant RESET_ON : STD_LOGIC := '1'; + + constant CLK_PERIOD : time := 10 ns; + constant RESET_WND : time := 100 ns; + ---------------------------------- + + ------ Constant For DUT v0 ------ + constant DUT1_SR_DEPTH : POSITIVE := 4; + constant DUT1_SR_INIT : STD_LOGIC := '0'; + ---------------------------------- + + ---------------------------------------------------------------------- + + + ----------------- Device Under Test (DUT) Declaration ---------------- + + ------------ DUT v1 -------------- + COMPONENT ShiftRegister_v1 + Generic( + SR_DEPTH : POSITIVE; + SR_INIT : STD_LOGIC + ); + Port ( + + ---------- Reset/Clock ---------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + --------------------------------- + + ------------- Data -------------- + din : IN STD_LOGIC; + dout : OUT STD_LOGIC + --------------------------------- + + ); + END COMPONENT; + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + ------------------------- Signal Declaration ------------------------- + + ---------- Reset/Clock ---------- + signal reset : STD_LOGIC := RESET_ON; + signal clk : STD_LOGIC := '1'; + --------------------------------- + + + -------- ShiftRegister_v1 ------- + signal dut1_din : STD_LOGIC := '0'; + signal dut1_dout : STD_LOGIC; + --------------------------------- + + ---------------------------------------------------------------------- + + + +begin + + + + + + + ------------------- Device Under Test (DUT) Wrapper ------------------ + + ------------ DUT v1 -------------- + dut1_ShiftRegister_v1 : ShiftRegister_v1 + + Generic Map( + SR_DEPTH => DUT1_SR_DEPTH, + SR_INIT => DUT1_SR_INIT + ) + Port Map( + + ---------- Reset/Clock ---------- + reset => reset, + clk => clk, + --------------------------------- + + ------------- Data -------------- + din => dut1_din, + dout => dut1_dout + --------------------------------- + + ); + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + + -------------------------- Signals Generation ------------------------- + + + ------ TB Clk Generation ------- + + clk <= not clk after CLK_PERIOD/2; + --------------------------------- + + + ----- TB Reset Generation ------ + reset_wave : process + begin + + reset <= '1'; + wait for RESET_WND; + + reset <= '0'; + wait; + + end process; + --------------------------------- + + + + -- TB din pattern Generation --- + dut1_din_pattern : process + begin + + -- wait the reset window + dut1_din <= '0'; + wait for RESET_WND; + + + -- Start + dut1_din <= '0'; + wait for CLK_PERIOD; + + dut1_din <= '1'; + wait for 4*CLK_PERIOD; + + dut1_din <= '0'; + wait for 8*CLK_PERIOD; + + -- Etc... + + -- Stop + wait; + + end process; + --------------------------------- + + + ---------------------------------------------------------------------- + + + +end Behavioral; diff --git a/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd new file mode 100644 index 0000000..bc50b5b --- /dev/null +++ b/LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd @@ -0,0 +1,198 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07.03.2019 16:39:28 +-- Design Name: +-- Module Name: tb_ShiftRegister_v2 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + + +library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values + use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity tb_ShiftRegister_v2 is +end tb_ShiftRegister_v2; + +architecture Behavioral of tb_ShiftRegister_v2 is + + ------------------------ Constant Declaration ------------------------- + + -- Constant For Test Bench (TB) -- + constant RESET_ON : STD_LOGIC := '1'; + + constant CLK_PERIOD : time := 10 ns; + constant RESET_WND : time := 100 ns; + ---------------------------------- + + ------ Constant For DUT v2 ------ + constant DUT2_SR_WIDTH : NATURAL := 8; + constant DUT2_SR_DEPTH : POSITIVE := 4; + constant DUT2_SR_INIT : STD_LOGIC := '0'; + ---------------------------------- + + ---------------------------------------------------------------------- + + + ----------------- Device Under Test (DUT) Declaration ---------------- + + ------------ DUT v2 -------------- + COMPONENT ShiftRegister_v2 + Generic( + SR_WIDTH : NATURAL := 7; + SR_DEPTH : POSITIVE := 4; + SR_INIT : STD_LOGIC := '0' + ); + Port ( + + ---------- Reset/Clock ---------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + --------------------------------- + + ------------- Data -------------- + din : IN STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0); + dout : OUT STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0) + --------------------------------- + + ); + END COMPONENT; + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + ------------------------- Signal Declaration ------------------------- + + ---------- Reset/Clock ---------- + signal reset : STD_LOGIC := RESET_ON; + signal clk : STD_LOGIC := '1'; + --------------------------------- + + + -------- ShiftRegister_v2 ------- + signal dut2_din : STD_LOGIC_VECTOR(DUT2_SR_WIDTH-1 downto 0) := (Others => '0'); + signal dut2_dout : STD_LOGIC_VECTOR(DUT2_SR_WIDTH-1 downto 0); + --------------------------------- + + ---------------------------------------------------------------------- + + + +begin + + + + + + + ------------------- Device Under Test (DUT) Wrapper ------------------ + + ------------ DUT v2 -------------- + dut2_ShiftRegister_v2 : ShiftRegister_v2 + + Generic Map( + SR_WIDTH => DUT2_SR_WIDTH, + SR_DEPTH => DUT2_SR_DEPTH, + SR_INIT => DUT2_SR_INIT + ) + Port Map( + + ---------- Reset/Clock ---------- + reset => reset, + clk => clk, + --------------------------------- + + ------------- Data -------------- + din => dut2_din, + dout => dut2_dout + --------------------------------- + + ); + ---------------------------------- + + + ---------------------------------------------------------------------- + + + + + -------------------------- Signals Generation ------------------------- + + + ------ TB Clk Generation ------- + + clk <= not clk after CLK_PERIOD/2; + --------------------------------- + + + ----- TB Reset Generation ------ + reset_wave : process + begin + + reset <= '1'; + wait for RESET_WND; + + reset <= '0'; + wait; + + end process; + --------------------------------- + + + + -- TB din pattern Generation --- + dut2_din_pattern : process + begin + + -- wait the reset window + dut2_din <= (Others => '0'); + wait for RESET_WND; + + -- Start + dut2_din <= (Others => '0'); + wait for CLK_PERIOD; + + dut2_din <= (Others => '1'); + wait for 4*CLK_PERIOD; + + dut2_din <= (Others => '0'); + wait for 8*CLK_PERIOD; + + -- Etc... + + -- Stop + wait; + + end process; + --------------------------------- + + + ---------------------------------------------------------------------- + + + +end Behavioral; diff --git a/LAB1/basys3_master.xdc b/LAB1/basys3_master.xdc new file mode 100644 index 0000000..58bfb18 --- /dev/null +++ b/LAB1/basys3_master.xdc @@ -0,0 +1,81 @@ +# This file is a general .xdc for the Basys3 rev B board +# To use it in a project: +# - uncomment the lines corresponding to used pins +# - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +# Clock signal +set_property PACKAGE_PIN W5 [get_ports clk] + set_property IOSTANDARD LVCMOS33 [get_ports clk] + create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk] + +# Reset signal +set_property PACKAGE_PIN U18 [get_ports reset] + set_property IOSTANDARD LVCMOS33 [get_ports reset] + +# Switches +set_property PACKAGE_PIN V17 [get_ports {sw[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +set_property PACKAGE_PIN V16 [get_ports {sw[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +set_property PACKAGE_PIN W16 [get_ports {sw[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +set_property PACKAGE_PIN W17 [get_ports {sw[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +set_property PACKAGE_PIN W15 [get_ports {sw[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +set_property PACKAGE_PIN V15 [get_ports {sw[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +set_property PACKAGE_PIN W14 [get_ports {sw[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +set_property PACKAGE_PIN W13 [get_ports {sw[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +set_property PACKAGE_PIN V2 [get_ports {sw[8]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +set_property PACKAGE_PIN T3 [get_ports {sw[9]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +set_property PACKAGE_PIN T2 [get_ports {sw[10]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +set_property PACKAGE_PIN R3 [get_ports {sw[11]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +set_property PACKAGE_PIN W2 [get_ports {sw[12]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +set_property PACKAGE_PIN U1 [get_ports {sw[13]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +set_property PACKAGE_PIN T1 [get_ports {sw[14]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +set_property PACKAGE_PIN R2 [get_ports {sw[15]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + +# LEDs +set_property PACKAGE_PIN U16 [get_ports {led[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +set_property PACKAGE_PIN E19 [get_ports {led[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +set_property PACKAGE_PIN U19 [get_ports {led[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +set_property PACKAGE_PIN V19 [get_ports {led[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +set_property PACKAGE_PIN W18 [get_ports {led[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +set_property PACKAGE_PIN U15 [get_ports {led[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +set_property PACKAGE_PIN U14 [get_ports {led[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +set_property PACKAGE_PIN V14 [get_ports {led[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +set_property PACKAGE_PIN V13 [get_ports {led[8]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +set_property PACKAGE_PIN V3 [get_ports {led[9]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +set_property PACKAGE_PIN W3 [get_ports {led[10]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +set_property PACKAGE_PIN U3 [get_ports {led[11]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +set_property PACKAGE_PIN P3 [get_ports {led[12]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +set_property PACKAGE_PIN N3 [get_ports {led[13]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +set_property PACKAGE_PIN P1 [get_ports {led[14]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +set_property PACKAGE_PIN L1 [get_ports {led[15]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] \ No newline at end of file diff --git a/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd b/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd new file mode 100644 index 0000000..6382814 --- /dev/null +++ b/LAB1/lab1_kit_car/lab1_kit_car.srcs/sources_1/new/KittCar.vhd @@ -0,0 +1,80 @@ +---------- DEFAULT LIBRARY --------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +------------------------------------ + +ENTITY KittCar IS + GENERIC ( + + CLK_PERIOD_NS : POSITIVE RANGE 1 TO 100 := 10; -- clk period in nanoseconds + MIN_KITT_CAR_STEP_MS : POSITIVE RANGE 1 TO 2000 := 1; -- Minimum step period in milliseconds (i.e., value in milliseconds of Delta_t) + + NUM_OF_SWS : INTEGER RANGE 1 TO 16 := 16; -- Number of input switches + NUM_OF_LEDS : INTEGER RANGE 1 TO 16 := 16 -- Number of output LEDs + + ); + PORT ( + + ------- Reset/Clock -------- + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + ---------------------------- + + -------- LEDs/SWs ---------- + sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0); -- Switches avaiable on Basys3 + led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0) -- LEDs avaiable on Basys3 + ---------------------------- + + ); +END KittCar; + +ARCHITECTURE Behavioral OF KittCar IS + SIGNAL leds_sr : STD_LOGIC_VECTOR(led'RANGE) := (OTHERS => '0'); + SIGNAL counter : UNSIGNED(47 DOWNTO 0) := (OTHERS => '0'); + SIGNAL n_period : POSITIVE RANGE 1 TO 2 ** NUM_OF_SWS := 1; +BEGIN + + PROCESS (clk, reset) + VARIABLE up : STD_LOGIC := '1'; + BEGIN + -- up/down logic + IF leds_sr(NUM_OF_LEDS - 1) = '1' THEN + up := '0'; + ELSIF leds_sr(0) = '1' THEN + up := '1'; + END IF; + + -- Reset the leds + IF unsigned(leds_sr) = 0 THEN + leds_sr <= (0 => '1', OTHERS => '0'); + END IF; + + IF reset = '1' THEN + leds_sr <= (OTHERS => '0'); + up := '1'; + counter <= (OTHERS => '0'); + ELSIF rising_edge(clk) THEN + -- Calculate the number of periods + IF counter >= ((MIN_KITT_CAR_STEP_MS * 1000000) * n_period) THEN + counter <= (OTHERS => '0'); + -- Shift the leds + IF up = '1' THEN + leds_sr <= leds_sr(NUM_OF_LEDS - 2 DOWNTO 0) & '0'; + ELSIF up = '0' THEN + leds_sr <= '0' & leds_sr(NUM_OF_LEDS - 1 DOWNTO 1); + END IF; + ELSE + counter <= counter + to_unsigned(CLK_PERIOD_NS, counter'LENGTH); + END IF; + END IF; + END PROCESS; + + PROCESS (sw) + BEGIN + n_period <= to_integer(unsigned(sw)) + 1; + END PROCESS; + + led <= leds_sr; + +END Behavioral; \ No newline at end of file