From c29b83ba63cead7b5bcda03cc54de817acf0bc0b Mon Sep 17 00:00:00 2001 From: Davide Date: Wed, 19 Mar 2025 17:41:06 +0100 Subject: [PATCH] Enhance README.md with improved structure and clarity --- README.md | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/README.md b/README.md index 4ec86f6..1d1f23c 100644 --- a/README.md +++ b/README.md @@ -1,14 +1,28 @@ -# VHDL Laboratory – Digital Electronic System Design -Politecnico di Milano (2024-2025) +# Digital Electronic System Design +**Politecnico di Milano (2024-2025)** -## Overview -This repository contains VHDL projects and exercises from the **Digital Electronic System Design Laboratory** at **Politecnico di Milano** (Course Code: 054083). The course focuses on **FPGA-based digital design** using VHDL, simulation, synthesis, and implementation. +## 📖 Overview +Welcome to the **Digital Electronic System Design Laboratory** repository! +This repository contains VHDL projects and exercises from the course **Digital Electronic System Design** at **Politecnico di Milano** *(Course Code: 054083)*. -## Tools & Hardware -- **Software**: Xilinx Vivado 2020.2 (WebPack Edition) -- **Hardware**: Digilent Basys 3 (Xilinx Artix-7 FPGA - *XC7A35T-1CPG236C*) +The course focuses on: +- **FPGA-based digital design** +- **VHDL simulation, synthesis, and implementation** -## Course Goals -- Develop practical skills for FPGA-based digital system design -- Implement and test VHDL architectures using Vivado and Basys 3 -- Learn FPGA timing, power, I/O, and memory management \ No newline at end of file +## 🛠️ Tools & Hardware +- **Software**: + - [Xilinx Vivado 2020.2](https://www.xilinx.com/products/design-tools/vivado.html) *(WebPack Edition)* +- **Hardware**: + - [Digilent Basys 3](https://digilent.com/shop/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/) + - FPGA: *Xilinx Artix-7* (**XC7A35TCPG236C-1**) + +## 🎯 Course Goals +- Develop practical skills for **FPGA-based digital system design** +- Implement and test **VHDL architectures** using Vivado and Basys 3 +- Learn about **FPGA timing, power, I/O, and memory management** + + + +## 📬 Contact +For any questions or issues open an issue in this repository. \ No newline at end of file