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Update VHDL and Python files for improved functionality and performance

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- Updated the date in the diligent_jstk_wrapper.vhd file.
- Modified the testbench (tb_digilent_jstk2.vhd) to ensure proper data transmission and added a delay to simulate real response time.
- Adjusted the digilent_jstk2.vhd file to refine the state machine logic for sending and receiving data, including a new IDLE state and improved handling of the SPI communication.
- Enhanced uart_viewer.py to automatically detect the Basys3 board's serial port, improving user experience and reducing configuration errors.
- Updated the Vivado project file (diligent_jstk.xpr) to reflect changes in simulation and synthesis settings, ensuring compatibility with the latest design updates.
This commit is contained in:
Davide Cavagnola
2025-05-15 16:46:09 +02:00
parent aa8d8f3c7c
commit c3967c3124
6 changed files with 495 additions and 192 deletions
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69
LAB3/design/diligent_jstk/diligent_jstk.bd
View File

@@ -5,7 +5,7 @@
"device": "xc7a35tcpg236-1",
"name": "diligent_jstk",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None",
"synth_flow_mode": "Hierarchical",
"tool_version": "2020.2",
"validated": "true"
},
@@ -15,7 +15,8 @@
"AXI4Stream_UART_0": "",
"jstk_uart_bridge_0": "",
"axi4stream_spi_master_0": "",
"digilent_jstk2_0": ""
"digilent_jstk2_0": "",
"system_ila_0": ""
},
"interface_ports": {
"usb_uart": {
@@ -551,25 +552,63 @@
"right": "0"
}
}
},
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"xci_name": "diligent_jstk_system_ila_0_0",
"xci_path": "ip\\diligent_jstk_system_ila_0_0\\diligent_jstk_system_ila_0_0.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_NUM_MONITOR_SLOTS": {
"value": "2"
},
"C_SLOT": {
"value": "1"
},
"C_SLOT_0_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
},
"C_SLOT_1_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
}
},
"interface_ports": {
"SLOT_0_AXIS": {
"mode": "Monitor",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
},
"SLOT_1_AXIS": {
"mode": "Monitor",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
}
}
}
},
"interface_nets": {
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"digilent_jstk2_0_m_axis": {
"interface_ports": [
"digilent_jstk2_0/m_axis",
"axi4stream_spi_master_0/S_AXIS"
"axi4stream_spi_master_0/S_AXIS",
"system_ila_0/SLOT_0_AXIS"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
},
"AXI4Stream_UART_0_UART": {
@@ -583,12 +622,6 @@
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
}
},
"nets": {
@@ -620,7 +653,8 @@
"AXI4Stream_UART_0/m00_axis_rx_aclk",
"jstk_uart_bridge_0/aclk",
"AXI4Stream_UART_0/s00_axis_tx_aclk",
"digilent_jstk2_0/aclk"
"digilent_jstk2_0/aclk",
"system_ila_0/clk"
]
},
"digilent_jstk2_0_btn_trigger": {
@@ -672,7 +706,8 @@
"jstk_uart_bridge_0/aresetn",
"AXI4Stream_UART_0/s00_axis_tx_aresetn",
"axi4stream_spi_master_0/aresetn",
"digilent_jstk2_0/aresetn"
"digilent_jstk2_0/aresetn",
"system_ila_0/resetn"
]
},
"proc_sys_reset_0_peripheral_reset": {