Update VHDL and Python files for improved functionality and performance

- Updated the date in the diligent_jstk_wrapper.vhd file.
- Modified the testbench (tb_digilent_jstk2.vhd) to ensure proper data transmission and added a delay to simulate real response time.
- Adjusted the digilent_jstk2.vhd file to refine the state machine logic for sending and receiving data, including a new IDLE state and improved handling of the SPI communication.
- Enhanced uart_viewer.py to automatically detect the Basys3 board's serial port, improving user experience and reducing configuration errors.
- Updated the Vivado project file (diligent_jstk.xpr) to reflect changes in simulation and synthesis settings, ensuring compatibility with the latest design updates.

LAB3/sim/tb_digilent_jstk2.vhd

@@ -130,23 +130,29 @@ BEGIN
         -- Main loop: wait for CMDSETLEDRGB, then send mem bytes for each byte received
         WHILE TRUE LOOP
             WAIT UNTIL rising_edge(aclk);
+
+            -- Default: s_axis_tvalid low unless sending
+            s_axis_tvalid <= '0';
+
             IF m_axis_tvalid = '1' THEN
                 IF m_axis_tdata = CMDSETLEDRGB THEN
                     send_data := TRUE;
                     mem_idx := 0;
                 END IF;
 
-                IF send_data THEN
-                    IF mem_idx <= 4 THEN
-                        s_axis_tdata <= spi_mem(mem_idx);
-                        s_axis_tvalid <= '1';
-                        mem_idx := mem_idx + 1;
-                    ELSE
+                IF send_data AND mem_idx <= 4 THEN
+                    -- Present data for one cycle when master is ready
+                    s_axis_tdata <= spi_mem(mem_idx);
+                    s_axis_tvalid <= '1';
+                    WAIT UNTIL rising_edge(aclk); -- handshake
+                    s_axis_tvalid <= '0';
+                    mem_idx := mem_idx + 1;
+                    -- Simula il tempo di risposta reale del JSTK2 (1,6 ms per byte)
+                    WAIT FOR 1600 us;
+                    IF mem_idx > 4 THEN
                         send_data := FALSE;
                     END IF;
                 END IF;
-            ELSE
-                s_axis_tvalid <= '0';
             END IF;
         END LOOP;
     END PROCESS;